Texas Instruments EV2011, BQ2011SN-D118 Datasheet

Features

➤

Conservative and repeatable
measurement of available charge
in rechargeable batteries

➤

Designed for portable equipment
such as power tools with high dis

-

charge rates

➤

Designed for battery pack inte

-

gration

-

120µA typical standby current
(self-discharge estimation mode)

-

Small size enables imple­mentations in as little as

1

2

square inch of PCB

➤ Direct drive of LEDs for capacity

display

➤ Self-discharge compensation us-

ing internal temperature sensor

➤ Simple single-wire serial commu-

nications port for subassembly
testing

➤

16-pin narrow SOIC

General Description

The bq2011 Gas Gauge IC is intended
for battery-pack installation to main

­tain an accurate record of available
battery charge. The IC monitors a
voltage drop across a sense resistor
connected in series between the nega

­tive battery terminal and ground to
determine charge and discharge ac

­tivity of the battery. The bq2011 is
designed for systems such as power
tools with very high discharge rates.

Battery self-discharge is estimated
based on an internal timer and tem

­perature sensor. Compensations for
battery temperature and rate of
charge or discharge are applied to
the charge, discharge, and
selfdischarge calculations to provide
available charge information across
a wide range of operating conditions.
Initial battery capacity is set using
the PFC and MODE pins. Actual
battery capacity is automatically
“learned” in the course of a dis­charge cycle from full to empty and
may be displayed depending on the
display mode.

Nominal available charge may be d i

-

rectly indicated using a five-seg

­ment LED display. These segments
are used to indicate graphically the
nominal available charge.

The bq2011 supports a simple single­line bidirectional serial link to an exter

­nal processor (common ground). The
bq2011 outputs battery information in
response to external commands over the
serial link. To support subassembly
testing, the outputs may also be con

­trolled by command. The external proc

­essor may also overwrite some of the
bq2011 gas gauge data registers.

The bq2011 may operate directly
from four cells. With the REF output
and an external transistor, a simple,
inexpensive regulator can be built to
provide V

CC

from a greater number

of cells.

Internal registers include available
charge, temperature, capacity, battery
ID,and battery status.

1

Gas Gauge IC for

High Discharge Rates

2/96 E

Pin Connections Pin Names

1

PN201101.eps

16-Pin Narrow SOIC

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

CC

REF

NC

DQ

RBI

SB

DISP

SR

MODE

SEG

1

SEG

2

SEG

3

SEG

4

SEG

5

PFC

V

SS

MODE Display mode output

SEG

1

LED segment 1

SEG

2

LED segment 2

SEG

3

LED segment 3

SEG

4

LED segment 4

SEG

5

LED segment 5

PFC Programmed full count

selection input

REF Voltage reference output

NC No connect

DQ Serial communications

input/output

RBI Register backup input

SB Battery sense input

DISP

Display control input

SR Sense resistor input

V

CC

3.0–6.5V

V

SS

Negative battery terminal

bq2011

Pin Descriptions

MODE

Display mode output

When left floating, this output selects rela

­tive mode for capacity display. If connected
to the anode of the LEDs to source current,
absolute mode is selected for capacity dis

­play. See Table 1.

SEG

1

–

SEG

5

LED display segment outputs

Each output may activate an LED to sink
the current sourced from MODE, the bat

­tery, or V

CC

.

PFC

Programmed full count selection input

This three-level input pin defines the pro

­grammed full count (PFC) thresholds and
scale selections described in Table 1. The
state of the PFC pin is only read immediate

­ly after a reset condition.

SR

Sense resistor input

The voltage drop (V

SR

) across the sense re-

sistor R

S

is monitored and integrated over
time to interpret charge and discharge activ­ity. The SR input is tied to the low side of
the sense resistor. V

SR>VSS

indicates dis-

charge, and V

SR<VSS

indicates charge. The

effective voltage drop, V

SRO

, as seen by the

bq2011 is V

SR+VOS

(see Table 3).

NC

No connect

DISP

Display control input

DISP

floating allows the LED display to
be active during charge and discharge if
V

SRO

< -1mV (charge) or V

SRO

> 2mV (dis

-

charge). Transitioning DISP

low activates

the display for 4±0.5 seconds.

SB

Secondary battery input

This input monitors the single-cell voltage
potential through a high-impedance resis

­tive divider network for the end-of-discharge
voltage (EDV) threshold and maximum cell
voltage (MCV).

RBI

Register backup input

This input is used to provide backup potential
to the bq2011 registers during periods when
V

CC

≤

3V. A storage capacitor should be con

­nected to RBI.

DQ

Serial I/O pin

This is an open-drain bidirectional pin.

REF

Voltage reference output for regulator

REF provides a voltage reference output for
an optional micro-regulator.

V

CC

Supply voltage input

V

SS

Ground

2

bq2011

Functional Description

General Operation

The bq2011 determines battery capacity by monitoring
the amount of charge input to or removed from a re

­chargeable battery. The bq2011 measures discharge and
charge currents, estimates self-discharge, monitors the
battery for low-battery voltage thresholds, and compen

­sates for temperature and charge/discharge rates. The
charge measurement is made by monitoring the voltage
across a small-value series sense resistor between the
negative battery terminal and ground. The available
battery charge is determined by monitoring this voltage
over time and correcting the measurement for the envi

­ronmental and operating conditions.

Figure 1 shows a typical battery pack application of the
bq2011 using the LED display with absolute mode as a
charge-state indicator. The bq2011 can be configured to
display capacity in either a relative or an absolute dis

­play mode. The relative display mode uses the last
measured discharge capacity of the battery as the bat

­tery “full” reference. The absolute display mode uses the
programmed full count (PFC) as the full reference, forc

­ing each segment of the display to represent a fixed
amount of charge. A push-button display feature is
available for momentarily enabling the LED display.

The bq2011 monitors the charge and discharge currents
as a voltage across a sense resistor (see R

S

in Figure 1).
A filter between the negative battery terminal and the
SR pin may be required if the rate of change of the bat

-

tery current is too great.

3

bq2011

FG201101.eps

PFC

SEG

5

SEG

4

SEG

3

SEG

2

SEG

1

V

SS

DISP

SB

V

CC

REF

bq2011

Gas Gauge IC

MODE

SR

RBI

DQ

V

CC

C1

0.1 F

Q1
ZVNL110A

R

1

R

S

RB

1

RB

2

Load

Charger

Indicates optional.

Directly connect to VCC across 4 cells (4.8V nominal and should not
exceed 6.5V) with a resistor and a Zener diode to limit voltage during charge.
Otherwise, R1, C1, and Q1 are needed for regulation of >4 cells.

Programming resistors and ESD-protection diodes are not shown.

R-C on SR may be required, (application-specific), where the maximum
R should not exceed 20K.

Figure 1. Battery Pack Application Diagram—LED Display,

Absolute Mode

Register Backup

The bq2011 RBI input pin is intended to be used with a
storage capacitor to provide backup potential to the inter

-

nal bq2011 registers when V

CC

momentarily drops below

3.0V. V

CC

is output on RBI when VCCis above 3.0V.

After V

CC

rises above 3.0V, the bq2011 checks the inter

­nal registers for data loss or corruption. If data has
changed, then the NAC and FULCNT registers are
cleared, and the LMD register is loaded with the initial
PFC.

Voltage Thresholds

In conjunction with monitoring VSRfor charge/discharge
currents, the bq2011 monitors the single-cell battery po

­tential through the SB pin. The single-cell voltage po

­tential is determined through a resistor-divider network
per the following equation:

RB
RB

N

1

2

1=−

where N is the number of cells, RB

1

is connected to the

positive battery terminal, and RB

2

is connected to the
negative battery terminal. The single-cell battery volt­age is monitored for the end-of-discharge voltage (EDV)
and for maximum cell voltage (MCV). The EDV thresh­old level is used to determine when the battery has
reached an “empty” state, and the MCV threshold is used
for fault detection during charging. The EDV and MCV
thresholds for the bq2011 are fixed at:

V

EDV

= 0.90V

V

MCV

= 2.00V

During discharge and charge, the bq2011 monitors V

SR

for various thresholds, V

SR1–VSR4

. These thresholds are

used to compensate the charge and discharge rates. Ref

­er to the discharge compensation section for details.
EDV monitoring is disabled if V

SR

> V

SR1

(50mV typical)

and resumes 1 second after V

SR

drops back below V

SR1

.

Reset

The bq2011 recognizes a valid battery whenever VSBis
greater than 0.1V typical. V

SB

rising from below 0.25V
resets the device. Reset can also be accomplished with a
command over the serial port as described in the Reset
Register section.

Temperature

The bq2011 internally determines the temperature in
10°C steps centered from -35°C to +85°C. The tempera

­ture steps are used to adapt charge and discharge rate
compensations, self-discharge counting, and available

charge display translation. The temperature range is
available over the serial port in 10°C increments as
shown below:

Layout Considerations

The bq2011 measures the voltage differential between
the SR and V

SS

pins. VOS(the offset voltage at the SR
pin) is greatly affected by PC board layout. For optimal
results, the PC board layout should follow the strict rule
of a single-point ground return. Sharing high-current
ground with small signal ground causes undesirable
noise on the small signal nodes. Additionally:

n

The capacitors (SB and VCC) should be placed as close
as possible to the SB and V

CC

pins, respectively, and

their paths to V

SS

should be as short as possible. A
high-quality ceramic capacitor of 0.1µf is recommended
for V

CC

.

n

The sense resistor (RS) should be as close as possible
to the bq2011.

n

The R-C on the SR pin should be located as close as
possible to the SR pin. The maximum R should not
exceed 20K.

4

bq2011

TMPGG (hex) Temperature Range

0x < -30°C

1x -30°C to -20°C

2x -20°C to -10°C

3x -10°C to 0°C

4x 0°C to 10°C

5x 10°C to 20°C

6x 20°C to 30°C

7x 30°C to 40°C

8x 40°C to 50°C

9x 50°C to 60°C

Ax 60°C to 70°C

Bx 70°C to 80°C

Cx > 80°C

Gas Gauge Operation

The operational overview diagram in Figure 2 illustrates
the operation of the bq2011. The bq2011 accumulates a
measure of charge and discharge currents, as well as an
estimation of self-discharge. Charge and discharge cur

­rents are temperature and rate compensated, whereas
self-discharge is only temperature compensated.

The main counter, Nominal Available Charge (NAC),
represents the available battery capacity at any given
time. Battery charging increments the NAC register,
while battery discharging and self-discharge decrement
the NAC register and increment the DCR (Discharge
Count Register).

The Discharge Count Register (DCR) is used to update
the Last Measured Discharge (LMD) register only if a
complete battery discharge from full to empty occurs
without any partial battery charges. Therefore, the
bq2011 adapts its capacity determination based on the
actual conditions of discharge.

The battery's initial capacity is equal to the Pro

­grammed Full Count (PFC) shown in Table 1. Until
LMD is updated, NAC counts up to but not beyond this
threshold during subsequent charges. This approach al­lows the gas gauge to be charger-independent and com­patible with any type of charge regime.

1. Last Measured Discharge (LMD) or
learned battery capacity:

LMD is the last measured discharge capacity of the
battery. On initialization (application of V

CC

or bat

­tery replacement), LMD = PFC. During subsequent
discharges, the LMD is updated with the latest
measured capacity in the Discharge Count Register
(DCR) representing a discharge from full to below
EDV. A qualified discharge is necessary for a ca

­pacity transfer from the DCR to the LMD register.
The LMD also serves as the 100% reference thresh

­old used by the relative display mode.

2. Programmed Full Count (PFC) or initial
battery capacity:

The initial LMD and gas gauge rate values are pro

­grammed by using PFC. The PFC also provides the
100% reference for the absolute display mode. The
bq2011 is configured for a given application by se

­lecting a PFC value from Table 1. The correct PFC
may be determined by multiplying the rated bat

­tery capacity in mAh by the sense resistor value:

Battery capacity (mAh)*sense resistor (Ω) =

PFC (mVh)

Selecting a PFC slightly less than the rated capac­ity for absolute mode provides capacity above the
full reference for much of the battery's life.

5

bq2011

FG201104.eps

Temperature

Compensation

Charge
Current

Discharge

Current

Self-Discharge

Timer

Temperature

Translation

Nominal
Available

Charge

(NAC)

Last

Measured

Discharged

(LMD)

Discharge

Count

Register

(DCR)

<

Qualified
Transfer

+

Rate and

Temperature

Compensation

Rate and

Temperature

Compensation

Temperature Step,
Other Data

+

-

Inputs

Main Counters

and Capacity

Reference (LMD)

Outputs

Serial

Port

Chip-Controlled

Available Charge

LED Display

-

+

Rate and

Temperature

Compensation

Figure 2. Operational Overview

Example: Selecting a PFC Value

Given:

Sense resistor = 0.005

Ω

Number of cells = 6
Capacity = 1300mAh, NiCd cells
Current range = 1A to 80A
Relative display mode
Self-discharge =

C

64

Voltage drop over sense resistor = 5mV to 400mV

Therefore:

1300mAh*0.005Ω= 6.5mVh

Select:

PFC = 34304 counts or 6.5mVh
PFC = Z (float)
MODE = not connected

The initial full battery capacity is 6.5mVh
(1300mAh) until the bq2011 “learns” a new capac

­ity with a qualified discharge from full to EDV.

6

bq2011

PFC

Programmed

Full Count (PFC) mVh Scale MODE Pin Display Mode

H 27648 10.5

1

2640

Floating RelativeZ 34304 6.5

1

5280

L 44800 8.5

1

5280

H 42240 8.0

1

5280

Connected to LEDs AbsoluteZ 31744 6.0

1

5280

L 23808 4.5

1

5280

Table 1. bq2011 Programmed Full Count mVh Selections

3. Nominal Available Charge (NAC):

NAC counts up during charge to a maximum value
of LMD and down during discharge and self dis

­charge to 0. NAC is reset to 0 on initialization and
on the first valid charge following discharge to EDV.
To prevent overstatement of charge during periods
of overcharge, NAC stops incrementing when NAC
= LMD.

Note: NAC is set to the value in LMD when SEG

5

is pulled low during a reset.

4. Discharge Count Register (DCR):

The DCR counts up during discharge independent
of NAC and could continue increasing after NAC
has decremented to 0. Prior to NAC = 0 (empty
battery), both discharge and self-discharge incre

­ment the DCR. After NAC = 0, only discharge in

­crements the DCR. The DCR resets to 0 when NAC
= LMD. The DCR does not roll over but stops
counting when it reaches FFFFh.

The DCR value becomes the new LMD value on the
first charge after a valid discharge to V

EDV

if:

n

No valid charge initiations (charges greater than
256 NAC counts; or 0.006 – 0.01C) occurred dur­ing the period between NAC = LMD and EDV
detected.

n

The self-discharge count is not more than 4096
counts (8% to 18% of PFC, specific percentage
threshold determined by PFC).

n

The temperature is≥0°C when the EDV level is
reached during discharge.

The valid discharge flag (VDQ) indicates whether
the present discharge is valid for LMD update.

Charge Counting

Charge activity is detected based on a negative voltage
on the V

SR

input. If charge activity is detected, the

bq2011 increments NAC at a rate proportional to V

SRO

(VSR+VOS) and, if enabled, activates an LED display
if V

SRO

< -1mV. Charge actions increment the NAC af

-

ter compensation for charge rate and temperature.

The bq2011 determines a valid charge activity sustained
at a continuous rate equivalent to V

SRO

< -400µV. A
valid charge equates to a sustained charge activity
greater than 256 NAC counts. Once a valid charge is de

-

tected, charge counting continues until V

SRO

rises

above -400µV.

Discharge Counting

All discharge counts where V

SRO

> 500µV cause the
NAC register to decrement and the DCR to increment.
Exceeding the fast discharge threshold (FDQ) if the rate
is equivalent to V

SRO

> 2mV activates the display, if en

-

abled. The display becomes inactive after V

SRO

falls be

-

low 2mV.

Self-Discharge Estimation

The bq2011 continuously decrements NAC and incre

-

ments DCR for self-discharge based on time and tempera

­ture. The self-discharge count rate is programmed to be a
nominal

1

80

*

NAC rate per day. This is the rate for a bat

­tery whose temperature is between 20°–30°C. The NAC
register cannot be decremented below 0.

Count Compensations

The bq2011 determines fast charge when the NAC up

­dates at a rate of≥2 counts/sec. Charge and discharge
activity is compensated for temperature and charge/dis

­charge rate before updating the NAC and/or DCR. Self­discharge estimation is compensated for temperature
before updating the NAC or DCR.

Charge Compensation

Two charge efficiency factors are used for trickle charge
and fast charge. Fast charge is defined as a rate of
charge resulting in≥2 NAC counts/sec (≥0.15C to 0.32C
depending on PFC selections; see Table 2). The compen­sation defaults to the fast charge factor until the actual
charge rate is determined.

Temperature adapts the charge rate compensation fac

­tors over three ranges between nominal, warm, and hot
temperatures. The compensation factors are shown below.

7

bq2011

Charge

Temperature

Trickle Charge

Compensation

Fast Charge

Compensation

<40°C 0.80 0.95

≥

40°C 0.75 0.90

Discharge Compensation

Corrections for the rate of discharge are made by adjust

-

ing an internal discharge compensation factor. The dis

-

charge factor is based on the dynamically measured V

SR

.

The compensation factors during discharge are:

Temperature compensation during discharge also takes place.
At lower temperatures, the compensation factor increases by

0.05 for each 10°C temperature step below 10°C.

Comp. factor = 1.00 + (0.05*N)

Where N = number of 10°C steps below 10°C and
V

SR

< 50mV.

For example:

T > 10°C: Nominal compensation, N = 0

0°C<T<10°C: N = 1 (i.e.,1.00 becomes 1.05)

-10°C<T<0°C: N = 2 (i.e., 1.00 becomes 1.10)

-20°C<T<-10°C: N = 3 (i.e., 1.00 becomes 1.15)

-20°C<T<-30°C: N = 4 (i.e., 1.00 becomes 1.20)

Self-Discharge Compensation

The self-discharge compensation is programmed for a
nominal rate of

1

80

*

NAC per day. This is the rate for a
battery within the 20–30°C temperature range (TMPGG
= 6x). This rate varies across 8 ranges from <10°C to
>70°C, doubling with each higher temperature step
(10°C). See Table 2

Error Summary

Capacity Inaccurate

The LMD is susceptible to error on initialization or if no up­dates occur. On initialization, the LMD value includes the
error between the programmed full capacity and the actual
capacity. This error is present until a valid discharge oc­curs and LMD is updated (see the DCR description on page

7). The other cause of LMD error is battery wear-out. As
the battery ages, the measured capacity must be adjusted
to account for changes in actual battery capacity.

A Capacity Inaccurate counter (CPI) is maintained and
incremented each time a valid charge occurs and is reset
whenever LMD is updated from the DCR. The counter
does not wrap around but stops counting at 255. The ca

­pacity inaccurate flag (CI) is set if LMD has not been
updated following 64 valid charges.

Current-Sensing Error

Table 3 illustrates the current-sensing error as a func

­tion of V

SR

. A digital filter eliminates charge and

discharge counts to the NAC register when V

SRO(VSR

+

V

OS

) is between -400µV and 500µV.

8

bq2011

Temperature

Range

Self-Discharge Compensation

Typical Rate/Day

< 10°C

NAC

320

10–20°C

NAC

160

20–30°C

NAC

80

30–40°C

NAC

40

40–50°C

NAC

20

50–60°C

NAC

10

60–70°C

NAC

5

> 70°C

NAC

25.

Table 2. Self-Discharge Compensation

Approximate

V

SR

Threshold

Discharge

Compensation

Factor Efficiency

V

SR

< 50 mV 1.00 100%

V

SR1

> 50 mV 1.05 95%

V

SR2

> 100 mV 1.15 85%

V

SR3

> 150 mV 1.25 75%

V

SR4

> 253 mV 1.25 75%

Symbol Parameter Typical Maximum Units Notes

INL

Integrated non-linearity
error

±

2

±

4

%

Add 0.1% per °C above or below 25°C
and 1% per volt above or below 4.25V.

INR

Integrated non­repeatability error

±

1

±

2

%

Measurement repeatability given
similar operating conditions.

Table 3. bq2011 Current-Sensing Errors

Communicating with the bq2011

The bq2011 includes a simple single-pin (DQ plus re

-

turn) serial data interface. A host processor uses the in

-

terface to access various bq2011 registers. Battery char

­acteristics may be easily monitored by adding a single
contact to the battery pack. The open-drain DQ pin on
the bq2011 should be pulled up by the host system, or may
be left floating if the serial interface is not used.

The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2011.
The command directs the bq2011 to either store the next
eight bits of data received to a register specified by the
command byte or output the eight bits of data specified
by the command byte.

The communication protocol is asynchronous return-to­one. Command and data bytes consist of a stream of eight
bits that have a maximum transmission rate of 333
bits/sec. The least-significant bit of a command or data
byte is transmitted first. The protocol is simple enough
that it can be implemented by most host processors using
either polled or interrupt processing. Data input from the
bq2011 may be sampled using the pulse-width capture
timers available on some microcontrollers.

Communication is normally initiated by the host proces­sor sending a BREAK command to the bq2011. A
BREAK is detected when the DQ pin is driven to a
logic-low state for a time, t

B

or greater. The DQ pin
should then be returned to its normal ready-high logic
state for a time, t

BR

. The bq2011 is now ready to receive

a command from the host processor.

The return-to-one data bit frame consists of three distinct
sections. The first section is used to start the transmission
by either the host or the bq2011 taking the DQ pin to a

logic-low state for a period, t

STRH,B

. The next section is the
actual data transmission, where the data should be valid by
a period, t

DSU

, after the negative edge used to start commu

-

nication. The data should be held for a period, t

DV

, to allow

the host or bq2011 to sample the data bit.

The final section is used to stop the transmission by return

­ing the DQ pin to a logic-high state by at least a period,
t

SSU

, after the negative edge used to start communication.

The final logic-high state should be held until a period, t

SV

,
to allow time to ensure that the bit transmission was
stopped properly. The timings for data and break commu

­nication are given in the serial communication timing
specification and illustration sections.

Communication with the bq2011 is always performed
with the least-significant bit being transmitted first.
Figure 3 shows an example of a communication se

­quence to read the bq2011 NAC register.

bq2011 Registers

The bq2011 command and status registers are listed in
Table 4 and described below.

Command Register (CMDR)

The write-only CMDR register is accessed when eight
valid command bits have been received by the bq2011.
The CMDR register contains two fields:

n

W/R bit

n

Command address

The W/R

bit of the command register is used to select
whether the received command is for a read or a write
function.

9

bq2011

TD201101.eps

DQ

Break 0 0 0 0 0 0 1 0 1 0 0 1

Written by Host to bq2011

CMDR = 03h

Received by Host to bq2011

NAC = 65h

LSB MSB LSB MSB

1110

Figure 3. Typical Communication with the bq2011

10

bq2011

Symbol

Register

Name

Loc.

(hex)

Read/

Write

Control Field

7(MSB) 6 5 43210(LSB)

CMDR

Command
register

00h Write W/R

AD6 AD5 AD4 AD3 AD2 AD1 AD0

FLGS1

Primary
status flags
register

01h Read CHGS BRP MCV CI VDQ n/u EDV n/u

TMPGG

Temperature
and gas gauge
register

02h Read TMP3 TMP2 TMP1 TMP0 GG3 GG2 GG1 GG0

NACH

Nominal
available
charge high
byte register

03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0

NACL

Nominal
available
charge low
byte register

17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0

BATID

Battery
identification
register

04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0

LMD

Last meas­ured dis­charge regis

-

ter

05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0

FLGS2

Secondary
status flags
register

06h Read CR DR2 DR1 DR0 n/u n/u n/u OVLD

CPI

Capacity
inaccurate
count register

09h Read CPI7 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 CPI0

OCTL

Output con

-

trol register

0ah Write 1 OC5 OC4 OC3 OC2 OC1 n/u OCE

FULCNT

Full count
register

0bh Read FUL7 FUL6 FUL5 FUL4 FUL3 FUL2 FUL1 FUL0

RST Reset register 39h Write RST 0 0 00000

Note: n/u = not used

Table 4. bq2011 Command and Status Registers

The W/R values are:

Where W/R

is:

0 The bq2011 outputs the requested register

contents specified by the address portion of
CMDR.

1 The following eight bits should be written

to the register specified by the address por

-

tion of CMDR.

The lower seven-bit field of CMDR contains the address
portion of the register to be accessed. Attempts to write
to invalid addresses are ignored.

Primary Status Flags Register (FLGS1)

The read-only FLGS1 register (address=01h) contains
the primary bq2011 flags.

The charge status flag (CHGS) is asserted when a
valid charge rate is detected. Charge rate is deemed
valid when V

SRO

< -400µV. A V

SRO

of greater than-

400µV or discharge activity clears CHGS.

The CHGS values are:

Where CHGS is:

0 Either discharge activity detected or V

SRO

>

-400µV

1V

SRO

< -400µV

The battery replaced flag (BRP) is asserted whenever
the potential on the SB pin (relative to V

SS

), VSB, rises
above 0.1V and determines the internal registers have
been corrupted. The BRP flag is also set when the
bq2011 is reset (see the RST register description). BRP
is latched until either the bq2011 is charged until NAC
= LMD or discharged until EDV is reached. BRP = 1
signifies that the device has been reset.

The BRP values are:

Where BRP is:

0 bq2011 is charged until NAC = LMD or dis

-

charged until the EDV flag is asserted

1 SB rising from below 0.1V, or a serial port

initiated reset has occurred

The maximum cell voltage flag (MCV) is asserted
whenever the potential on the SB pin (relative to V

SS

)is

above 2.0V. The MCV flag is asserted until the condi

-

tion causing MCV is removed.

The MCV values are:

Where MCV is:

0V

SB

< 2.0V

1V

SB

> 2.0V

The capacity inaccurate flag (CI) is used to warn the
user that the battery has been charged a substantial
number of times since LMD has been updated. The CI
flag is asserted on the 64th charge after the last LMD
update or when the bq2011 is reset. The flag is cleared
after an LMD update.

The CI values are:

Where CI is:

0 When LMD is updated with a valid full dis

-

charge or the bq2011 is reset

1 After the 64th valid charge action with no

LMD updates

11

bq2011

FLGS1 Bits

76543 2 1 0

- - MCV - - - - -

FLGS1 Bits

76543 2 1 0

---CI- - - -

FLGS1 Bits

76543 2 1 0

CHGS - -- - - - -

FLGS1 Bits

76543 2 1 0

- BRP - - - - - -

CMDR Bits

765 4 3 2 1 0

- AD6 AD5 AD4 AD3 AD2 AD1

AD0

(LSB)

CMDR Bits

76543 2 1 0

W/R

- -- - - - -

The valid discharge flag (VDQ) is asserted when the
bq2011 is discharged from NAC=LMD. The flag remains
set until either LMD is updated or one of three actions
that can clear VDQ occurs:

n

The self-discharge count register (SDCR) has
exceeded the maximum acceptable value (4096
counts) for an LMD update.

n

A valid charge action equal to 256 NAC counts with
V

SRO

< -400µV.

n

The EDV flag was set at a temperature below 0°C

The VDQ values are:

Where VDQ is:

0 SDCR≥4096, subsequent valid charge ac

­tion detected, or EDV is asserted with the
temperature less than 0°C

1 On first discharge after NAC = LMD

The end-of-discharge warning flag (EDV) warns the
user that the battery is empty. SEG1 blinks at a 4Hz
rate. EDV detection is disabled if V

SR>VSR1

. The EDV

flag is latched until a valid charge has been detected.

The EDV values are:

Where EDV is:

0 Valid charge action detected and V

SB

≥

0.90V

1V

SB

< 0.90V providing that VSR< V

SR1

Temperature and Gas Gauge Register
(TMPGG)

The read-only TMPGG register (address=02h) contains
two data fields. The first field contains the battery tem

­perature. The second field contains the available charge
from the battery.

The bq2011 contains an internal temperature sensor.
The temperature is used to set charge and discharge ef

-

ficiency factors as well as to adjust the self-discharge co

­efficient. The temperature register contents may be
translated as shown below.

The bq2011 calculates the available charge as a function
of NAC, temperature, and a full reference, either LMD
or PFC. The results of the calculation are available via
the display port or the gas gauge field of the TMPGG
register. The register is used to give available capacity
in

1

16

increments from 0 to

15

16

.

12

bq2011

TMPGG Temperature Bits

7 6 5 4 3210

TMP3 TMP2 TMP1 TMP0 - - -

FLGS1 Bits

765 4 3 2 1 0

--- - - -EDV-

TMPGG Gas Gauge Bits

765 4 3 2 1 0

- - - - GG3 GG2 GG1 GG0

FLGS1 Bits

76543 2 1 0

- - - - VDQ - - -

TMP3 TMP2 TMP1 TMP0 Temperature

0000 T < -30°C

0001-30°C < T < -20°C

0010-20°C < T < -10°C

0011-10°C < T < 0°C

01000°C < T < 10°C

010110°C < T < 20°C

011020°C < T < 30°C

011130°C < T < 40°C

100040°C < T < 50°C

100150°C < T < 60°C

101060°C < T < 70°C

101170°C < T < 80°C

1100 T > 80°C

The gas gauge display and the gas gauge portion of the
TMPGG register are adjusted for cold temperature de

-

pendencies. A piece-wise correction is performed as fol

-

lows:

The adjustment between > 0°C and -20°C < T < 0°C has a
4°C hysteresis.

Nominal Available Charge Register (NAC)

The read/write NACH register (address=03h) and the
read-only NACL register (address=17h) are the main
gas gauging registers for the bq2011. The NAC registers
are incremented during charge actions and decremented
during discharge and self-discharge actions. The correc­tion factors for charge/discharge efficiency are applied
automatically to NAC.

On reset, the NACH and NACL registers are cleared to
zero. NACL stops counting when NACH reaches zero.
When the bq2011 detects a valid charge, NACL resets to
zero; writing to the NAC register affects the available

charge counts and, therefore, affects the bq2011 gas
gauge operation.

Battery Identification Register (BATID)

The read/write BATID register (address=04h) is avail

-

able for use by the system to determine the type of bat

­tery pack. The BATID contents are retained as long as
V

CC

is greater than 2V. The contents of BATID have no

effect on the operation of the bq2011. There is no de

­fault setting for this register.

Last Measured Discharge Register (LMD)

LMD is a read/write register (address=05h) that the
bq2011 uses as a measured full reference. The bq2011
adjusts LMD based on the measured discharge capacity
of the battery from full to empty. In this way the bq2011
updates the capacity of the battery. LMD is set to PFC
during a bq2011 reset.

Secondary Status Flags Register (FLGS2)

The read-only FLGS2 register (address=06h) contains
the secondary bq2011 flags.

The charge rate flag (CR) is used to denote the fast
charge regime. Fast charge is assumed whenever a
charge action is initiated. The CR flag remains asserted
if the charge rate does not fall below 2 counts/sec.

The CR values are:

Where CR is:

0 When charge rate falls below 2 counts/sec

1 When charge rate is above 2 counts/sec

The fast charge regime efficiency factors are used when
CR = 1. When CR = 0, the trickle charge efficiency fac

­tors are used. The time to change CR varies due to the
user-selectable count rates.

The discharge rate flags, DR2–0,are bits 6–4.

They are used to determine the present discharge re­gime as follows:

The overload flag (OVLD) is asserted when a discharge
overload is detected, V

SRD

> 50mV. OVLD remains as

­serted as long as the condition persists and is cleared
when V

SRD

< 50mV.

DR2–0 and OVLD are set based on the measurement of the
voltage at the SR pin relative to V

SS

. The rate at which

this measurement is made varies with device activity.

13

bq2011

FLGS2 Bits

76543 2 1 0

CR - - - - - - -

FLGS2 Bits

7 6 5 4 3210

- DR2 DR1 DR0 - - -

DR2 DR1 DR0 VSR(V)

000 V

SR

< 50mV

001

50mV < V

SR

< 100mV

(overload, OVLD=1)

0 1 0 100mV < V

SR

< 150mV

0 1 1 150mV < V

SR

< 253mV

100 V

SRD

> 253mV

Temperature Available Capacity Calculation

> 0°C NAC / “Full Reference”

-20°C < T < 0°C 0.75*NAC / “Full Reference”

< -20°C 0.5*NAC / “Full Reference”

FLGS2 Bits

76543 2 1 0

- - - - - - - OVLD

Full Count Register (FULCNT)

The read-only FULCNT register (address=0bh) provides
the system with a diagnostic of the number of times the
battery has been fully charged (NAC = LMD). The
number of full occurrences can be determined by multiply

-

ing the value in the FULCNT register by 16. Any dis

­charge action other than self-discharge allows detection of
another full occurrence during the next valid charge ac

­tion.

Capacity Inaccurate Count Register (CPI)

The read-only CPI register (address=09h) is used to in

­dicate the number of times a battery has been charged
without an LMD update. Because the capacity of a re

­chargeable battery varies with age and operating condi

­tions, the bq2011 adapts to the changing capacity over
time. A complete discharge from full (NAC=LMD) to
empty (EDV=1) is required to perform an LMD update
assuming there have been no intervening valid charges,
the temperature is greater than or equal to 0°C, and the
self-discharge counter is less than 4096 counts.

The CPI register is incremented every time a valid
charge is detected. The register increments to 255 with­out rolling over. When the contents of CPI are incre­mented to 64, the capacity inaccurate flag, CI, is as­serted in the FLGS1 register. CPI is reset whenever an
update of the LMD register is performed, and the CI flag
is also cleared.

Output Control Register (OCTL)

The write-only OCTL register (address=0ah) provides
the system with a means to check the display connec

­tions for the bq2011. The segment drivers may be over

­written by data from OCTL when the least-significant
bit of OCTL, OCE, is set. The data in bits OC

5–1

of the

OCTL register (see Table 4 on page 10 for details) is out

­put onto the segment pins, SEG

5–1

, respectively if
OCE=1. Whenever OCE is written to 1, the MSB of
OCTL should be set to a 1. The OCE register location
must be cleared to return the bq2011 to normal opera

­tion. OCE may be cleared by either writing the bit to a
logic zero via the serial port or by resetting the bq2011
as explained below. Note: Whenever the OCTL register is
written, the MSB of OCTL should be written to a logic one.

Reset Register (RST)

The reset register (address=39h) provides the means to
perform a software-controlled reset of the device. A full
device reset may be accomplished by first writing LMD
(address = 05h) to 00h and then writing the RST regis

­ter contents from 00h to 80h. Setting any bit other than

the most-significant bit of the RST register is not al

­lowed, and results in improper operation of the bq2011.

Resetting the bq2011 sets the following:

n

LMD = PFC

n

CPI, VDQ, NAC, and OCE = 0 or
NAC = LMD when SEG5 = L

n

CI and BRP = 1

Display

The bq2011 can directly display capacity information
using low-power LEDs. If LEDs are used, the segment
pins should be tied to V

CC

, the battery, or the MODE pin

for programming the bq2011.

The bq2011 displays the battery charge state in either
absolute or relative mode. In relative mode, the battery
charge is represented as a percentage of the LMD. Each
LED segment represents 20% of the LMD.

In absolute mode, each segment represents a fixed
amount of charge, based on the initial PFC. In absolute
mode, each segment represents 20% of the PFC. As the
battery wears out over time, it is possible for the LMD
to be below the initial PFC. In this case, all of the LEDs
may not turn on, representing the reduction in the ac­tual battery capacity.

The capacity display is also adjusted for the present bat­tery temperature. The temperature adjustment reflects
the available capacity at a given temperature but does
not affect the NAC register. The temperature adjust­ments are detailed in the TMPGG register description.

When DISP

is tied to VCC, the SEG

1–5

outputs are inac-

tive. When DISP

is left floating, the display becomes ac

­tive during charge if the NAC registers are counting at a
rate equivalent to V

SRO

< -1mV or fast discharge if the

NAC registers are counting at a rate equivalent to V

SRO

> 2mV. When pulled low, the segment output becomes
active for 4 seconds,±0.5 seconds.

The segment outputs are modulated as two banks, with
segments 1, 3, and 5 alternating with segments 2 and 4.
The segment outputs are modulated at approximately
320Hz, with each bank active for 30% of the period.

SEG

1

blinks at a 4Hz rate whenever VSBhas been de

­tected to be below V

EDV

to indicate a low-battery condi

­tion or NAC is less than 10% of the LMD or PFC, de

­pending on the display mode.

Microregulator

The bq2011 can operate directly from 4 cells. To facilitate
the power supply requirements of the bq2011, an REF out

­put is provided to regulate an external low-threshold n­FET. A micropower source for the bq2011 can be inexpen

­sively built using the FET and an external resistor.

14

bq2011

15

bq2011

Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Unit Notes

V

CC

Relative to V

SS

-0.3 +7.0 V

All other pins Relative to V

SS

-0.3 +7.0 V

V

SR

Relative to V

SS

-0.3 +7.0 V

Minimum 100Ωseries resistor
should be used to protect SR in case
of a shorted battery (see the bq2011
application note for details).

T

OPR

Operating temperature

0 +70 °C Commercial

-40 +85 °C Industrial

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera

-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo

-

sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

DC Voltage Thresholds (T

A

= T

OPR

; V = 3.0 to 6.5V)

Symbol Parameter Minimum Typical Maximum Unit Notes

V

EDV

End-of-discharge warning 0.87 0.90 0.93 V SB

V

SR1

Discharge compensation threshold 20 50 75 mV SR (see note)

V

SR2

Discharge compensation threshold 70 100 125 mV SR (see note)

V

SR3

Discharge compensation threshold 120 150 175 mV SR (see note)

V

SR4

Discharge compensation threshold 220 253 275 mV SR (see note)

V

SRQ

Valid charge - - -400

µ

VVSR+ V

OS

V

SRD

Valid discharge 500 - -

µ

VVSR+ V

OS

V

MCV

Maximum single-cell voltage 1.95 2.0 2.05 V SB

V

BR

Battery removed/replaced - 0.1 0.25 V SB

Note: For proper operation of the threshold detection circuit, VCCmust be at least 1.5V greater than the volt

-

age being measured.

16

bq2011

DC Electrical Characteristics (T

A

= T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

V

CC

Supply voltage 3.0 4.25 6.5 V

V

CC

excursion from < 2.0V to

≥

3.0V initializes the unit.

V

OS

Offset referred to V

SR

-

±50 ±150 µV

DISP

= V

CC

V

REF

Reference at 25°C 5.7 6.0 6.3 V I

REF

= 5µA

Reference at -40°C to +85°C 4.5 - 7.5 V I

REF

= 5µA

R

REF

Reference input impedance 2.0 5.0 - MΩV

REF

= 3V

I

CC

Normal operation

- 90 135

µ

AV

CC

= 3.0V, DQ = 0

- 120 180

µ

AV

CC

= 4.25V, DQ = 0

- 170 250

µ

AV

CC

= 6.5V, DQ = 0

V

SB

Battery input 0 - V

CC

V

R

SBmax

SB input impedance 10 - - MΩ0 < VSB< V

CC

I

DISP

DISP input leakage - - 5

µ

AV

DISP

= V

SS

I

MODE

MODE input leakage -0.2 - 0.2

µ

A DISP = V

CC

I

RBI

RBI data-retention current - - 100 nA V

RBI

> VCC< 3V

R

DQ

Internal pulldown 500 - - K

Ω

V

SR

Sense resistor input -0.3 - 2.0 V

V

SR>VSS

= discharge;

V

SR

< VSS= charge

R

SR

SR input impedance 10 - - MΩ-200mV < VSR< V

CC

V

IHPFC

PFC logic input high VCC- 0.2 - - V PFC

V

ILPFC

PFC logic input low - - VSS+ 0.2 V PFC

V

IZPFC

PFC logic input Z float - float V PFC

I

IHPFC

PFC input high current - 1.2 -

µ

AV

PFC

= VCC/2

I

ILPFC

PFC input low current - 1.2 -

µ

AV

PFC

= VCC/2

V

OLSL

SEGXoutput low, low V

CC

- 0.1 - V

V

CC

= 3V, I

OLS

≤

1.75mA

SEG

1

–SEG

5

V

OLSH

SEGXoutput low, high V

CC

- 0.4 - V

V

CC

= 6.5V, I

OLS

≤

11.0mA

SEG

1

–SEG

5

V

OHML

MODE output high, low V

CC

VCC- 0.3 - - V VCC= 3V, I

OHMODE

= -5.25mA

V

OHMH

MODE output high, high V

CC

VCC- 0.6 - - V VCC= 6.5V, I

OHMODE

= -33.0mA

I

OHMODE

MODE source current -33 - - mA At V

OHMODE

= VCC- 0.6V

I

OLS

SEGXsink current 11.0 - - mA At V

OLSH

= 0.4V, VCC= 6.5V

I

OL

Open-drain sink current 5.0 - - mA At VOL= VSS+ 0.3V, DQ

V

OL

Open-drain output low - - 0.5 V I

OL

≤

5mA, DQ

V

IHDQ

DQ input high 2.5 - - V DQ

V

ILDQ

DQ input low - - 0.8 V DQ

R

FLOAT

Float state external impedance - 5 - MΩPFC

Note: All voltages relative to VSS.

17

bq2011

Serial Communication Timing Specification (T

A

=T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

t

CYCH

Cycle time, host to bq2011 3 - - ms See note

t

CYCB

Cycle time, bq2011 to host 3 - 6 ms

t

STRH

Start hold, host to bq2011 5 - - ns

t

STRB

Start hold, bq2011 to host 500 - -

µ

s

t

DSU

Data setup - - 750

µ

s

t

DH

Data hold 750 - -

µ

s

t

DV

Data valid 1.50 - - ms

t

SSU

Stop setup - - 2.25 ms

t

SH

Stop hold 700 - -

µ

s

t

SV

Stop valid 2.95 - - ms

t

B

Break 3 - - ms

t

BR

Break recovery 1 - - ms

Note: The open-drain DQ pin should be pulled to at least VCCby the host system for proper DQ operation.

DQ may be left floating if the serial interface is not used.

DQ

(R/W "1")

t

STRH

t

STRB

t

DSU

t

DH

t

DV

t

SV

t

SSU

t

SH

t

CYCH, tCYCB, tB

t

BR

DQ

(R/W "0")

DQ

(BREAK)

Serial Communication Timing Illustration

18

bq2011

16-Pin SOIC Narrow (SN)

16-Pin SN(SOIC Narrow

)

Dimension Minimum Maximum

A 0.060 0.070

A1 0.004 0.010

B 0.013 0.020
C 0.007 0.010
D 0.385 0.400
E 0.150 0.160

e 0.045 0.055
H 0.225 0.245
L 0.015 0.035

All dimensions are in inches.

A

A1

.004

C

B

e

D

E

H

L

19

bq2011

* Contact factory for availability.

Ordering Information

bq2011

Package Option:

SN = 16-pin narrow SOIC

Device:

bq2011 Gas Gauge IC

Temperature Range:

blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)*

Data Sheet Revision History

Change No. Page No. Description Nature of Change

3 7 Self-discharge count rate Was:

1

64

*

NAC rate per day

Is:

1

80

*

NAC rate per day

3 7 Compensation factor 30–40°C Was: 0.90

Is: 0.95

3 7 Compensation factor >40°C Was: 0.80

Is: 0.90

4 7 Charge compensation Changed compensation factor variation with temperature

4 8 Self-discharge compensation Changed self-discharge compensation rate variation with

temperature

Notes: Changes 1 and 2 = See the 1995 Data Book.

Change 3 = Jan. 1996 D changes from July 1994 C.
Change 4 = Feb. 1996 E changes from Jan. 1996 D.

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Copyright  1999, Texas Instruments Incorporated