TEXAS INSTRUMENTS DRV601 Technical data

DRV601

www.ti.com

........................................................................................................................................... SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008

DIRECTPATH™ STEREO LINE DRIVER, ADJUSTABLE GAIN

1

FEATURES

2

• External Gain Setting Resistors

• Space Saving Package

– 20-Pin, 4 mm × 4 mm Thin QFN, Thermally

Optimized PowerPAD™ Package

• Ground-Referenced Outputs Eliminate

DC-Blocking Capacitor
– Reduce Board Area
– Reduce Component Cost
– Improve THD+N Performance
– No Degradation of Low-Frequency

Response Due to Output Capacitors

• Wide Power Supply Range: 1.8 V to 4.5 V

• 2 Vrms/Ch Output Voltage into 600 Ω at 3.3 V

supply

DESCRIPTION

The DRV601 is a stereo line driver designed to allow the removal of the output dc-blocking capacitors for
reduced component count and cost. The device is ideal for single supply electronics where size and cost are
critical design parameters.

The DRV601 is capable of driving 2 Vrms into a 600- Ω load at 3.3 V. The device has external gain setting
resistors, that support a gain range of -1V/V to -10V/V, and line outputs that has ± 8-kV IEC ESD protection. The
device has independent shutdown control for the right and left audio channels.

The DRV601 is available in a 4 mm × 4 mm Thin QFN package.

• Independent Right and Left Channel

Shutdown Control

• Short-Circuit and Thermal Protection

• Pop Reduction Circuitry

APPLICATIONS

• Set-Top Boxes

• CD / DVD Players

• DVD-Receivers

• HTIB

• PDP / LCD TV's

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 DIRECTPATH, PowerPAD, DirectPath are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2008, Texas Instruments Incorporated

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

NC

PVDD

SDL

SGND

NC

C1P

PGND

C1N

NC

PVSS

INR

SDR

INL

NC

OUTR

NC

SVSS

NC

OUTL

SVDD

NC − Nointernalconnection

DRV601

SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

RTJ (QFN) PACKAGE

(TOP VIEW)

www.ti.com

TERMINAL FUNCTIONS

TERMINAL

NAME QFN

C1P 1 I/O Charge pump flying capacitor positive terminal
PGND 2 I Power ground, connect to ground.
C1N 3 I/O Charge pump flying capacitor negative terminal
NC 4, 6, 8, 12, 16, 20 No connection
PVSS 5 O Output from charge pump.
SVSS 7 I Amplifier negative supply, connect to PVSS via star connection.
OUTL 9 O Left audio channel output signal
SVDD 10 I Amplifier positive supply, connect to PVDD via star connection.
OUTR 11 O Right audio channel output signal
INL 13 I Left audio channel input signal
SDR 14 I Right channel shutdown, active low logic.
INR 15 I Right audio channel input signal
SGND 17 I Signal ground, connect to ground.
SDL 18 I Left channel shutdown, active low logic.
PVDD 19 I Supply voltage, connect to positive supply.

Exposed Pad

I/O DESCRIPTION

Exposed pad must be soldered to a floating plane. Do NOT connect to power or ground.

2 Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): DRV601

DRV601

www.ti.com

ABSOLUTE MAXIMUM RATINGS

........................................................................................................................................... SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008

(1)

over operating free-air temperature range, TA= 25 ° C (unless otherwise noted)

VALUE / UNIT

Supply voltage, AVDD, PVDD – 0.3 V to 5.5 V
V
R
T
T
T

Input voltage V

I

Minimum load impedance ≥ 100 Ω

(Load)

Operating free-air temperature range – 40 ° C to 85 ° C

A

Operating junction temperature range 0 ° C to 150 ° C

J

Storage temperature range – 65 ° C to 85 ° C

stg

– 0.3 V to V

SS

+ 0.3 V

DD

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

AVAILABLE OPTIONS

T

A

PACKAGED DEVICES

-40 ° C to 85 ° C 20-pin, 4 mm × 4 mm QFN DRV601RTJ

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

(2) The RTJ package is only available taped and reeled. To order, add the suffix “ R ” to the end of the part number for a reel of 3000, or add

the suffix “ T ” to the end of the part number for a reel of 250 (e.g., DRV601RTJR).

(1)

PART NUMBER SYMBOL

(2)

AKQ

RECOMMENDED OPERATING CONDITIONS

V

SS

V

IH

V

IL

T

A

(1) Device can shut down for V

Supply voltage, AVDD, PVDD 1.8 4.5
High-level input voltage SDL, SDR 1.5 V
Low-level input voltage SDL, SDR 0.5 V
Operating free-air temperature – 40 85 ° C

> 4.5 V to prevent damage to the device.

DD

ELECTRICAL CHARACTERISTICS

TA= 25 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

|V

| Output offset voltage V

OS

PSRR Power Supply Rejection Ratio V
V
V
|IIH| High-level input current ( SDL, SDR) V
|IIL| Low-level input current ( SDL, SDR) V

I

High-level output voltage V

OH

Low-level output voltage V

OL

Supply Current

DD

MIN MAX UNIT

= 1.8 V to 4.5 V, Inputs grounded 8 mV

DD

= 1.8 V to 4.5 V 88 dB

DD

= 3.3 V, RL= 600 Ω 3.10 V

DD

= 3.3 V, RL= 600 Ω – 3.05 V

DD

= 4.5 V, VI= V

DD

= 4.5 V, VI= 0 V 1 µ A

DD

V

= 1.8 V, No load, SDL= SDR = V

DD

V

= 3.3 V, No load, SDL = SDR = V

DD

V

= 4.5 V, No load, SDL = SDR = V

DD

Shutdown mode, V

DD

DD

DD
DD

= 1.8 V to 4.5 V 1 µ A

DD

5.3

7.1 mA

8.7

(1)

V

1 µ A

Copyright © 2008, Texas Instruments Incorporated 3

Product Folder Link(s): DRV601

DRV601

SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................

OPERATING CHARACTERISTICS

V

= 3.3 V , TA= 25 ° C, RL= 600 Ω , C

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Output Voltage(Outputs In Phase) V

THD+N Total harmonic distortion plus noise

Crosstalk VO= 2 Vrms, f = 1 kHz -80 dB

A

vo

R

in

R

fb

Open-loop voltage gain 155 dB
Input resistor range 1 10 47 k Ω
Feedback resistor range 4.7 20 100 k Ω
Slew rate 2.2 V/ µ s
Maximum capacitive load 300 pF

V

n

Noise output voltage 22-kHz filter, A-weighted 10 µ Vrms
ESD Electrostatic discharge OUTR, OUTL ± 8 kV
f

osc

Charge pump switching frequency 280 320 420 kHz

Start-up time from shutdown 450 µ s

Input impedance 1 M Ω
SNR Signal-to-noise ratio 105 dB
G

(bw)

Unity Gain Bandwidth 3.5 MHz

Thermal shutdown

= C

(PUMP)

(PVSS)

= 1 µ F , C

THD = 1%, V
THD = 1%, V
THD = 1%, V

100 k Ω

= 1 µ F, R

IN

= 3.3 V, f = 1 kHz 2.1

DD

= 4.5 V, f = 1 kHz 2.7

DD

= 4.5 V, f = 1 kHz, RL=

DD

= 10 k Ω , R

in

= 20 k Ω (unless otherwise noted)

fb

2.8

VO= 2 Vrms, f = 1 kHz 0.008%
VO= 2 Vrms, f = 6.67 kHz 0.030%

Vo= 2 Vrms (THD+N = 0.1%), 22-kHz BW,
A-weighted

Threshold 150 170 ° C
Hysteresis 15 ° C

www.ti.com

RMS

4 Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): DRV601

FunctionalBlockDiagram

Rin

SVDD

SVDD

SVSS

SVSS

SGND

AudioOut - R

AudioOut - L

Short

Circuit

Protection

Charge

Pump

Bias

Circuitry

SDx

C 1N

C 1P

PVSS

Rin

Rfb

Rfb

+

+

-

-

DRV601

www.ti.com

........................................................................................................................................... SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008

Functional Block Diagram

Copyright © 2008, Texas Instruments Incorporated 5

Product Folder Link(s): DRV601

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

O

0.001

10

0.01

0.1

1

THD+N-totalHarmonicDistortion+Noise-%

V =1.8V,

R =100k ,
f=1kHz

DD

L

W

0.001

10

0.01

0.1

1

THD+N-totalHarmonicDistortion+Noise-%

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

O

V =3.3V,

R =100k ,
f=1kHz

DD

L

W

0.001

10

0.01

0.1

1

THD+N-totalHarmonicDistortion+Noise-%

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

O

V =4.5V,

R =100k ,
f=1kHz

DD

L

W

0.001

10

0.01

0.1

1

THD+N-totalHarmonicDistortion+Noise-%

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

O

V =3.3V,

R =600 ,
f=1kHz

DD

L

W

0.001

10

0.01

0.1

1

THD+N-totalHarmonicDistortion+Noise-%

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

O

V =1.8V,

R =600 ,
f=1kHz

DD

L

W

0.001

10

0.01

0.1

1

THD+N-totalHarmonicDistortion+Noise-%

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

O

V =4.5V,

R =600 ,
f=1kHz

DD

L

W

DRV601

SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................

TYPICAL CHARACTERISTICS

C

= C

(PUMP)

= 1 µ F , C

(PVSS)

= 1 µ F, R

IN

= 10 k Ω , R

in

= 20 k Ω (unless otherwise noted)

fb

Table of Graphs

Total harmonic distortion + noise vs Output Voltage 1-6
Total harmonic distortion + noise vs Frequency 7-8
Quiescent supply current vs Supply voltage 9
Output spectrum 10
Gain and phase vs Frequency 11-12

TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +

NOISE NOISE NOISE

vs vs vs

OUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE

www.ti.com

FIGURE

Figure 1. Figure 2. Figure 3.

TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +

NOISE NOISE NOISE

OUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE

vs vs vs

Figure 4. Figure 5. Figure 6.

6 Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): DRV601