TEXAS INSTRUMENTS DRV601 Technical data

DRV601

www.ti.com

........................................................................................................................................... SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008

DIRECTPATH™ STEREO LINE DRIVER, ADJUSTABLE GAIN

FEATURES

• External Gain Setting Resistors

• Space Saving Package

– 20-Pin, 4 mm × 4 mm Thin QFN, Thermally

Optimized PowerPAD™ Package

• Ground-Referenced Outputs Eliminate

DC-Blocking Capacitor – Reduce Board Area – Reduce Component Cost – Improve THD+N Performance – No Degradation of Low-Frequency

Response Due to Output Capacitors

• Wide Power Supply Range: 1.8 V to 4.5 V

• 2 Vrms/Ch Output Voltage into 600 Ω at 3.3 V

supply

DESCRIPTION

The DRV601 is a stereo line driver designed to allow the removal of the output dc-blocking capacitors for reduced component count and cost. The device is ideal for single supply electronics where size and cost are critical design parameters.

The DRV601 is capable of driving 2 Vrms into a 600- Ω load at 3.3 V. The device has external gain setting resistors, that support a gain range of -1V/V to -10V/V, and line outputs that has ± 8-kV IEC ESD protection. The device has independent shutdown control for the right and left audio channels.

The DRV601 is available in a 4 mm × 4 mm Thin QFN package.

• Independent Right and Left Channel

Shutdown Control

• Short-Circuit and Thermal Protection

• Pop Reduction Circuitry

APPLICATIONS

• Set-Top Boxes

• CD / DVD Players

• DVD-Receivers

• HTIB

• PDP / LCD TV's

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 DIRECTPATH, PowerPAD, DirectPath are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

PVDD

SDL

SGND

C1P

PGND

C1N

PVSS

INR

SDR

INL

OUTR

SVSS

OUTL

SVDD

NC − Nointernalconnection

DRV601

SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

RTJ (QFN) PACKAGE

(TOP VIEW)

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TERMINAL FUNCTIONS

TERMINAL

NAME QFN

C1P 1 I/O Charge pump flying capacitor positive terminal PGND 2 I Power ground, connect to ground. C1N 3 I/O Charge pump flying capacitor negative terminal NC 4, 6, 8, 12, 16, 20 No connection PVSS 5 O Output from charge pump. SVSS 7 I Amplifier negative supply, connect to PVSS via star connection. OUTL 9 O Left audio channel output signal SVDD 10 I Amplifier positive supply, connect to PVDD via star connection. OUTR 11 O Right audio channel output signal INL 13 I Left audio channel input signal SDR 14 I Right channel shutdown, active low logic. INR 15 I Right audio channel input signal SGND 17 I Signal ground, connect to ground. SDL 18 I Left channel shutdown, active low logic. PVDD 19 I Supply voltage, connect to positive supply.

Exposed Pad

I/O DESCRIPTION

Exposed pad must be soldered to a floating plane. Do NOT connect to power or ground.

Product Folder Link(s): DRV601

DRV601

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ABSOLUTE MAXIMUM RATINGS

........................................................................................................................................... SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008

(1)

over operating free-air temperature range, TA= 25 ° C (unless otherwise noted)

VALUE / UNIT

Supply voltage, AVDD, PVDD – 0.3 V to 5.5 V V R T T T

Input voltage V

Minimum load impedance ≥ 100 Ω

(Load)

Operating free-air temperature range – 40 ° C to 85 ° C

Operating junction temperature range 0 ° C to 150 ° C

Storage temperature range – 65 ° C to 85 ° C

stg

– 0.3 V to V

+ 0.3 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

AVAILABLE OPTIONS

PACKAGED DEVICES

-40 ° C to 85 ° C 20-pin, 4 mm × 4 mm QFN DRV601RTJ

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

(2) The RTJ package is only available taped and reeled. To order, add the suffix “ R ” to the end of the part number for a reel of 3000, or add

the suffix “ T ” to the end of the part number for a reel of 250 (e.g., DRV601RTJR).

(1)

PART NUMBER SYMBOL

(2)

AKQ

RECOMMENDED OPERATING CONDITIONS

(1) Device can shut down for V

Supply voltage, AVDD, PVDD 1.8 4.5 High-level input voltage SDL, SDR 1.5 V Low-level input voltage SDL, SDR 0.5 V Operating free-air temperature – 40 85 ° C

> 4.5 V to prevent damage to the device.

ELECTRICAL CHARACTERISTICS

TA= 25 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

| Output offset voltage V

PSRR Power Supply Rejection Ratio V V V |IIH| High-level input current ( SDL, SDR) V |IIL| Low-level input current ( SDL, SDR) V

High-level output voltage V

Low-level output voltage V

Supply Current

MIN MAX UNIT

= 1.8 V to 4.5 V, Inputs grounded 8 mV

= 1.8 V to 4.5 V 88 dB

= 3.3 V, RL= 600 Ω 3.10 V

= 3.3 V, RL= 600 Ω – 3.05 V

= 4.5 V, VI= V

= 4.5 V, VI= 0 V 1 µ A

= 1.8 V, No load, SDL= SDR = V

= 3.3 V, No load, SDL = SDR = V

= 4.5 V, No load, SDL = SDR = V

Shutdown mode, V

DD DD

= 1.8 V to 4.5 V 1 µ A

5.3

7.1 mA

8.7

(1)

1 µ A

Product Folder Link(s): DRV601

DRV601

SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................

OPERATING CHARACTERISTICS

= 3.3 V , TA= 25 ° C, RL= 600 Ω , C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output Voltage(Outputs In Phase) V

THD+N Total harmonic distortion plus noise

Crosstalk VO= 2 Vrms, f = 1 kHz -80 dB

Open-loop voltage gain 155 dB Input resistor range 1 10 47 k Ω Feedback resistor range 4.7 20 100 k Ω Slew rate 2.2 V/ µ s Maximum capacitive load 300 pF

Noise output voltage 22-kHz filter, A-weighted 10 µ Vrms ESD Electrostatic discharge OUTR, OUTL ± 8 kV f

osc

Charge pump switching frequency 280 320 420 kHz

Start-up time from shutdown 450 µ s

Input impedance 1 M Ω SNR Signal-to-noise ratio 105 dB G

(bw)

Unity Gain Bandwidth 3.5 MHz

Thermal shutdown

= C

(PUMP)

(PVSS)

= 1 µ F , C

THD = 1%, V THD = 1%, V THD = 1%, V

100 k Ω

= 1 µ F, R

= 3.3 V, f = 1 kHz 2.1

= 4.5 V, f = 1 kHz 2.7

= 4.5 V, f = 1 kHz, RL=

= 10 k Ω , R

= 20 k Ω (unless otherwise noted)

2.8

VO= 2 Vrms, f = 1 kHz 0.008% VO= 2 Vrms, f = 6.67 kHz 0.030%

Vo= 2 Vrms (THD+N = 0.1%), 22-kHz BW, A-weighted

Threshold 150 170 ° C Hysteresis 15 ° C

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RMS

Product Folder Link(s): DRV601

FunctionalBlockDiagram

Rin

SVDD

SVSS

SGND

AudioOut - R

AudioOut - L

Short

Circuit

Protection

Charge

Pump

Bias

Circuitry

SDx

C 1N

C 1P

PVSS

Rin

Rfb

DRV601

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........................................................................................................................................... SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008

Functional Block Diagram

Product Folder Link(s): DRV601

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

0.001

0.01

0.1

THD+N-totalHarmonicDistortion+Noise-%

V =1.8V,

R =100k , f=1kHz

0.001

0.01

0.1

THD+N-totalHarmonicDistortion+Noise-%

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

V =3.3V,

R =100k , f=1kHz

0.001

0.01

0.1

THD+N-totalHarmonicDistortion+Noise-%

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

V =4.5V,

R =100k , f=1kHz

0.001

0.01

0.1

THD+N-totalHarmonicDistortion+Noise-%

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

V =3.3V,

R =600 , f=1kHz

0.001

0.01

0.1

THD+N-totalHarmonicDistortion+Noise-%

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

V =1.8V,

R =600 , f=1kHz

0.001

0.01

0.1

THD+N-totalHarmonicDistortion+Noise-%

3m 310m 100m 500m 2

V -OutputVoltage-Vrms

V =4.5V,

R =600 , f=1kHz

DRV601

SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................

TYPICAL CHARACTERISTICS

= C

(PUMP)

= 1 µ F , C

(PVSS)

= 1 µ F, R

= 10 k Ω , R

= 20 k Ω (unless otherwise noted)

Table of Graphs

Total harmonic distortion + noise vs Output Voltage 1-6 Total harmonic distortion + noise vs Frequency 7-8 Quiescent supply current vs Supply voltage 9 Output spectrum 10 Gain and phase vs Frequency 11-12

TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +

NOISE NOISE NOISE

vs vs vs

OUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE

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FIGURE

Figure 1. Figure 2. Figure 3.

TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +

NOISE NOISE NOISE

OUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE

vs vs vs

Figure 4. Figure 5. Figure 6.

Product Folder Link(s): DRV601

20 20k50 100 500 1k 2k 5k

f-frequency-Hz

0.001

0.01

0.1

THD+N-totalHarmonicDistortion+Noise-%

V =3.3V,

R =600 , 2Vrms

20 20k50 100 500 1k 2k 5k

f-frequency-Hz

0.001

0.01

0.1

THD+N-totalHarmonicDistortion+Noise-%

V =3.3V,

R =600 , 200mVrms

0 4.50.5 1 1.5 2 2.5 3 3.5

V -SupplyVoltage-V

I -SupplyCurrent-mA

R =600 , NoLoad

-140

-120

-100

-80

-60

-40

-20

0 20k10k

f-frequency-Hz

FFT-dBr

V =3.3V,

R =600 , G=-60dB

3.5

4.5

5.5

6.5

20 100k100 1k 2k 10k

f-frequency-Hz

Gain-dB

V =3.3V,

R =600 , 2Vrms

-200

-175

-150

-125

-100

-75

-50

-25

20 100k100 1k 2k 10k

f-frequency-Hz

Phase-deg

V =3.3V,

R =600 , 2Vrms

DRV601

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........................................................................................................................................... SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008

TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +

NOISE NOISE QUIESCENT SUPPLY CURRENT

vs vs vs

FREQUENCY FREQUENCY SUPPLY VOLTAGE

Figure 7. Figure 8. Figure 9.

FFT GAIN PHASE

vs vs vs

FREQUENCY FREQUENCY FREQUENCY

Figure 10. Figure 11. Figure 12.

Product Folder Link(s): DRV601

f =

2 R Cp

L O

C =

2 R fp

OUT

GND

V /2

Conventional

GND

DirectPath

DRV601

SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................

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APPLICATION INFORMATION

Line Driver Amplifiers

Single-supply Line Driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 13 illustrates the conventional Line Driver amplifier connection to the load and output signal.

DC blocking capacitors are often large in value. The line load (typical resistive values of 600 Ω to 10 k Ω ) combine with the dc blocking capacitors to form a high-pass filter. Equation 1 shows the relationship between the load impedance (R

can be determined using Equation 2 , where the load impedance and the cutoff frequency are known.

If fCis low, the capacitor must then have a large value because the load resistance is small. Large capacitance values require large package sizes. Large package sizes consume PCB area, stand high above the PCB, increase cost of assembly, and can reduce the fidelity of the audio output signal.

), the capacitor (C

), and the cutoff frequency (fC).

(1)

(2)

Figure 13. Amplifier Applications

The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. The DirectPath™ amplifier requires no output dc blocking capacitors. The bottom block diagram and waveform of Figure 13 illustrate the ground-referenced Line Driver architecture. This is the architecture of the DRV601.

Product Folder Link(s): DRV601

2p RINC

2p fcINR

DRV601

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........................................................................................................................................... SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008

Charge Pump Flying Capacitor and PVSS Capacitor

The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 1 µ F is typical. Capacitor values that are smaller than 1 µ F can be used, but the maximum output voltage may be reduced and the device may not operate to specifications.

Decoupling Capacitors

The DRV601 is a DirectPath™ Line Driver amplifier that require adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic capacitor, typically 2.2 µ F, placed as close as possible to the device V

lead works best. Placing this

decoupling capacitor close to the DRV601 is important for the performance of the amplifier. For filtering lower frequency noise signals, a 10- µ F or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device.

Gain setting resistors ranges

The gain setting resistors, R DRV601 is kept within acceptable limits. Voltage gain is defined as R

Selecting values that are too low demands a large input ac-coupling capacitor, C high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different gain settings.

Gain Input Resistor Value, R

-1 V/V 10 k Ω 10 k Ω

-1.5 V/V 10 k Ω 15 k Ω

-2 V/V 10 k Ω 20 k Ω

-10 V/V 4,7 k Ω 47 k Ω

and Rfb, must be chosen so that noise, stability and input capacitor size of the

divided by Rin.

. Selecting values that are too

Table 1. Recommended Resistor Values

Feedback Resistor Value, R

Input-Blocking Capacitors

DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the DRV601. These capacitors block the DC portion of the audio source and allow the DRV601 inputs to be properly biased to provide maximum performance.

These capacitors form a high-pass filter with the input resistor, Rin. The cutoff frequency is calculated using

Equation 3 . For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the

input resistor chosen from the gain table above, then the frequency and/or capacitance can be determined when one of the two values are given.

Supply Voltage Limiting At 4.5 V

The DRV601 have a built-in charge pump which serves to generate a negative rail for the line driver. Because the line driver operates from a positive voltage and negative voltage supply, circuitry has been implemented to protect the devices in the amplifier from an overvoltage condition. Once the supply is above 4.5 V, the DRV601 can shut down in an overvoltage protection mode to prevent damage to the device. The DRV601 resume normal operation once the supply is reduced to 4.5 V or lower.

Capacitive load

The DRV601 has the ability to drive a high capacitive load up to 330pF directly, higher capacitive loads can be accepted by adding a series resistor of 10 Ω or larger. The figure below shows a 10kHz signal into a 470pF capacitor using the 10R series resistor.

(3)

Product Folder Link(s): DRV601

t − Time=20ms/div

Ch2

1 V/div

DRV601

SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................

SQUARE WAVE OUTPUT VOLTAGE

with

CAPACITIVE LOAD

Figure 14.

Layout Recommendations

A proposed layout for the DRV601 can be seen in the DRV601EVM user's guide, SLOU215 , and the Gerber files can be downloaded on www.ti.com , open the DRV601 product folder and look in the Tools & Software folder.

www.ti.com

Exposed Pad On DRV601RTJ Package

The exposed metal pad on the DRV601RTJ package must be soldered down to a pad on the PCB in order to maintain reliability. The pad on the PCB should be allowed to float and not be connected to ground or power. Connecting this pad to power or ground prevents the device from working properly because it is connected internally to PVSS.

SGND and PGND Connections

The SGND and PGND pins of the DRV601 must be routed back to the decoupling capacitor separately in order to provide proper device operation. If the SGND and PGND pins are connected directly to each other, the part functions without risk of failure, but the noise and THD performance do not meet the specifications.

Gain setting resistors

The gain setting resistors, R

and R

, must be placed close to pin 13 respectively pin 17 to minimize the

capacitive loading on these input pins and to ensure maximum stability of the DRV601. For the recommenced PCB layout, see the DRV601EVM user guide.

Product Folder Link(s): DRV601

DRV601

AudioIn-R

AudioIn-L

SGND

AudioOut-R

AudioOut-L

SDL

C1N

Right

Output

PVSS

SDR

PGND

PVDD SVDD

Shuntdown

Control

PCM1773

VOUT_R

VOUT_L

330pF

LeftOutput

VCC

47kW

33pF

3.3V

1 Fm

15kW

1 Fm

33kW

33pF

330pF

47kW

1 Fm

C1P

1 Fm

DRV601

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........................................................................................................................................... SLOS553B – JANUARY 2008 – REVISED NOVEMBER 2008

Figure 15. Application Circuit

Product Folder Link(s): DRV601

PACKAGE OPTION ADDENDUM

www.ti.com 16-Apr-2009

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

DRV601RTJR ACTIVE QFN RTJ 20 3000 Green (RoHS &

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

(3)

no Sb/Br)

DRV601RTJRG4 ACTIVE QFN RTJ 20 3000 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DRV601RTJT ACTIVE QFN RTJ 20 250 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DRV601RTJTG4 ACTIVE QFN RTJ 20 250 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 1-May-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

DRV601RTJR QFN RTJ 20 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 DRV601RTJT QFN RTJ 20 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 1-May-2009

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DRV601RTJR QFN RTJ 20 3000 346.0 346.0 29.0 DRV601RTJT QFN RTJ 20 250 190.5 212.7 31.8

Pack Materials-Page 2

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TEXAS INSTRUMENTS DRV601 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

APPLICATIONS

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

OPERATING CHARACTERISTICS

TYPICAL CHARACTERISTICS

Table of Graphs

APPLICATION INFORMATION

Line Driver Amplifiers

Charge Pump Flying Capacitor and PVSS Capacitor

Decoupling Capacitors

Gain setting resistors ranges

Input-Blocking Capacitors

Supply Voltage Limiting At 4.5 V

Capacitive load

Layout Recommendations

Exposed Pad On DRV601RTJ Package

SGND and PGND Connections

Gain setting resistors