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DRA77xP, DRA76xP Infotainment Applications Processor

Silicon Revision 1.0

1 Device Overview

1.1 Features

1

• Architecture Designed for Infotainment Applications

• Video, Image, and Graphics Processing Support – Full-HD Video (1920 × 1080p, 60 fps) – Multiple Video Input and Video Output – 2D and 3D Graphics

• Dual Arm®Cortex®-A15 Microprocessor Subsystem

• Up to Two C66x Floating-Point VLIW DSP – Fully Object-Code Compatible with C67x and

C64x+

– Up to Thirty-Two 16 x 16-Bit Fixed-Point

Multiplies per Cycle

• Up to 2.5MB of On-Chip L3 RAM

• Level 3 (L3) and Level 4 (L4) Interconnects

• Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules

– Supports up to DDR2-800 and DDR3-1333 – Up to 2GB Supported per EMIF

• Dual ARM® Cortex®-M4 Image Processing Units (IPU)

• Up to Two Embedded Vision Engines (EVEs)

• Imaging Subsystem (ISS) – Image Signal Processor (ISP) – Wide Dynamic Range and Lens Distortion

Correction (WDR and Mesh LDC)

– One Camera Adaptation Layer (CAL_B)

• IVA Subsystem

• Display Subsystem – Display Controller with DMA Engine and up to

Three Pipelines

– HDMI™ Encoder: HDMI 1.4a and DVI 1.0

Compliant

• Video Processing Engine (VPE)

• 2D-Graphics Accelerator (BB2D) Subsystem – Vivante®GC320 Core

• Dual-Core PowerVR®SGX544 3D GPU

• Two Video Input Port (VIP) Modules – Support for up to Eight Multiplexed Input Ports

• General-Purpose Memory Controller (GPMC)

• Enhanced Direct Memory Access (EDMA) Controller

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SPRS993E –MARCH 2017–REVISED DECEMBER 2018

• 2-Port Gigabit Ethernet (GMAC)

• Sixteen 32-Bit General-Purpose Timers

• 32-Bit MPU Watchdog Timer

• Five Inter-Integrated Circuit (I2C) Ports

• HDQ™/ 1-Wire®Interface

• SATA Interface

• Media Local Bus (MLB) Subsystem

• Ten Configurable UART/IrDA/CIR Modules

• Four Multichannel Serial Peripheral Interfaces (McSPI)

• Quad SPI (QSPI)

• Eight Multichannel Audio Serial Port (McASP) Modules

• SuperSpeed USB 3.0 Dual-Role Device

• Three High-Speed USB 2.0 Dual-Role Devices

• Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces ( MMC™/ SD®/SDIO)

• PCI Express®3.0 Subsystems with Two 5-Gbps Lanes

– One 2-Lane Gen2-Compliant Port – or Two 1-Lane Gen2-Compliant Ports

• Up to Two Controller Area Network (DCAN) Modules

– CAN 2.0B Protocol

• Modular Controller Area Network (MCAN) Module – CAN 2.0B Protocol with Available FD (Flexible

Data Rate) Functionality

• MIPI CSI-2 Camera Serial Interface

• Up to 247 General-Purpose I/O (GPIO) Pins

• Device Security Features – Hardware Crypto Accelerators and DMA – Firewalls – JTAG®Lock – Secure Keys – Secure ROM and Boot – Customer Programmable Keys and OTP Data

• Power, Reset, and Clock Management

• On-Chip Debug with CTools Technology

• 28-nm CMOS Technology

• 23 mm × 23 mm, 0.8-mm Pitch, 784-Pin BGA (ACD)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

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1.2 Applications

• Human-Machine Interface (HMI)

• Navigation

• Digital and Analog Radio

• Rear Seat Entertainment

• Multimedia Playback

1.3 Description

DRA77xP and DRA76xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

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• Web Browsing

• ADAS Integration

• Integrated Automotive Digital Cockpit

• Infotainment / Center Stack

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA77xP and DRA76xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

Device Information

PART NUMBER PACKAGE BODY SIZE

DRA77xP FCBGA (784) 23.0 mm × 23.0 mm DRA76xP FCBGA (784) 23.0 mm × 23.0 mm

2

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Program/Data Storage

Serial Interfaces

Connectivity

I2C x5

UART x10

McSPI x4

DCAN x2

McASP x8

System

Spinlock

(2x Arm

Cortex–A15)

DSP1 C66x

Co-Processors

PCIe SS x2

Mailbox x13

GPIO x8

Timers x16

WDT

MediaLB /

MOST150

GMAC AVB

up to 2.5MiB RAM w/ ECC

SATA

(NAND/NOR/

Async)

MMC / SD x4

2x 32b

DMM

2x VCP

HD ATL

(Dual-Core SGX544 3D)

BB2D

320 2D)

VIP1

QSPI

3x USB 2.0

Dual Mode FS/HS

1x w/ PHY

2x w/ ULPI

EDMA

SDMA

2x EVE

Analytic

Processors

2x MMU

VPE

PWM SS x3

intro_001

KBDHDQ

1x USB 3.0

FS/HS/SS

Dual Mode w/PHY

GPMC / ELM

DDR2/3(L) w/ ECC

(1)

EMIF x2

256KiB

ROM

OCMC

DRA77x / DRA76x

(GC

GPU

MPU

DSP2 C66x

Co-Processors

(Dual Cortex–M4)

IPU1

(Dual Cortex–M4)

IPU2

IVA HD

1080p Video

Co-Processor

Radio Accelerators

High-Speed Interconnect

MCAN-FD x1

ISS

ISP CAL_B

WDR & Mesh LDC

VIP2

CAL CSI2 x2

Display Subsystem

LCD2

LCD1

1xGFX / 3xVID

Blend / Scale

HDMI 1.4a

LCD3

Secure Boot

Debug

Security

TEE

(HS devices)

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1.4 Functional Block Diagram

Figure 1-1 is functional block diagram for the device.

DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

(1) ECC is only available on EMIF1.

Figure 1-1. DRA77xP, DRA76xP Block Diagram

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2 Revision History

Changes from March 17, 2018 to December 15, 2018 (from D Revision (March 2018) to E Revision) Page

• Added clarification notes regarding X5777x part number to Table 3-1, Device Comparison............................... 6

• Updated porz, resetn and rstoutn signal descriptions in Table 4-28 PRCM Signal Descriptions. ...................... 117

• Added table note for maximum valid input voltage on an IO pin to Section 5.1, Absolute Maximum Rating Over

Junction Temperature Range .................................................................................................... 145

• Updated Section 5.3, Power-On Hours (POH)................................................................................. 146

• Added clarification note regarding TSHUT feature. .......................................................................... 150

• Added definition for MPU OPP_LOW in Voltage Domains Operating Performance Points and Supported OPP vs

Max Frequency tables............................................................................................................. 152

• Added Ivpp specification in Table 5-14, Recommended Operating Conditions for OTP eFuse Programming ....... 182

• Updated Section 5.8.3, Impact to Your Hardware Warranty................................................................. 183

• Updated Section 5.10.3, Power Supply Sequences .......................................................................... 187

• Updated system clock names in Section 5.10.4, Clock Specifications ..................................................... 195

• Updated manual mode and timing tables for DSS, GMAC-RGMII, and MMC2 ........................................... 231

• Added missing balls in Table 5-71, McSPI3/4 IOSETs ...................................................................... 274

• Updated phase polarity in all QSPI timing figures............................................................................. 277

• Removed references to OpenGL in Section 6.10, GPU...................................................................... 362

• Updated Section 7.3.5, Power Supply Mapping ............................................................................... 410

• Added new Section 7.3.7, Loss of Input Power Event........................................................................ 411

• Added clarification notes regarding X5777x part number in Table 8-1, Nomenclature Description .................... 478

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3 Device Comparison

3.1 Device Comparison Table

Table 3-1 shows a comparison between devices, highlighting the differences.

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Table 3-1. Device Comparison

(8)

Features Device

Jacinto 6 Plus EX Jacinto 6 Plus EP Jacinto 6 Plus

DRA777P DRA776P DRA775P DRA774P DRA773P DRA772P DRA771P DRA770P DRA767P DRA766P DRA765P DRA764P

CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24] Base PN register bitfield value

(7)(8)

104

(0x68)

102

(0x66)

101

(0x65)

100

(0x64)99(0x63)98(0x62)97(0x61)96(0x60)87(0x57)86(0x56)85(0x55)84(0x54)

Processors/ Accelerators

Speed Grades S P L J S P L J S P L J Dual Arm Cortex-A15

Microprocessor Subsystem C66x VLIW DSP DSP1

MPU core 0 Yes Yes Yes MPU core 1 Yes Yes Yes

Yes Yes Yes

(with L1D ECC) DSP2

Yes Yes No

(with L1D ECC)

BitBLT 2D Hardware

BB2D Yes Yes Yes

Acceleration Engine Display Subsystem VOUT1 Yes

VOUT2 Yes VOUT3 Yes

(1) (1) (1)

Yes Yes Yes

(1) (1) (1)

Yes Yes Yes

(1) (1) (1)

HDMI Yes Yes Yes

Embedded Vision Engine EVE1 Yes No No

EVE2 Yes No No

Dual Arm Cortex-M4 Image Processing Unit

IPU1 Yes Yes Yes

IPU2 Yes Yes Yes Image Video Accelarator IVA Yes Yes Yes SGX544 Dual-Core 3D

GPU Yes Yes Yes Graphics Processing Unit

Imaging Subsystem (ISS) ISP Optional

WDR & Mesh

(6)

LDC

Optional

CAL_B Optional

(2) (2)

(2)

Optional Optional

Optional

(2) (2)

(2)

Optional Optional

Optional

(2) (2)

(2)

6

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Table 3-1. Device Comparison

Features Device

Jacinto 6 Plus EX Jacinto 6 Plus EP Jacinto 6 Plus

DRA777P DRA776P DRA775P DRA774P DRA773P DRA772P DRA771P DRA770P DRA767P DRA766P DRA765P DRA764P

Video Input Port VIP1 vin1a Yes Yes No

vin1b Yes Yes No

vin2a Yes Yes Yes

vin2b Yes Yes Yes

VIP2 vin3a Yes Yes Yes

vin3b Yes Yes Yes

vin4a Yes Yes Yes

vin4b Yes Yes Yes

VIP3 vin5a No No No

vin6a No No No Video Processing Engine VPE Yes Yes Yes Camera Adaptation Layer

(CAL) Camera Serial Interface 2 (CSI2)

Program/Data Storage

On-Chip Shared Memory OCMC_RAM1 512 KB 512 KB 512 KB

General-Purpose Memory Controller

DDR2/DDR3/DDR3L Memory Controller

Dynamic Memory Manager (DMM)

Radio Support

Audio Tracking Logic (ATL) ATL Yes Yes Yes Viterbi Coprocessor (VCP) VCP1 Yes Yes Yes

Peripherals

(4)

CSI2_0

(CLK + 4 Data)

CSI2_1

(CLK + 2 Data)

OCMC_RAM2 1MB No No

OCMC_RAM3 1MB No No

GPMC Yes Yes Yes

EMIF1 up to 2GB

(with optional R-mod-W ECC) EMIF2 up to 2GB up to 2GB up to 2GB DMM Yes Yes Yes

VCP2 Yes Yes Yes

Yes Yes Yes

(8)

(continued)

(with optional R-mod-W ECC)

up to 2GB

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Table 3-1. Device Comparison

(8)

(continued)

Features Device

Jacinto 6 Plus EX Jacinto 6 Plus EP Jacinto 6 Plus

DRA777P DRA776P DRA775P DRA774P DRA773P DRA772P DRA771P DRA770P DRA767P DRA766P DRA765P DRA764P

Controller Area Network Interface (CAN)

(5)

DCAN1

(5)

DCAN2 MCAN with

(5)

FD

Yes Yes Yes Yes Yes Yes Yes Yes Yes

Enhanced DMA EDMA Yes Yes Yes System DMA DMA_SYSTEM Yes Yes Yes Ethernet Subsystem

(Ethernet SS)

GMAC_SW[0] MII, RMII, or RGMII MII, RMII, or RGMII MII, RMII, or RGMII GMAC_SW[1] MII, RMII, or RGMII MII, RMII, or RGMII MII, RMII, or RGMII

General-Purpose I/O GPIO Up to 247 Up to 247 Up to 247 Inter-Integrated Circuit

I2C 5 5 5

Interface System Mailbox Module MAILBOX 13 13 13 Media Local Bus Subsystem MLB 4096 Fs 4096 Fs 4096 Fs Multi-Channel Audio Serial

Port

McASP1 16 serializers 16 serializers 16 serializers McASP2 16 serializers 16 serializers 16 serializers McASP3 4 serializers 4 serializers 4 serializers McASP4 4 serializers 4 serializers 4 serializers McASP5 4 serializers 4 serializers 4 serializers McASP6 4 serializers 4 serializers 4 serializers McASP7 4 serializers 4 serializers 4 serializers McASP8 4 serializers 4 serializers 4 serializers

MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO)

MMC1 1x UHSI 4b 1x UHSI 4b 1x UHSI 4b MMC2 1x eMMC™ 8b 1x eMMC 8b 1x eMMC 8b MMC3 1x SDIO 8b 1x SDIO 8b 1x SDIO 8b MMC4 1x SDIO 4b 1x SDIO 4b 1x SDIO 4b

PCI Express 3.0 Port with Integrated PHY

PCIe_SS1 Yes Yes Yes (Single-lane mode) PCIe_SS2 Yes Yes No

SATA SATA Yes Yes Yes Real-Time Clock RTCSS No No No Programmable Real-Time

PRU-ICSS No No No

Unit Subsystem and Industrial Communication Subsystem

8

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Table 3-1. Device Comparison

Features Device

Jacinto 6 Plus EX Jacinto 6 Plus EP Jacinto 6 Plus

DRA777P DRA776P DRA775P DRA774P DRA773P DRA772P DRA771P DRA770P DRA767P DRA766P DRA765P DRA764P

Multichannel Serial Peripheral Interface

HDQ1W HDQ1W Yes Yes Yes Quad SPI QSPI Yes Yes Yes Spinlock Module SPINLOCK Yes Yes Yes Keyboard Controller KBD Yes Yes Yes Timers, General-Purpose TIMER 16 16 16 Timer, Watchdog WATCHDOG

Pulse-Width Modulation Subsystem

Universal Asynchronous Receiver/Transmitter

Universal Serial Bus (USB3.0)

Universal Serial Bus (USB2.0)

(1) DSS clock jitter can be improved by providing an external clock source (via inputs vin1a_clk, vin1b_clk) or from internal SATA or PCIe PLLs. (2) Device supports ISS as an optional feature if the part number is designated with the “I” option. (3) USB4 will not be supported on some pin-compatible roadmap devices. USB3 will be mapped to these balls instead. Pin compatibility can be maintained in the future by either not using

USB4, or via software change to use USB4 on this device, but USB3 on these balls in the future.

(4) In the Unified L3 memory map, there is maximum of 2GB of SDRAM space which is available to all L3 initiators including MPU (MPU, GPU, DSP, IVA, DMA, etc). Typically this space is

interleaved across both EMIFs to optimize memory performance. If a system populates > 2GB of physical memory, that additional addressable space can be accessed only by the MPU

McSPI 4 4 4

TIMER PWMSS1 Yes Yes Yes PWMSS2 Yes Yes Yes PWMSS3 Yes Yes Yes UART 10 10 10

USB1 (SuperSpeed, Dual-RoleDevice [DRD])

USB2 (HighSpeed, Dual-RoleDevice [DRD], with embedded HS PHY)

USB3 (HighSpeed, OTG2.0, with ULPI)

USB4 (HighSpeed, OTG2.0, with ULPI)

Yes Yes Yes

(8)

(continued)

(3)

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via the Arm V7 Large Physical Address Extensions (LPAE). (5) DCAN1 has one pin mux option that can optionally be used for MCAN functionality. DCAN2 has two pin mux options, one of which can be optionally used for MCAN functionality. (6) Wide Dynamic Range and Lens Distortion Correction. (7) For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bitfield, see the Jacinto 6 Plus Technical Reference Manual. (8) X577Px is the base part number for the superset device. Software should constrain the features used to match the intended production device. The Base PN register bitfield value is 0x69.

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3.2 Related Products

Automotive Processors DRAx Infotainment SoCs The "Jacinto 6" family of infotainment processors (DRA7xx), paired with robust software and ecosystem offering bring

unprecedented feature-rich, in-vehicle infotainment, instrument cluster and telematics features to the next generation automobiles.

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ACD_001

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4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the ball locations for the 784 plastic ball grid array (PBGA) package and are used in

conjunction with Table 4-1 through Table 4-32 to locate signal names and ball grid numbers.

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4.2 Pin Attributes

Table 4-1 describes the terminal characteristics and the signals multiplexed on each ball. The following list

describes the table column headers:

1. BALL NUMBER: Ball number(s) on the bottom side associated with each signal on the bottom.

2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).

3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).

Table 4-1 does not take into account the subsystem multiplexing signals. Subsystem

multiplexing signals are described in Section 4.3, Signal Descriptions.

In the Driver off mode, the buffer is configured in high-impedance.

4. 76xP: This column shows if the functionality is applicable for DRA76xP devices. Note that the Pin Attributes table presents the functionality of DRA77xP device. An empty box means "Yes".

5. MUXMODE: Multiplexing mode number:

a. MUXMODE 0 is the primary mode; this means that when MUXMODE = 0 is set, the function

mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily the default muxmode.

Figure 4-1. ACD S-PBGA-N784 Package (Bottom View)

NOTE

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The default mode is the mode at the release of the reset; also see the RESET REL. MUXMODE column.

b. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some

muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.

c. An empty box means Not Applicable.

6. TYPE: Signal type and direction: – I = Input

– O = Output – IO = Input or Output – D = Open drain – DS = Differential Signaling – A = Analog – PWR = Power – GND = Ground – CAP = LDO Capacitor

7. BALL RESET STATE: The state of the terminal at power-on reset: – drive 0 (OFF): The buffer drives VOL(pulldown or pullup resistor not activated)

– drive 1 (OFF): The buffer drives VOH(pulldown or pullup resistor not activated) – OFF: High-impedance – PD: High-impedance with an active pulldown resistor – PU: High-impedance with an active pullup resistor – An empty box means Not Applicable

8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal)

– drive 0 (OFF): The buffer drives VOL(pulldown or pullup resistor not activated) – drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated) – drive 1 (OFF): The buffer drives VOH(pulldown or pullup resistor not activated) – OFF: High-impedance – PD: High-impedance with an active pulldown resistor – PU: High-impedance with an active pullup resistor – An empty box means Not Applicable

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NOTE

12

NOTE

For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see the Power Reset and Clock Management / PRCM Reset Management Functional Description section of the Device TRM.

9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).

An empty box means Not Applicable.

10. IO VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply). An empty box means Not Applicable.

11. POWER: The voltage supply that powers the terminal IO buffers. An empty box means Not Applicable.

12. HYS: Indicates if the input buffer is with hysteresis: – Yes: With hysteresis

– No: Without hysteresis

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13. BUFFER TYPE: Drive strength of the associated output buffer.

14. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor.

15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or

DRA77P, DRA76P

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– An empty box: Not Applicable

NOTE

For more information, see the hysteresis values in Section 5.7, Electrical Characteristics.

An empty box means Not Applicable.

NOTE

For programmable buffer strength: – The default value is given in Table 4-1. – A note describes all possible values according to the selected muxmode.

Pullup and pulldown resistors can be enabled or disabled via software. – PU: Internal pullup

– PD: Internal pulldown – PU/PD: Internal pullup and pulldown – PUx/PDy: Programmable internal pullup and pulldown – PDy: Programmable internal pulldown – An empty box means No pull

logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers. – 0: Logic 0 driven on the peripheral's input signal port.

– 1: Logic 1 driven on the peripheral's input signal port. – Blank: Pin state driven on the peripheral's input signal port.

NOTE

Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (Hi-Z mode is not an input signal).

NOTE

When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

CAUTION

Peripherals exposed in Pin Attributes Table and Pin Multiplexing Table represent functionality of a DRA77xP device. Not all exposed peripherals are supported on DRA7xx devices. For peripherals supported on DRA7xx family of products please refer to Table 3-1, Device Comparison.

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Some of the DDR1 and DDR2 signals have an additional state change at the release of porz. The state that the signals change to at the release of porz is as follows:

drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_nck, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_ba[2:0], ddr1_a[15:0], ddr2_csn0, ddr2_ck, ddr2_nck, ddr2_casn, ddr2_rasn, ddr2_wen, ddr2_ba[2:0], ddr2_a[15:0].

OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0], ddr2_dqm[3:0], ddr2_dqs[3:0], ddr2_dqsn[3:0], ddr2_d[31:0].

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NOTE

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BALL

RESET

STATE [7]

(1)

RESET

STATE [8]

BALL

REL.

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

CSI2

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

J11 cap_vbbldo_dspeve cap_vbbldo_dspeve CAP U13 cap_vbbldo_gpu cap_vbbldo_gpu CAP R19 cap_vbbldo_iva cap_vbbldo_iva CAP J19 cap_vbbldo_mpu cap_vbbldo_mpu CAP H11 cap_vddram_core1 cap_vddram_core1 CAP J17 cap_vddram_core2 cap_vddram_core2 CAP U15 cap_vddram_core3 cap_vddram_core3 CAP R17 cap_vddram_core4 cap_vddram_core4 CAP Y16 cap_vddram_core5 cap_vddram_core5 CAP G10 cap_vddram_dspeve1 cap_vddram_dspeve1 CAP H10 cap_vddram_dspeve2 cap_vddram_dspeve2 CAP T16 cap_vddram_gpu cap_vddram_gpu CAP R20 cap_vddram_iva cap_vddram_iva CAP J16 cap_vddram_mpu1 cap_vddram_mpu1 CAP J21 cap_vddram_mpu2 cap_vddram_mpu2 CAP AD17 csi2_0_dx0 csi2_0_dx0 0 I 1.8 vdda_csi Yes LVCMOS

AF16 csi2_0_dx1 csi2_0_dx1 0 I 1.8 vdda_csi Yes LVCMOS

AF19 csi2_0_dx2 csi2_0_dx2 0 I 1.8 vdda_csi Yes LVCMOS

AE15 csi2_0_dx3 csi2_0_dx3 0 I 1.8 vdda_csi Yes LVCMOS

AE19 csi2_0_dx4 csi2_0_dx4 0 I 1.8 vdda_csi Yes LVCMOS

AD18 csi2_0_dy0 csi2_0_dy0 0 I 1.8 vdda_csi Yes LVCMOS

AF17 csi2_0_dy1 csi2_0_dy1 0 I 1.8 vdda_csi Yes LVCMOS

AF20 csi2_0_dy2 csi2_0_dy2 0 I 1.8 vdda_csi Yes LVCMOS

AE16 csi2_0_dy3 csi2_0_dy3 0 I 1.8 vdda_csi Yes LVCMOS

AE18 csi2_0_dy4 csi2_0_dy4 0 I 1.8 vdda_csi Yes LVCMOS

AC13 csi2_1_dx0 csi2_1_dx0 0 I 1.8 vdda_csi Yes LVCMOS

AD15 csi2_1_dx1 csi2_1_dx1 0 I 1.8 vdda_csi Yes LVCMOS

AC16 csi2_1_dx2 csi2_1_dx2 0 I 1.8 vdda_csi Yes LVCMOS

MUXMODE

[5]

TYPE [6]

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

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SPRS993E –MARCH 2017–REVISED DECEMBER 2018

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Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

AC14 csi2_1_dy0 csi2_1_dy0 0 I 1.8 vdda_csi Yes LVCMOS

AD14 csi2_1_dy1 csi2_1_dy1 0 I 1.8 vdda_csi Yes LVCMOS

AC17 csi2_1_dy2 csi2_1_dy2 0 I 1.8 vdda_csi Yes LVCMOS

D19 dcan1_rx dcan1_rx

E19 dcan1_tx dcan1_tx

AG19 ddr1_casn ddr1_casn 0 O PD drive 1

AG24 ddr1_ck ddr1_ck 0 O PD drive clk

AH23 ddr1_cke ddr1_cke 0 O PD drive 0

T27 ddr1_dqm_ecc ddr1_dqm_ecc No 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

U28 ddr1_dqsn_ecc ddr1_dqsn_ecc No 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS

U27 ddr1_dqs_ecc ddr1_dqs_ecc No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS

AH24 ddr1_nck ddr1_nck 0 O PD drive clk

AH20 ddr1_rasn ddr1_rasn 0 O PD drive 1

AF23 ddr1_rst ddr1_rst 0 O PD drive 0

AG22 ddr1_wen ddr1_wen 0 O PD drive 1

T25 ddr2_casn ddr2_casn 0 O PD drive 1

mcan_rx uart8_txd 2 O mmc2_sdwp 3 I 0 sata1_led 4 O hdmi1_cec 6 IO gpio1_15 14 IO Driver off 15 I

mcan_tx uart8_rxd 2 I 1 mmc2_sdcd 3 I 1 hdmi1_hpd 6 I gpio1_14 14 IO Driver off 15 I

MUXMODE

0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

TYPE [6]

[5]

(1)

(continued)

BALL

RESET

STATE [7]

(OFF)

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.35/1.5/1.8 vdds_ddr1 No LVCMOS

1.35/1.5/1.8 vdds_ddr2 No LVCMOS

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

CSI2

Voltage LVCMOS

DDR

PULL UP/DOWN TYPE [14]

PU/PD

Pux/PDy

DSIS [15]

16

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DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

R28 ddr2_ck ddr2_ck 0 O PD drive clk

R25 ddr2_cke ddr2_cke 0 O PD drive 0

R27 ddr2_nck ddr2_nck 0 O PD drive clk

R26 ddr2_rasn ddr2_rasn 0 O PD drive 1

N25 ddr2_rst ddr2_rst 0 O PD drive 0

T24 ddr2_wen ddr2_wen 0 O PD drive 1

AE22 ddr1_a0 ddr1_a0 0 O PD drive 1

AD20 ddr1_a1 ddr1_a1 0 O PD drive 1

AE21 ddr1_a2 ddr1_a2 0 O PD drive 1

AD22 ddr1_a3 ddr1_a3 0 O PD drive 1

AE23 ddr1_a4 ddr1_a4 0 O PD drive 1

AH22 ddr1_a5 ddr1_a5 0 O PD drive 1

AD24 ddr1_a6 ddr1_a6 0 O PD drive 1

AC22 ddr1_a7 ddr1_a7 0 O PD drive 1

AG23 ddr1_a8 ddr1_a8 0 O PD drive 1

AF24 ddr1_a9 ddr1_a9 0 O PD drive 1

AD21 ddr1_a10 ddr1_a10 0 O PD drive 1

AE24 ddr1_a11 ddr1_a11 0 O PD drive 1

AG21 ddr1_a12 ddr1_a12 0 O PD drive 1

AF21 ddr1_a13 ddr1_a13 0 O PD drive 1

AC23 ddr1_a14 ddr1_a14 0 O PD drive 1

AG20 ddr1_a15 ddr1_a15 0 O PD drive 1

AE20 ddr1_ba0 ddr1_ba0 0 O PD drive 1

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

(OFF)

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.35/1.5/1.8 vdds_ddr2 No LVCMOS

1.35/1.5/1.8 vdds_ddr1 No LVCMOS

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

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Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

AC21 ddr1_ba1 ddr1_ba1 0 O PD drive 1

AH21 ddr1_ba2 ddr1_ba2 0 O PD drive 1

AD23 ddr1_csn0 ddr1_csn0 0 O PD drive 1

AE26 ddr1_d0 ddr1_d0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AE27 ddr1_d1 ddr1_d1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AF28 ddr1_d2 ddr1_d2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AH26 ddr1_d3 ddr1_d3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AF25 ddr1_d4 ddr1_d4 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AG27 ddr1_d5 ddr1_d5 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AF27 ddr1_d6 ddr1_d6 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AF26 ddr1_d7 ddr1_d7 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AB24 ddr1_d8 ddr1_d8 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AD27 ddr1_d9 ddr1_d9 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AE28 ddr1_d10 ddr1_d10 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AD28 ddr1_d11 ddr1_d11 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AD26 ddr1_d12 ddr1_d12 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AE25 ddr1_d13 ddr1_d13 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AD25 ddr1_d14 ddr1_d14 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AC26 ddr1_d15 ddr1_d15 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AA25 ddr1_d16 ddr1_d16 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AB25 ddr1_d17 ddr1_d17 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AA26 ddr1_d18 ddr1_d18 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AA28 ddr1_d19 ddr1_d19 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

(OFF)

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.35/1.5/1.8 vdds_ddr1 No LVCMOS

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

18

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DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

AA27 ddr1_d20 ddr1_d20 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AA24 ddr1_d21 ddr1_d21 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AC25 ddr1_d22 ddr1_d22 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

Y26 ddr1_d23 ddr1_d23 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

W26 ddr1_d24 ddr1_d24 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AB23 ddr1_d25 ddr1_d25 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

V24 ddr1_d26 ddr1_d26 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

Y24 ddr1_d27 ddr1_d27 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

W25 ddr1_d28 ddr1_d28 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

Y25 ddr1_d29 ddr1_d29 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

W24 ddr1_d30 ddr1_d30 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

Y28 ddr1_d31 ddr1_d31 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AG26 ddr1_dqm0 ddr1_dqm0 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AC24 ddr1_dqm1 ddr1_dqm1 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AB26 ddr1_dqm2 ddr1_dqm2 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

Y27 ddr1_dqm3 ddr1_dqm3 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AH25 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS

AC27 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS

AB27 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS

W28 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS

AG25 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS

AC28 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS

AB28 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

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Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

W27 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS

U25 ddr1_ecc_d0 ddr1_ecc_d0 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

U26 ddr1_ecc_d1 ddr1_ecc_d1 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

V25 ddr1_ecc_d2 ddr1_ecc_d2 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

V26 ddr1_ecc_d3 ddr1_ecc_d3 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

V27 ddr1_ecc_d4 ddr1_ecc_d4 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

T28 ddr1_ecc_d5 ddr1_ecc_d5 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

T26 ddr1_ecc_d6 ddr1_ecc_d6 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

V28 ddr1_ecc_d7 ddr1_ecc_d7 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AF22 ddr1_odt0 ddr1_odt0 0 O PD drive 0

AB22 ddr1_vref0 ddr1_vref0 0 PWR OFF OFF 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

P25 ddr2_a0 ddr2_a0 0 O PD drive 1

P26 ddr2_a1 ddr2_a1 0 O PD drive 1

P28 ddr2_a2 ddr2_a2 0 O PD drive 1

P27 ddr2_a3 ddr2_a3 0 O PD drive 1

P24 ddr2_a4 ddr2_a4 0 O PD drive 1

P23 ddr2_a5 ddr2_a5 0 O PD drive 1

N26 ddr2_a6 ddr2_a6 0 O PD drive 1

M25 ddr2_a7 ddr2_a7 0 O PD drive 1

N28 ddr2_a8 ddr2_a8 0 O PD drive 1

M27 ddr2_a9 ddr2_a9 0 O PD drive 1

L25 ddr2_a10 ddr2_a10 0 O PD drive 1

N27 ddr2_a11 ddr2_a11 0 O PD drive 1

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

(OFF)

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.35/1.5/1.8 vdds_ddr1 No LVCMOS

1.35/1.5/1.8 vdds_ddr2 No LVCMOS

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

20

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DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

M28 ddr2_a12 ddr2_a12 0 O PD drive 1

R24 ddr2_a13 ddr2_a13 0 O PD drive 1

N24 ddr2_a14 ddr2_a14 0 O PD drive 1

R23 ddr2_a15 ddr2_a15 0 O PD drive 1

L24 ddr2_ba0 ddr2_ba0 0 O PD drive 1

U24 ddr2_ba1 ddr2_ba1 0 O PD drive 1

M24 ddr2_ba2 ddr2_ba2 0 O PD drive 1

M26 ddr2_csn0 ddr2_csn0 0 O PD drive 1

C28 ddr2_d0 ddr2_d0 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

A26 ddr2_d1 ddr2_d1 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

E24 ddr2_d2 ddr2_d2 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

D25 ddr2_d3 ddr2_d3 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

D26 ddr2_d4 ddr2_d4 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

B27 ddr2_d5 ddr2_d5 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

B26 ddr2_d6 ddr2_d6 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

C26 ddr2_d7 ddr2_d7 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

F26 ddr2_d8 ddr2_d8 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

E25 ddr2_d9 ddr2_d9 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

E26 ddr2_d10 ddr2_d10 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

G27 ddr2_d11 ddr2_d11 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

E28 ddr2_d12 ddr2_d12 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

G26 ddr2_d13 ddr2_d13 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

G28 ddr2_d14 ddr2_d14 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

(OFF)

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.35/1.5/1.8 vdds_ddr2 No LVCMOS

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

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Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

F25 ddr2_d15 ddr2_d15 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

G25 ddr2_d16 ddr2_d16 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

G24 ddr2_d17 ddr2_d17 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

F23 ddr2_d18 ddr2_d18 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

F24 ddr2_d19 ddr2_d19 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

H28 ddr2_d20 ddr2_d20 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

H25 ddr2_d21 ddr2_d21 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

H27 ddr2_d22 ddr2_d22 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

H26 ddr2_d23 ddr2_d23 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

K27 ddr2_d24 ddr2_d24 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

K26 ddr2_d25 ddr2_d25 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

J25 ddr2_d26 ddr2_d26 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

K28 ddr2_d27 ddr2_d27 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

H24 ddr2_d28 ddr2_d28 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

J24 ddr2_d29 ddr2_d29 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

K24 ddr2_d30 ddr2_d30 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

L26 ddr2_d31 ddr2_d31 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

C27 ddr2_dqm0 ddr2_dqm0 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

E27 ddr2_dqm1 ddr2_dqm1 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

G23 ddr2_dqm2 ddr2_dqm2 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

J26 ddr2_dqm3 ddr2_dqm3 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

D28 ddr2_dqs0 ddr2_dqs0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS

F27 ddr2_dqs1 ddr2_dqs1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

22

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DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

J27 ddr2_dqs2 ddr2_dqs2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS

L28 ddr2_dqs3 ddr2_dqs3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS

D27 ddr2_dqsn0 ddr2_dqsn0 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS

F28 ddr2_dqsn1 ddr2_dqsn1 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS

J28 ddr2_dqsn2 ddr2_dqsn2 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS

L27 ddr2_dqsn3 ddr2_dqsn3 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS

K25 ddr2_odt0 ddr2_odt0 0 O PD drive 0

M22 ddr2_vref0 ddr2_vref0 0 PWR OFF OFF 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

F19 emu0 emu0 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual

gpio8_30 14 IO

C23 emu1 emu1 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual

gpio8_31 14 IO

AC5 gpio6_10 gpio6_10 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

mdio_mclk 1 O 1 i2c3_sda 2 IO 1 usb3_ulpi_d7 3 IO 0 vin2b_hsync1 4 I ehrpwm2A 10 O gpio6_10 14 IO Driver off 15 I

AB4 gpio6_11 gpio6_11 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

mdio_d 1 IO 1 i2c3_scl 2 IO 1 usb3_ulpi_d6 3 IO 0 vin2b_vsync1 4 I ehrpwm2B 10 O gpio6_11 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

(OFF)

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.35/1.5/1.8 vdds_ddr2 No LVCMOS

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

Pux/PDy

PU/PD

DSIS [15]

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DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

www.ti.com

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

E21 gpio6_14 gpio6_14 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

mcasp1_axr8 1 IO 0 dcan2_tx

mcan_tx uart10_rxd 3 I 1 vout2_hsync 6 O vin4a_hsync0 8 I 0 i2c3_sda 9 IO 1 timer1 10 IO gpio6_14 14 IO Driver off 15 I

F17 gpio6_15 gpio6_15 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

mcasp1_axr9 1 IO 0 dcan2_rx

mcan_rx uart10_txd 3 O vout2_vsync 6 O vin4a_vsync0 8 I 0 i2c3_scl 9 IO 1 timer2 10 IO gpio6_15 14 IO Driver off 15 I

F18 gpio6_16 gpio6_16 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

mcasp1_axr10 1 IO 0 vout2_fld 6 O vin4a_fld0 8 I 0 clkout1 9 O timer3 10 IO gpio6_16 14 IO Driver off 15 I

MUXMODE

[5]

2 IO

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

24

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DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

P6 gpmc_a0 gpmc_a0 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d16 2 I 0 vout3_d16 3 O vin4a_d0 4 I 0 vin4b_d0 6 I 0 i2c4_scl 7 IO 1 uart5_rxd 8 I 1 gpio7_3

gpmc_a26 gpmc_a16

Driver off 15 I

J6 gpmc_a1 gpmc_a1 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d17 2 I 0 vout3_d17 3 O vin4a_d1 4 I 0 vin4b_d1 6 I 0 i2c4_sda 7 IO 1 uart5_txd 8 O gpio7_4 14 IO Driver off 15 I

R4 gpmc_a2 gpmc_a2 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d18 2 I 0 vout3_d18 3 O vin4a_d2 4 I 0 vin4b_d2 6 I 0 uart7_rxd 7 I 1 uart5_ctsn 8 I 1 gpio7_5 14 IO Driver off 15 I

MUXMODE

[5]

14 IO

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

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DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

www.ti.com

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

R5 gpmc_a3 gpmc_a3 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_cs2 1 O 1 vin3a_d19 2 I 0 vout3_d19 3 O vin4a_d3 4 I 0 vin4b_d3 6 I 0 uart7_txd 7 O uart5_rtsn 8 O gpio7_6 14 IO Driver off 15 I

M6 gpmc_a4 gpmc_a4 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_cs3 1 O 1 vin3a_d20 2 I 0 vout3_d20 3 O vin4a_d4 4 I 0 vin4b_d4 6 I 0 i2c5_scl 7 IO 1 uart6_rxd 8 I 1 gpio1_26 14 IO Driver off 15 I

K4 gpmc_a5 gpmc_a5 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d21 2 I 0 vout3_d21 3 O vin4a_d5 4 I 0 vin4b_d5 6 I 0 i2c5_sda 7 IO 1 uart6_txd 8 O gpio1_27 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

26

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DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

P5 gpmc_a6 gpmc_a6 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d22 2 I 0 vout3_d22 3 O vin4a_d6 4 I 0 vin4b_d6 6 I 0 uart8_rxd 7 I 1 uart6_ctsn 8 I 1 gpio1_28 14 IO Driver off 15 I

N6 gpmc_a7 gpmc_a7 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d23 2 I 0 vout3_d23 3 O vin4a_d7 4 I 0 vin4b_d7 6 I 0 uart8_txd 7 O uart6_rtsn 8 O gpio1_29 14 IO Driver off 15 I

N4 gpmc_a8 gpmc_a8 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_hsync0 2 I 0 vout3_hsync 3 O vin4b_hsync1 6 I 0 timer12 7 IO spi4_sclk 8 IO 0 gpio1_30 14 IO Driver off 15 I

R3 gpmc_a9 gpmc_a9 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_vsync0 2 I 0 vout3_vsync 3 O vin4b_vsync1 6 I 0 timer11 7 IO spi4_d1 8 IO 0 gpio1_31 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

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DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

www.ti.com

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

J5 gpmc_a10 gpmc_a10 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_de0 2 I 0 vout3_de 3 O vin4b_clk1 6 I 0 timer10 7 IO spi4_d0 8 IO 0 gpio2_0 14 IO Driver off 15 I

K5 gpmc_a11 gpmc_a11 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_fld0 2 I 0 vout3_fld 3 O vin4a_fld0 4 I 0 vin4b_de1 6 I 0 timer9 7 IO spi4_cs0 8 IO 1 gpio2_1 14 IO Driver off 15 I

P4 gpmc_a12 gpmc_a12 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin4a_clk0 4 I 0 gpmc_a0 5 O vin4b_fld1 6 I 0 timer8 7 IO spi4_cs1 8 IO 1 dma_evt1 9 I 0 gpio2_2 14 IO Driver off 15 I

R2 gpmc_a13 gpmc_a13 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_rtclk 1 I 0 vin4a_hsync0 4 I 0 timer7 7 IO spi4_cs2 8 IO 1 dma_evt2 9 I 0 gpio2_3 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

28

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DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

R6 gpmc_a14 gpmc_a14 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_d3 1 I 0 vin4a_vsync0 4 I 0 timer6 7 IO spi4_cs3 8 IO 1 gpio2_4 14 IO Driver off 15 I

T2 gpmc_a15 gpmc_a15 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_d2 1 I 0 vin4a_d8 4 I 0 timer5 7 IO gpio2_5 14 IO Driver off 15 I

U1 gpmc_a16 gpmc_a16 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_d0 1 IO 0 vin4a_d9 4 I 0 gpio2_6 14 IO Driver off 15 I

P3 gpmc_a17 gpmc_a17 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_d1 1 I 0 vin4a_d10 4 I 0 gpio2_7 14 IO Driver off 15 I

R1 gpmc_a18 gpmc_a18 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_sclk 1 O vin4a_d11 4 I 0 gpio2_8 14 IO Driver off 15 I

H6 gpmc_a19 gpmc_a19 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat4 1 IO 1 gpmc_a13 2 O vin4a_d12 4 I 0 vin3b_d0 6 I 0 gpio2_9 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

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DRA77P, DRA76P

SPRS993E –MARCH 2017–REVISED DECEMBER 2018

www.ti.com

Table 4-1. Pin Attributes

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 76x [4]

G6 gpmc_a20 gpmc_a20 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat5 1 IO 1 gpmc_a14 2 O vin4a_d13 4 I 0 vin3b_d1 6 I 0 gpio2_10 14 IO Driver off 15 I

J4 gpmc_a21 gpmc_a21 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat6 1 IO 1 gpmc_a15 2 O vin4a_d14 4 I 0 vin3b_d2 6 I 0 gpio2_11 14 IO Driver off 15 I

F5 gpmc_a22 gpmc_a22 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat7 1 IO 1 gpmc_a16 2 O vin4a_d15 4 I 0 vin3b_d3 6 I 0 gpio2_12 14 IO Driver off 15 I

G5 gpmc_a23 gpmc_a23 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_clk 1 IO 1 gpmc_a17 2 O vin4a_fld0 4 I 0 vin3b_d4 6 I 0 gpio2_13 14 IO Driver off 15 I

J3 gpmc_a24 gpmc_a24 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat0 1 IO 1 gpmc_a18 2 O vin3b_d5 6 I 0 gpio2_14 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

30

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Texas Instruments DRA77P, DRA76P Datasheet

1 Device Overview

1.1 Features

1.2 Applications

1.3 Description

1.4 Functional Block Diagram

Table of Contents

2 Revision History

3 Device Comparison

3.1 Device Comparison Table

3.2 Related Products

4 Terminal Configuration and Functions

4.1 Pin Diagram

4.2 Pin Attributes