Datasheet DRA756, DRA755, DRA754, DRA752, DRA751 Datasheet (Texas Instruments)

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DRA75x, DRA74x Infotainment Applications Processor

Silicon Revision 2.0

1 Device Overview

1.1 Features

1

• Architecture designed for infotainment applications

• Video, image, and graphics processing support – Full-HD video (1920 × 1080p, 60 fps) – Multiple video input and video output – 2D and 3D graphics

• Dual Arm®Cortex®-A15 microprocessor subsystem

• Up to two C66x floating-point VLIW DSP – Fully object-code compatible with C67x and

C64x+

– Up to thirty-two 16 x 16-Bit fixed-point multiplies

per cycle

• Up to 2.5MB of on-chip L3 RAM

• Level 3 (L3) and level 4 (L4) interconnects

• Two DDR2/DDR3/DDR3L memory interface (EMIF) modules

– Supports up to DDR2-800 and DDR3-1066 – Up to 2GB supported per EMIF

• Dual Arm®Cortex®-M4 Image Processing Units (IPU)

• Up to two Embedded Vision Engines (EVEs)

• IVA subsystem

• Display subsystem – Display controller with DMA engine and up to

three pipelines

– HDMI™ encoder: HDMI 1.4a and DVI 1.0

compliant

• Video Processing Engine (VPE)

• 2D-graphics accelerator (BB2D) subsystem – Vivante®GC320 core

• Dual-core PowerVR®SGX544 3D GPU

• Three Video Input Port (VIP) modules – Support for up to 10 multiplexed input ports

• General-Purpose Memory Controller (GPMC)

• Enhanced Direct Memory Access (EDMA) controller

• 2-port gigabit ethernet (GMAC)

DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

• Sixteen 32-Bit general-purpose timers

• 32-Bit MPU watchdog timer

• Five Inter-Integrated Circuit ( I2C™) ports

• HDQ™/ 1-Wire®interface

• SATA interface

• MediaLB®(MLB) subsystem

• Ten configurable UART/IrDA/CIR modules

• Four Multichannel Serial Peripheral Interfaces (McSPI)

• Quad SPI (QSPI)

• Eight Multichannel Audio Serial Port (McASP) modules

• SuperSpeed USB 3.0 dual-role device

• Three high-speed USB 2.0 dual-role devices

• Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces ( MMC™/ SD®/SDIO)

• PCI-Express®3.0 subsystems with two 5-Gbps lanes

– One 2-lane gen2-compliant port – or Two 1-lane gen2-compliant ports

• Dual Controller Area Network (DCAN) modules – CAN 2.0B protocol

• Up to 247 General-Purpose I/O (GPIO) pins

• Real-Time Clock SubSystem (RTCSS)

• Device security features – Hardware crypto accelerators and DMA – Firewalls – JTAG®lock – Secure keys – Secure ROM and boot

• Power, Reset, and Clock Management (PRCM)

• On-chip debug with CTools technology

• 28-nm CMOS technology

• 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

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1.2 Applications

• Human-machine interface (HMI)

• Navigation

• Digital and analog radio

• Rear seat entertainment

1.3 Description

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm®Cortex®-A15 RISC CPUs with Arm®Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

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• Multimedia playback

• Web browsing

• ADAS integration

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.

Device Information

PART NUMBER PACKAGE BODY SIZE

DRA756ABC FCBGA (760) 23.0 mm × 23.0 mm DRA755ABC FCBGA (760) 23.0 mm × 23.0 mm DRA754ABC FCBGA (760) 23.0 mm × 23.0 mm DRA756ABC FCBGA (760) 23.0 mm × 23.0 mm DRA755ABC FCBGA (760) 23.0 mm × 23.0 mm DRA754ABC FCBGA (760) 23.0 mm × 23.0 mm DRA752ABC FCBGA (760) 23.0 mm × 23.0 mm DRA751ABC FCBGA (760) 23.0 mm × 23.0 mm DRA750ABC FCBGA (760) 23.0 mm × 23.0 mm

(1) For more information, see Section 10, Mechanical, Packaging, and Orderable Information.

(1)

2

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Program/Data Storage

Serial Interfaces

Connectivity

I2C x5

UART x10

McSPI x4

DCAN x2

McASP x8

Display Subsystem

LCD2

LCD1

System

Spinlock

1xGFX / 3xVID

Blend / Scale

(2x Arm

Cortex–A15)

DSP1 C66x

Co-Processors

PCIe SS x2

Mailbox x13

GPIO x8

Timers x16

WDT

MediaLB /

MOST150

GMAC AVB

up to 2.5MiB RAM w/ ECC

SATA

(NAND/NOR/

Async)

MMC / SD x4

2x 32b

DMM

2x VCP

HD ATL

(Dual-Core SGX544 3D)

BB2D

320 2D)

VIP1

HDMI 1.4a

QSPI

3x USB 2.0

Dual Mode FS/HS

1x w/ PHY

2x w/ ULPI

LCD3

EDMA

sDMA

2x EVE

Analytic

Processors

2x MMU

VPE

PWM SS x3

intro_001

RTC SS

KBDHDQ

1x USB 3.0

FS/HS/SS

Dual Mode w/PHY

GPMC / ELM

DDR2/3 w/ECC

(1)

EMIF x2

256KiB

ROM

OCMC

DRA75x / DRA74x

(GC

GPU

MPU

DSP2 C66x

Co-Processors

(Dual Cortex–M4)

IPU1

(Dual Cortex–M4)

IPU1

IPU2

VIP2 VIP3

IVA HD

1080p Video

Co-Processor

Radio Accelerators

High-Speed Interconnect

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1.4 Functional Block Diagram

Figure 1-1 is functional block diagram for the device.

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(1) ECC is only available on EMIF1.

Figure 1-1. DRA75x, DRA74x Block Diagram

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2 Revision History

Changes from November 30, 2018 to May 15, 2019 (from E Revision (November 2018) to F Revision) Page

• Fixed type direction to “O” for mii1_txer and mii0_txer signals in Table 4-20, GMAC Signal Descriptions............ 122

• Added clarification notes for EMU[1:0] connections in Table 4-23, GPIOs Signal Descriptions and Table 4-27,

Debug Signal Descriptions ....................................................................................................... 125

• Added MII_TXER timing to GMAC MII Timings section ...................................................................... 301

• Updated MDIO Timing Diagram and MDIO7 parameter values............................................................. 303

• Added note regarding DDR ECC solutions to Table 8-43, Supported DDR3 Device Combinations ................... 409

• Added clarifications about validated DDR topology in Section 8.7.3.15, CK and ADDR_CTRL Topologies and

Routing Definition.................................................................................................................. 419

• Updated a note for cosmetic marks on the package.......................................................................... 432

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3 Device Comparison

Table 3-1 shows a comparison between devices, highlighting the differences.

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Table 3-1. Device Comparison

FEATURES

DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Features

CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24] Base PN register bitfield value

Processors/ Accelerators

Speed Grades P L J P L J P L J Dual Arm Cortex-A15 Microprocessor

Subsystem (MPU)

C66x VLIW DSP

BitBLT 2D Hardware Acceleration Engine (BB2D)

Display Subsystem

Embedded Vision Engine (EVE)

Dual Arm Cortex-M4 Image Processing Unit (IPU)

Image Video Accelarator (IVA) IVA Yes Yes Yes SGX544 Dual-Core 3D Graphics Processing

Unit (GPU)

(3)(4)

MPU core 0 Yes Yes Yes MPU core 1 Yes Yes Yes DSP1 Yes Yes Yes DSP2 Yes Yes No

BB2D Yes Yes Yes VOUT1 Yes Yes Yes

VOUT2 Yes Yes Yes VOUT3 Yes Yes Yes HDMI Yes Yes Yes EVE1 Yes No No EVE2 Yes No No IPU1 Yes Yes Yes IPU2 Yes Yes Yes

GPU Yes Yes Yes

15 (0xF) 14 (0xE) 13 (0xD) 11 (0xB) 10 (0xA) 9 (0x9) 7 (0x7) 6 (0x6) 5 (0x5)

Jacinto 6 EX Jacinto 6 EP Jacinto 6

(4)

DEVICE

6

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Table 3-1. Device Comparison

FEATURES

DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

vin1a Yes Yes No

VIP1

Video Input Port (VIP)

VIP2

VIP3

Video Processing Engine (VPE) VPE Yes Yes Yes

Program/Data Storage

On-Chip Shared Memory (RAM)

General-Purpose Memory Controller (GPMC) GPMC Yes Yes Yes

DDR2/DDR3 Memory Controller

Dynamic Memory Manager (DMM) DMM Yes Yes Yes

Radio Support

Audio Tracking Logic (ATL) ATL Yes Yes Yes

Viterbi Coprocessor (VCP)

Peripherals

Dual Controller Area Network Interface (DCAN)

Enhanced DMA (EDMA) EDMA Yes Yes Yes System DMA (DMA_SYSTEM) DMA_SYSTEM Yes Yes Yes

Ethernet Subsystem (Ethernet SS)

General-Purpose I/O (GPIO) GPIO up to 247 up to 247 up to 247

(2)

vin1b Yes Yes No vin2a Yes Yes Yes vin2b Yes Yes Yes vin3a Yes Yes Yes vin3b Yes Yes Yes vin4a Yes Yes Yes vin4b Yes Yes Yes vin5a Yes Yes No vin6a Yes Yes No

OCMC_RAM1 512KB 512KB 512KB OCMC_RAM2 1MB No No OCMC_RAM3 1MB No No

EMIF1 up to 2GB (with optional SECDED) up to 2GB (with optional SECDED) up to 2GB EMIF2 up to 2GB up to 2GB up to 2GB

VCP1 Yes Yes Yes VCP2 Yes Yes Yes

DCAN1 Yes Yes Yes DCAN2 Yes Yes Yes

GMAC_SW[0] MII, RMII, or RGMII MII, RMII, or RGMII MII, RMII, or RGMII GMAC_SW[1] MII, RMII, or RGMII MII, RMII, or RGMII MII, RMII, or RGMII

Jacinto 6 EX Jacinto 6 EP Jacinto 6

(4)

(continued)

DEVICE

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Table 3-1. Device Comparison

FEATURES

DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

Inter-Integrated Circuit Interface (I2C) I2C 5 5 5 System Mailbox Module MAILBOX 13 13 13 Media Local Bus Subsystem (MLBSS) MLB Yes Yes Yes

McASP1 16 serializers 16 serializers 16 serializers McASP2 16 serializers 16 serializers 16 serializers McASP3 4 serializers 4 serializers 4 serializers

Multichannel Audio Serial Port (McASP)

MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO)

PCI Express 3.0 Port with Integrated PHY

SATA SATA Yes Yes Yes Real-Time Clock Subsystem (RTCSS) RTCSS Yes Yes Yes Multichannel Serial Peripheral Interface (McSPI) McSPI 4 4 4 HDQ1W HDQ1W Yes Yes Yes Quad SPI (QSPI) QSPI Yes Yes Yes Spinlock Module SPINLOCK Yes Yes Yes Keyboard Controller (KBD) KBD Yes Yes Yes Timers, General-Purpose TIMER 16 16 16

Timer, Watchdog

Pulse-Width Modulation Subsystem (PWMSS)

Universal Asynchronous Receiver/Transmitter (UART)

McASP4 4 serializers 4 serializers 4 serializers McASP5 4 serializers 4 serializers 4 serializers McASP6 4 serializers 4 serializers 4 serializers McASP7 4 serializers 4 serializers 4 serializers McASP8 4 serializers 4 serializers 4 serializers MMC1 1x UHSI 4b 1x UHSI 4b 1x UHSI 4b MMC2 1x eMMC™ 8b 1x eMMC 8b 1x eMMC 8b MMC3 1x SDIO 8b 1x SDIO 8b 1x SDIO 8b MMC4 1x SDIO 4b 1x SDIO 4b 1x SDIO 4b PCIe_SS1 Yes Yes Yes (Single-lane mode) PCIe_SS2 Yes Yes No

WATCHDOG TIMER

PWMSS1 Yes Yes Yes PWMSS2 Yes Yes Yes PWMSS3 Yes Yes Yes

UART 10 10 10

Jacinto 6 EX Jacinto 6 EP Jacinto 6

Yes Yes Yes

(4)

(continued)

DEVICE

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Table 3-1. Device Comparison

FEATURES

DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

USB1

Universal Serial Bus (USB3.0)

Universal Serial Bus (USB2.0)

(1) USB4 will not be supported on some pin-compatible roadmap devices. USB3 will be mapped to these balls instead. Pin compatibility can be maintained in the future by either not using

USB4, or via software change to use USB4 on this device, but USB3 on these balls in the future.

(2) In the Unified L3 memory map, there is maximum of 2GB of SDRAM space which is available to all L3 initiators including MPU (MPU, GPU, DSP, IVA, DMA, etc). Typically this space is

interleaved across both EMIFs to optimize memory performance. If a system populates > 2GB of physical memory, that additional addressable space can be accessed only by the MPU via the Arm V7 Large Physical Address Extensions (LPAE).

(3) For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bitfield, see the DRA75x, DRA74x SoC for Automotive Infotainment Silicon Revision 2.0, 1.x. (4) X5777x is the base part number for the superset device. Software should constrain the features used to match the intended production device. The Base PN register bitfield value is 0x3F.

(SuperSpeed, Dual-Role-Device [DRD])

USB2 (HighSpeed, Dual-Role-Device [DRD], with embedded HS PHY)

USB3 (HighSpeed, OTG2.0, with ULPI)

USB4 (HighSpeed, OTG2.0, with ULPI)

Jacinto 6 EX Jacinto 6 EP Jacinto 6

Yes Yes Yes

(4)

(continued)

DEVICE

(1)

3.1 Related Products

Automotive Processors DRAx Infotainment SoCs The "Jacinto 6" family of infotainment processors (DRA7xx), paired with robust software and ecosystem offering bring

unprecedented feature-rich, in-vehicle infotainment, instrument cluster and telematics features to the next generation automobiles.

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4 Terminal Configuration and Functions

4.1 Terminal Assignment

Figure 4-1 shows the ball locations for the 760 plastic ball grid array (PBGA) package and are used in

conjunction with Table 4-2 through Table 4-34 to locate signal names and ball grid numbers.

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Figure 4-1. ABC S-PBGA-N760 Package (Bottom View)

The following bottom balls are not connected: AF7 / AF10 / AF13 / AF16 / AF19 / AE4 / AE25 / AB26 / W3 / W26 / T3 / T26 / N3 / N26 / K3 / K26 / G3 / D4 / D25 / C10 / C13 / C16 / C19 / C22.

These balls do not exist on the package.

4.1.1 Unused Balls Connection Requirements

This section describes the Unused/Reserved balls connection requirements.

The following balls are reserved: A27 / K14 / Y5 / Y10 / B28 These balls must be left unconnected.

All unused power supply balls must be supplied with the voltages specified in the

Section 5.4, Recommended Operating Conditions, unless alternative tie-off options are

included in Section 4.4, Signal Descriptions.

Table 4-1. Unused Balls Specific Connection Requirements

NOTE

BALLS CONNECTION REQUIREMENTS

AE15 / AC15 / AE14 / D20 / AD17 / AC17 / AC16 / AB16 / V27 /

AH25 / AE27 / AD27 / Y28 / G28 / H27 / K27 / M28

E20 / D21 / E23 / C20 / C21 / V28 / F18 / AG25 / AE28 / AD28 / Y27

10

/ G27 / H28 / K28 / M27 / F17 / C25

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These balls must be connected to GND through an external pull resistor if unused

These balls must be connected to the corresponding power supply through an external pull resistor if unused

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Table 4-1. Unused Balls Specific Connection Requirements (continued)

BALLS CONNECTION REQUIREMENTS

AF14 (rtc_iso)

AB17 (rtc_porz)

All other unused signal balls with a Pad Configuration Register can be left unconnected with their internal pullup or pulldown resistor enabled.

All other unused signal balls without Pad Configuration Register can be left unconnected.

4.2 Ball Characteristics

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This ball should be connected to the corresponding power supply through an external pull resistor if unused; or can be connected to

F22 (porz) when RTC unused (level translation may be needed)

This ball should be connected to VSS when RTC is unused; or can be connected to F22 (porz) when RTC unused (level translation may be needed)

NOTE

Table 4-2 describes the terminal characteristics and the signals multiplexed on each ball. The following list

describes the table column headers:

1. BALL NUMBER: Ball number(s) on the bottom side associated with each signal on the bottom.

2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).

3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).

NOTE

Table 4-2 does not take into account the subsystem multiplexing signals. Subsystem

multiplexing signals are described in Section 4.4, Signal Descriptions.

NOTE

In the Driver off mode, the buffer is configured in high-impedance.

4. 74x: This column shows if the functionality is applicable for DRA74x devices. Note that the ball characteristics table presents the functionality of DRA75x device. An empty box means "Yes".

5. MUXMODE: Multiplexing mode number:

a. MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function

mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily the default muxmode.

NOTE

The default mode is the mode at the release of the reset; also see the RESET REL. MUXMODE column.

b. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some

muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.

c. An empty box means Not Applicable.

6. TYPE: Signal type and direction: – I = Input

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– O = Output – IO = Input or Output – D = Open drain – DS = Differential Signaling – A = Analog – PWR = Power – GND = Ground – CAP = LDO Capacitor

7. BALL RESET STATE: The state of the terminal at power-on reset: – drive 0 (OFF): The buffer drives VOL(pulldown or pullup resistor not activated)

– drive 1 (OFF): The buffer drives VOH(pulldown or pullup resistor not activated) – OFF: High-impedance – PD: High-impedance with an active pulldown resistor – PU: High-impedance with an active pullup resistor – An empty box means Not Applicable

8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal)

– drive 0 (OFF): The buffer drives VOL(pulldown or pullup resistor not activated) – drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated) – drive 1 (OFF): The buffer drives VOH(pulldown or pullup resistor not activated) – OFF: High-impedance – PD: High-impedance with an active pulldown resistor – PU: High-impedance with an active pullup resistor – An empty box means Not Applicable

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NOTE

For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see the Power Reset and Clock Management / PRCM Reset Management Functional Description section of the Device TRM.

9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).

An empty box means Not Applicable.

10. IO VOLTAGE VALUE: This column describes the IO voltage value (VDDS supply). An empty box means Not Applicable.

11. POWER: The voltage supply that powers the terminal IO buffers. An empty box means Not Applicable.

12. HYS: Indicates if the input buffer is with hysteresis: – Yes: With hysteresis

– No: Without hysteresis – An empty box: Not Applicable

NOTE

For more information, see the hysteresis values in Section 5.7, Electrical Characteristics.

13. BUFFER TYPE: Drive strength of the associated output buffer. An empty box means Not Applicable.

12

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14. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor.

15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or

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NOTE

For programmable buffer strength: – The default value is given in Table 4-2. – A note describes all possible values according to the selected muxmode.

Pullup and pulldown resistors can be enabled or disabled via software. – PU: Internal pullup

– PD: Internal pulldown – PU/PD: Internal pullup and pulldown – PUx/PDy: Programmable internal pullup and pulldown – PDy: Programmable internal pulldown – An empty box means No pull

logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers. – 0: Logic 0 driven on the peripheral's input signal port.

– 1: Logic 1 driven on the peripheral's input signal port. – blank: Pin state driven on the peripheral's input signal port.

NOTE

Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration. (Hi-Z mode is not an input signal.)

NOTE

When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

CAUTION

Peripherals exposed in Ball Characteristics Table and Multiplexing Characteristics Table represent functionality of a DRA75x device. Not all exposed peripherals are supported on DRA7xx devices. For peripherals supported on DRA7xx family of products please refer to Table 3-1, Device Comparison.

NOTE

Some of the DDR1 and DDR2 signals have an additional state change at the release of porz. The state that the signals change to at the release of porz is as follows:

drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_nck, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_ba[2:0], ddr1_a[15:0], ddr2_csn0, ddr2_ck, ddr2_nck, ddr2_casn, ddr2_rasn, ddr2_wen, ddr2_ba[2:0], ddr2_a[15:0].

OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0], ddr2_dqm[3:0], ddr2_dqs[3:0], ddr2_dqsn[3:0], ddr2_d[31:0].

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

K9 cap_vbbldo_dspeve cap_vbbldo_dspeve CAP Y14 cap_vbbldo_gpu cap_vbbldo_gpu CAP R20 cap_vbbldo_iva cap_vbbldo_iva CAP J16 cap_vbbldo_mpu cap_vbbldo_mpu CAP L9 cap_vddram_core1 cap_vddram_core1 CAP J19 cap_vddram_core2 cap_vddram_core2 CAP Y15 cap_vddram_core3 cap_vddram_core3 CAP P19 cap_vddram_core4 cap_vddram_core4 CAP Y16 cap_vddram_core5 cap_vddram_core5 CAP J10 cap_vddram_dspeve1 cap_vddram_dspeve1 CAP J9 cap_vddram_dspeve2 cap_vddram_dspeve2 CAP Y13 cap_vddram_gpu cap_vddram_gpu CAP T20 cap_vddram_iva cap_vddram_iva CAP K16 cap_vddram_mpu1 cap_vddram_mpu1 CAP K19 cap_vddram_mpu2 cap_vddram_mpu2 CAP G19 dcan1_rx dcan1_rx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

uart8_txd 2 O mmc2_sdwp 3 I 0 sata1_led 4 O hdmi1_cec 6 IO gpio1_15 14 IO Driver off 15 I

G20 dcan1_tx dcan1_tx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

uart8_rxd 2 I 1 mmc2_sdcd 3 I 1 hdmi1_hpd 6 I gpio1_14 14 IO Driver off 15 I

AD20 ddr1_a0 ddr1_a0 0 O PD drive 1

AC19 ddr1_a1 ddr1_a1 0 O PD drive 1

AD21 ddr1_a10 ddr1_a10 0 O PD drive 1

AD22 ddr1_a11 ddr1_a11 0 O PD drive 1

AC21 ddr1_a12 ddr1_a12 0 O PD drive 1

MUXMODE

[5]

TYPE [6]

BALL

RESET

STATE [7]

(1)

BALL

RESET

REL.

STATE [8]

(OFF)

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.35/1.5/1.8 vdds_ddr1 No LVCMOS

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

DDR

PULL UP/DOWN TYPE [14]

PU/PD 1

Pux/PDy

DSIS [15]

14

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SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AF18 ddr1_a13 ddr1_a13 0 O PD drive 1

AE17 ddr1_a14 ddr1_a14 0 O PD drive 1

AD18 ddr1_a15 ddr1_a15 0 O PD drive 1

AC20 ddr1_a2 ddr1_a2 0 O PD drive 1

AB19 ddr1_a3 ddr1_a3 0 O PD drive 1

AF21 ddr1_a4 ddr1_a4 0 O PD drive 1

AH22 ddr1_a5 ddr1_a5 0 O PD drive 1

AG23 ddr1_a6 ddr1_a6 0 O PD drive 1

AE21 ddr1_a7 ddr1_a7 0 O PD drive 1

AF22 ddr1_a8 ddr1_a8 0 O PD drive 1

AE22 ddr1_a9 ddr1_a9 0 O PD drive 1

AF17 ddr1_ba0 ddr1_ba0 0 O PD drive 1

AE18 ddr1_ba1 ddr1_ba1 0 O PD drive 1

AB18 ddr1_ba2 ddr1_ba2 0 O PD drive 1

AC18 ddr1_casn ddr1_casn 0 O PD drive 1

AG24 ddr1_ck ddr1_ck 0 O PD drive clk

AG22 ddr1_cke ddr1_cke 0 O PD drive 0

AH23 ddr1_csn0 ddr1_csn0 0 O PD drive 1

AF25 ddr1_d0 ddr1_d0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AF26 ddr1_d1 ddr1_d1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AG27 ddr1_d10 ddr1_d10 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AF28 ddr1_d11 ddr1_d11 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AE26 ddr1_d12 ddr1_d12 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

(OFF)

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.35/1.5/1.8 vdds_ddr1 No LVCMOS

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

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SPRS950F –DECEMBER 2015–REVISED MAY 2019

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AC25 ddr1_d13 ddr1_d13 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AC24 ddr1_d14 ddr1_d14 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AD25 ddr1_d15 ddr1_d15 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

V20 ddr1_d16 ddr1_d16 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

W20 ddr1_d17 ddr1_d17 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AB28 ddr1_d18 ddr1_d18 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AC28 ddr1_d19 ddr1_d19 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AG26 ddr1_d2 ddr1_d2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AC27 ddr1_d20 ddr1_d20 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

Y19 ddr1_d21 ddr1_d21 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AB27 ddr1_d22 ddr1_d22 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

Y20 ddr1_d23 ddr1_d23 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AA23 ddr1_d24 ddr1_d24 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

Y22 ddr1_d25 ddr1_d25 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

Y23 ddr1_d26 ddr1_d26 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AA24 ddr1_d27 ddr1_d27 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

Y24 ddr1_d28 ddr1_d28 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AA26 ddr1_d29 ddr1_d29 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AH26 ddr1_d3 ddr1_d3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AA25 ddr1_d30 ddr1_d30 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AA28 ddr1_d31 ddr1_d31 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AF24 ddr1_d4 ddr1_d4 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AE24 ddr1_d5 ddr1_d5 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

16

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SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AF23 ddr1_d6 ddr1_d6 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AE23 ddr1_d7 ddr1_d7 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AC23 ddr1_d8 ddr1_d8 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AF27 ddr1_d9 ddr1_d9 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AD23 ddr1_dqm0 ddr1_dqm0 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AB23 ddr1_dqm1 ddr1_dqm1 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AC26 ddr1_dqm2 ddr1_dqm2 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AA27 ddr1_dqm3 ddr1_dqm3 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

V26 ddr1_dqm_ecc ddr1_dqm_ecc No 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AH25 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS

AE27 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS

AD27 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS

Y28 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS

AG25 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS

AE28 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS

AD28 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS

Y27 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS

V28 ddr1_dqsn_ecc ddr1_dqsn_ecc No 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS

V27 ddr1_dqs_ecc ddr1_dqs_ecc No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS

W22 ddr1_ecc_d0 ddr1_ecc_d0 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

V23 ddr1_ecc_d1 ddr1_ecc_d1 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

W19 ddr1_ecc_d2 ddr1_ecc_d2 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

W23 ddr1_ecc_d3 ddr1_ecc_d3 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

Y25 ddr1_ecc_d4 ddr1_ecc_d4 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

V24 ddr1_ecc_d5 ddr1_ecc_d5 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

V25 ddr1_ecc_d6 ddr1_ecc_d6 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

Y26 ddr1_ecc_d7 ddr1_ecc_d7 No 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AH24 ddr1_nck ddr1_nck 0 O PD drive clk

AE20 ddr1_odt0 ddr1_odt0 0 O PD drive 0

AF20 ddr1_rasn ddr1_rasn 0 O PD drive 1

AG21 ddr1_rst ddr1_rst 0 O PD drive 0

Y18 ddr1_vref0 ddr1_vref0 0 PWR OFF OFF 1.35/1.5/1.8 vdds_ddr1 No LVCMOS

AH21 ddr1_wen ddr1_wen 0 O PD drive 1

R25 ddr2_a0 ddr2_a0 0 O PD drive 1

R26 ddr2_a1 ddr2_a1 0 O PD drive 1

N23 ddr2_a10 ddr2_a10 0 O PD drive1

P26 ddr2_a11 ddr2_a11 0 O PD drive 1

N28 ddr2_a12 ddr2_a12 0 O PD drive1

T22 ddr2_a13 ddr2_a13 0 O PD drive 1

R22 ddr2_a14 ddr2_a14 0 O PD drive1

U22 ddr2_a15 ddr2_a15 0 O PD drive1

R28 ddr2_a2 ddr2_a2 0 O PD drive 1

R27 ddr2_a3 ddr2_a3 0 O PD drive 1

P23 ddr2_a4 ddr2_a4 0 O PD drive 1

P22 ddr2_a5 ddr2_a5 0 O PD drive 1

P25 ddr2_a6 ddr2_a6 0 O PD drive 1

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

(OFF)

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.35/1.5/1.8 vdds_ddr1 No LVCMOS

1.35/1.5/1.8 vdds_ddr2 No LVCMOS

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

18

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DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

N20 ddr2_a7 ddr2_a7 0 O PD drive 1

P27 ddr2_a8 ddr2_a8 0 O PD drive 1

N27 ddr2_a9 ddr2_a9 0 O PD drive 1

U23 ddr2_ba0 ddr2_ba0 0 O PD drive1

U27 ddr2_ba1 ddr2_ba1 0 O PD drive1

U26 ddr2_ba2 ddr2_ba2 0 O PD drive1

U28 ddr2_casn ddr2_casn 0 O PD drive 1

T28 ddr2_ck ddr2_ck 0 O PD drive clk

U24 ddr2_cke ddr2_cke 0 O PD drive 0

P24 ddr2_csn0 ddr2_csn0 0 O PD drive 1

E26 ddr2_d0 ddr2_d0 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

G25 ddr2_d1 ddr2_d1 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

H24 ddr2_d10 ddr2_d10 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

H26 ddr2_d11 ddr2_d11 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

G26 ddr2_d12 ddr2_d12 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

J25 ddr2_d13 ddr2_d13 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

J26 ddr2_d14 ddr2_d14 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

J24 ddr2_d15 ddr2_d15 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

L22 ddr2_d16 ddr2_d16 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

K20 ddr2_d17 ddr2_d17 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

K21 ddr2_d18 ddr2_d18 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

L23 ddr2_d19 ddr2_d19 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

F25 ddr2_d2 ddr2_d2 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

(OFF)

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.35/1.5/1.8 vdds_ddr2 No LVCMOS

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

L24 ddr2_d20 ddr2_d20 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

J23 ddr2_d21 ddr2_d21 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

K22 ddr2_d22 ddr2_d22 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

J20 ddr2_d23 ddr2_d23 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

L27 ddr2_d24 ddr2_d24 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

L26 ddr2_d25 ddr2_d25 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

L25 ddr2_d26 ddr2_d26 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

L28 ddr2_d27 ddr2_d27 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

M23 ddr2_d28 ddr2_d28 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

M24 ddr2_d29 ddr2_d29 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

F24 ddr2_d3 ddr2_d3 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

M25 ddr2_d30 ddr2_d30 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

M26 ddr2_d31 ddr2_d31 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

F26 ddr2_d4 ddr2_d4 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

F27 ddr2_d5 ddr2_d5 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

E27 ddr2_d6 ddr2_d6 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

E28 ddr2_d7 ddr2_d7 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

H23 ddr2_d8 ddr2_d8 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

H25 ddr2_d9 ddr2_d9 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

F28 ddr2_dqm0 ddr2_dqm0 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

G24 ddr2_dqm1 ddr2_dqm1 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

K23 ddr2_dqm2 ddr2_dqm2 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

M22 ddr2_dqm3 ddr2_dqm3 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

PULL UP/DOWN TYPE [14]

Pux/PDy

DSIS [15]

20

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

G28 ddr2_dqs0 ddr2_dqs0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS

H27 ddr2_dqs1 ddr2_dqs1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS

K27 ddr2_dqs2 ddr2_dqs2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS

M28 ddr2_dqs3 ddr2_dqs3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr2 LVCMOS

G27 ddr2_dqsn0 ddr2_dqsn0 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS

H28 ddr2_dqsn1 ddr2_dqsn1 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS

K28 ddr2_dqsn2 ddr2_dqsn2 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS

M27 ddr2_dqsn3 ddr2_dqsn3 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 LVCMOS

T27 ddr2_nck ddr2_nck 0 O PD drive clk

R23 ddr2_odt0 ddr2_odt0 0 O PD drive 0

T23 ddr2_rasn ddr2_rasn 0 O PD drive 1

R24 ddr2_rst ddr2_rst 0 O PD drive 0

N22 ddr2_vref0 ddr2_vref0 0 PWR OFF OFF 1.35/1.5/1.8 vdds_ddr2 No LVCMOS

U25 ddr2_wen ddr2_wen 0 O PD drive 1

G21 emu0 emu0 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual

gpio8_30 14 IO

D24 emu1 emu1 0 IO PU PU 0 1.8/3.3 vddshv3 Yes Dual

gpio8_31 14 IO

AC5 gpio6_10 gpio6_10 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

mdio_mclk 1 O 1 i2c3_sda 2 IO 1 usb3_ulpi_d7 3 IO 0 vin2b_hsync1 4 I vin5a_clk0 No 9 I 0 ehrpwm2A 10 O gpio6_10 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

(OFF)

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.35/1.5/1.8 vdds_ddr2 No LVCMOS

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

DDR

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

Pux/PDy

PU/PD

DSIS [15]

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SPRS950F –DECEMBER 2015–REVISED MAY 2019

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AB4 gpio6_11 gpio6_11 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

mdio_d 1 IO 1 i2c3_scl 2 IO 1 usb3_ulpi_d6 3 IO 0 vin2b_vsync1 4 I vin5a_de0 No 9 I 0 ehrpwm2B 10 O gpio6_11 14 IO Driver off 15 I

E21 gpio6_14 gpio6_14 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

mcasp1_axr8 1 IO 0 dcan2_tx 2 IO 1 uart10_rxd 3 I 1 vout2_hsync 6 O vin4a_hsync0 8 I 0 i2c3_sda 9 IO 1 timer1 10 IO gpio6_14 14 IO Driver off 15 I

F20 gpio6_15 gpio6_15 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

mcasp1_axr9 1 IO 0 dcan2_rx 2 IO 1 uart10_txd 3 O vout2_vsync 6 O vin4a_vsync0 8 I 0 i2c3_scl 9 IO 1 timer2 10 IO gpio6_15 14 IO Driver off 15 I

F21 gpio6_16 gpio6_16 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

mcasp1_axr10 1 IO 0 vout2_fld 6 O vin4a_fld0 8 I 0 clkout1 9 O timer3 10 IO gpio6_16 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

22

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DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

R6 gpmc_a0 gpmc_a0 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d16 2 I 0 vout3_d16 3 O vin4a_d0 4 I 0 vin4b_d0 6 I 0 i2c4_scl 7 IO 1 uart5_rxd 8 I 1 gpio7_3 14 IO Driver off 15 I

T9 gpmc_a1 gpmc_a1 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d17 2 I 0 vout3_d17 3 O vin4a_d1 4 I 0 vin4b_d1 6 I 0 i2c4_sda 7 IO 1 uart5_txd 8 O gpio7_4 14 IO Driver off 15 I

N9 gpmc_a10 gpmc_a10 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_de0 2 I 0 vout3_de 3 O vin4b_clk1 6 I 0 timer10 7 IO spi4_d0 8 IO 0 gpio2_0 14 IO Driver off 15 I

P9 gpmc_a11 gpmc_a11 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_fld0 2 I 0 vout3_fld 3 O vin4a_fld0 4 I 0 vin4b_de1 6 I 0 timer9 7 IO spi4_cs0 8 IO 1 gpio2_1 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

P4 gpmc_a12 gpmc_a12 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin4a_clk0 4 I 0 gpmc_a0 5 O vin4b_fld1 6 I 0 timer8 7 IO spi4_cs1 8 IO 1 dma_evt1 9 I 0 gpio2_2 14 IO Driver off 15 I

R3 gpmc_a13 gpmc_a13 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_rtclk 1 I 0 vin4a_hsync0 4 I 0 timer7 7 IO spi4_cs2 8 IO 1 dma_evt2 9 I 0 gpio2_3 14 IO Driver off 15 I

T2 gpmc_a14 gpmc_a14 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_d3 1 I 0 vin4a_vsync0 4 I 0 timer6 7 IO spi4_cs3 8 IO 1 gpio2_4 14 IO Driver off 15 I

U2 gpmc_a15 gpmc_a15 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_d2 1 I 0 vin4a_d8 4 I 0 timer5 7 IO gpio2_5 14 IO Driver off 15 I

U1 gpmc_a16 gpmc_a16 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_d0 1 IO 0 vin4a_d9 4 I 0 gpio2_6 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

24

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SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

P3 gpmc_a17 gpmc_a17 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_d1 1 I 0 vin4a_d10 4 I 0 gpio2_7 14 IO Driver off 15 I

R2 gpmc_a18 gpmc_a18 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

qspi1_sclk 1 O vin4a_d11 4 I 0 gpio2_8 14 IO Driver off 15 I

(10)

K7

T6 gpmc_a2 gpmc_a2 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

(10)

M7

gpmc_a19 gpmc_a19 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat4 1 IO 1 gpmc_a13 2 O vin4a_d12 4 I 0 vin3b_d0 6 I 0 gpio2_9 14 IO Driver off 15 I

vin3a_d18 2 I 0 vout3_d18 3 O vin4a_d2 4 I 0 vin4b_d2 6 I 0 uart7_rxd 7 I 1 uart5_ctsn 8 I 1 gpio7_5 14 IO Driver off 15 I

gpmc_a20 gpmc_a20 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat5 1 IO 1 gpmc_a14 2 O vin4a_d13 4 I 0 vin3b_d1 6 I 0 gpio2_10 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

(10)

J5

(10)

K6

J7 gpmc_a23 gpmc_a23 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

(10)

J4

(10)

J6

gpmc_a21 gpmc_a21 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat6 1 IO 1 gpmc_a15 2 O vin4a_d14 4 I 0 vin3b_d2 6 I 0 gpio2_11 14 IO Driver off 15 I

gpmc_a22 gpmc_a22 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat7 1 IO 1 gpmc_a16 2 O vin4a_d15 4 I 0 vin3b_d3 6 I 0 gpio2_12 14 IO Driver off 15 I

mmc2_clk 1 IO 1 gpmc_a17 2 O vin4a_fld0 4 I 0 vin3b_d4 6 I 0 gpio2_13 14 IO Driver off 15 I

gpmc_a24 gpmc_a24 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat0 1 IO 1 gpmc_a18 2 O vin3b_d5 6 I 0 gpio2_14 14 IO Driver off 15 I

gpmc_a25 gpmc_a25 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat1 1 IO 1 gpmc_a19 2 O vin3b_d6 6 I 0 gpio2_15 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

26

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SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

(10)

H4

(10)

H5

T7 gpmc_a3 gpmc_a3 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

P6 gpmc_a4 gpmc_a4 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

gpmc_a26 gpmc_a26 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat2 1 IO 1 gpmc_a20 2 O vin3b_d7 6 I 0 gpio2_16 14 IO Driver off 15 I

gpmc_a27 gpmc_a27 0 O PD PD 15 1.8/3.3 vddshv11 Yes Dual

mmc2_dat3 1 IO 1 gpmc_a21 2 O vin3b_hsync1 6 I 0 gpio2_17 14 IO Driver off 15 I

qspi1_cs2 1 O 1 vin3a_d19 2 I 0 vout3_d19 3 O vin4a_d3 4 I 0 vin4b_d3 6 I 0 uart7_txd 7 O uart5_rtsn 8 O gpio7_6 14 IO Driver off 15 I

qspi1_cs3 1 O 1 vin3a_d20 2 I 0 vout3_d20 3 O vin4a_d4 4 I 0 vin4b_d4 6 I 0 i2c5_scl 7 IO 1 uart6_rxd 8 I 1 gpio1_26 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

Submit Documentation Feedback

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

R9 gpmc_a5 gpmc_a5 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d21 2 I 0 vout3_d21 3 O vin4a_d5 4 I 0 vin4b_d5 6 I 0 i2c5_sda 7 IO 1 uart6_txd 8 O gpio1_27 14 IO Driver off 15 I

R5 gpmc_a6 gpmc_a6 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d22 2 I 0 vout3_d22 3 O vin4a_d6 4 I 0 vin4b_d6 6 I 0 uart8_rxd 7 I 1 uart6_ctsn 8 I 1 gpio1_28 14 IO Driver off 15 I

P5 gpmc_a7 gpmc_a7 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d23 2 I 0 vout3_d23 3 O vin4a_d7 4 I 0 vin4b_d7 6 I 0 uart8_txd 7 O uart6_rtsn 8 O gpio1_29 14 IO Driver off 15 I

N7 gpmc_a8 gpmc_a8 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_hsync0 2 I 0 vout3_hsync 3 O vin4b_hsync1 6 I 0 timer12 7 IO spi4_sclk 8 IO 0 gpio1_30 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

28

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DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

R4 gpmc_a9 gpmc_a9 0 O PD PD 15 1.8/3.3 vddshv10 Yes Dual

vin3a_vsync0 2 I 0 vout3_vsync 3 O vin4b_vsync1 6 I 0 timer11 7 IO spi4_d1 8 IO 0 gpio1_31 14 IO Driver off 15 I

M6 gpmc_ad0 gpmc_ad0 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d0 2 I 0 vout3_d0 3 O gpio1_6 14 IO sysboot0 15 I

M2 gpmc_ad1 gpmc_ad1 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d1 2 I 0 vout3_d1 3 O gpio1_7 14 IO sysboot1 15 I

J1 gpmc_ad10 gpmc_ad10 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d10 2 I 0 vout3_d10 3 O gpio7_28 14 IO sysboot10 15 I

J2 gpmc_ad11 gpmc_ad11 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d11 2 I 0 vout3_d11 3 O gpio7_29 14 IO sysboot11 15 I

H1 gpmc_ad12 gpmc_ad12 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d12 2 I 0 vout3_d12 3 O gpio1_18 14 IO sysboot12 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

PU/PD 0

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

J3 gpmc_ad13 gpmc_ad13 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d13 2 I 0 vout3_d13 3 O gpio1_19 14 IO sysboot13 15 I

H2 gpmc_ad14 gpmc_ad14 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d14 2 I 0 vout3_d14 3 O gpio1_20 14 IO sysboot14 15 I

H3 gpmc_ad15 gpmc_ad15 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d15 2 I 0 vout3_d15 3 O gpio1_21 14 IO sysboot15 15 I

L5 gpmc_ad2 gpmc_ad2 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d2 2 I 0 vout3_d2 3 O gpio1_8 14 IO sysboot2 15 I

M1 gpmc_ad3 gpmc_ad3 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d3 2 I 0 vout3_d3 3 O gpio1_9 14 IO sysboot3 15 I

L6 gpmc_ad4 gpmc_ad4 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d4 2 I 0 vout3_d4 3 O gpio1_10 14 IO sysboot4 15 I

L4 gpmc_ad5 gpmc_ad5 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d5 2 I 0 vout3_d5 3 O gpio1_11 14 IO sysboot5 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

30

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

L3 gpmc_ad6 gpmc_ad6 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d6 2 I 0 vout3_d6 3 O gpio1_12 14 IO sysboot6 15 I

L2 gpmc_ad7 gpmc_ad7 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d7 2 I 0 vout3_d7 3 O gpio1_13 14 IO sysboot7 15 I

L1 gpmc_ad8 gpmc_ad8 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d8 2 I 0 vout3_d8 3 O gpio7_18 14 IO sysboot8 15 I

K2 gpmc_ad9 gpmc_ad9 0 IO OFF OFF 15 1.8/3.3 vddshv10 Yes Dual

vin3a_d9 2 I 0 vout3_d9 3 O gpio7_19 14 IO sysboot9 15 I

N1 gpmc_advn_ale gpmc_advn_ale 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual

gpmc_cs6 1 O clkout2 2 O gpmc_wait1 3 I 1 vin4a_vsync0 4 I 0 gpmc_a2 5 O gpmc_a23 6 O timer3 7 IO i2c3_sda 8 IO 1 dma_evt2 9 I 0 gpio2_23 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

PU/PD

DSIS [15]

Submit Documentation Feedback

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

N6 gpmc_ben0 gpmc_ben0 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual

gpmc_cs4 1 O vin1b_hsync1 No 3 I 0 vin3b_de1 6 I 0 timer2 7 IO dma_evt3 9 I 0 gpio2_26 14 IO Driver off 15 I

M4 gpmc_ben1 gpmc_ben1 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual

gpmc_cs5 1 O vin1b_de1 No 3 I 0 vin3b_clk1 4 I 0 gpmc_a3 5 O vin3b_fld1 6 I 0 timer1 7 IO dma_evt4 9 I 0 gpio2_27 14 IO Driver off 15 I

P7 gpmc_clk gpmc_clk 0 IO PU PU 15 1.8/3.3 vddshv10 Yes Dual

gpmc_cs7 1 O clkout1 2 O gpmc_wait1 3 I 1 vin4a_hsync0 4 I 0 vin4a_de0 5 I 0 vin3b_clk1 6 I 0 timer4 7 IO i2c3_scl 8 IO 1 dma_evt1 9 I 0 gpio2_22 14 IO Driver off 15 I

T1 gpmc_cs0 gpmc_cs0 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual

gpio2_19 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

PU/PD 0

PU/PD

DSIS [15]

32

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

H6 gpmc_cs1 gpmc_cs1 0 O PU PU 15 1.8/3.3 vddshv11 Yes Dual

mmc2_cmd 1 IO 1 gpmc_a22 2 O vin4a_de0 4 I 0 vin3b_vsync1 6 I 0 gpio2_18 14 IO Driver off 15 I

P2 gpmc_cs2 gpmc_cs2 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual

qspi1_cs0 1 O 1 gpio2_20 14 IO Driver off 15 I

P1 gpmc_cs3 gpmc_cs3 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual

qspi1_cs1 1 O 1 vin3a_clk0 2 I 0 vout3_clk 3 O gpmc_a1 5 O gpio2_21 14 IO Driver off 15 I

M5 gpmc_oen_ren gpmc_oen_ren 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual

gpio2_24 14 IO Driver off 15 I

N2 gpmc_wait0 gpmc_wait0 0 I PU PU 15 1.8/3.3 vddshv10 Yes Dual

gpio2_28 14 IO Driver off 15 I

M3 gpmc_wen gpmc_wen 0 O PU PU 15 1.8/3.3 vddshv10 Yes Dual

gpio2_25 14 IO

Driver off 15 I

AG16 hdmi1_clockx hdmi1_clockx 0 O 1.8 vdda_hdmi HDMIPHY PDy AH16 hdmi1_clocky hdmi1_clocky 0 O 1.8 vdda_hdmi HDMIPHY PDy AG17 hdmi1_data0x hdmi1_data0x 0 O 1.8 vdda_hdmi HDMIPHY PDy AH17 hdmi1_data0y hdmi1_data0y 0 O 1.8 vdda_hdmi HDMIPHY PDy AG18 hdmi1_data1x hdmi1_data1x 0 O 1.8 vdda_hdmi HDMIPHY PDy AH18 hdmi1_data1y hdmi1_data1y 0 O 1.8 vdda_hdmi HDMIPHY PDy AG19 hdmi1_data2x hdmi1_data2x 0 O 1.8 vdda_hdmi HDMIPHY PDy AH19 hdmi1_data2y hdmi1_data2y 0 O 1.8 vdda_hdmi HDMIPHY PDy

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

UP/DOWN TYPE [14]

PU/PD

PU/PD 1

PU/PD

PULL

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

C20 i2c1_scl i2c1_scl 0 IO OFF OFF 1.8/3.3 vddshv3 Yes Dual

C21 i2c1_sda i2c1_sda 0 IO OFF OFF 1.8/3.3 vddshv3 Yes Dual

F17 i2c2_scl i2c2_scl 0 IO OFF OFF 15 1.8/3.3 vddshv3 Yes Dual

hdmi1_ddc_sda 1 IO

Driver off 15 I

C25 i2c2_sda i2c2_sda 0 IO OFF OFF 15 1.8/3.3 vddshv3 Yes Dual

hdmi1_ddc_scl 1 IO

Driver off 15 I

AH15 ljcb_clkn ljcb_clkn 0 IO 1.8 vdda_pcie LJCB AG15 ljcb_clkp ljcb_clkp 0 IO 1.8 vdda_pcie LJCB B14 mcasp1_aclkr mcasp1_aclkr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp7_axr2 1 IO 0

vout2_d0 6 O

vin4a_d0 8 I 0

i2c4_sda 10 IO 1

gpio5_0 14 IO

Driver off 15 I

C14 mcasp1_aclkx mcasp1_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

vin6a_fld0 No 7 I 0

i2c3_sda 10 IO 1

gpio7_31 14 IO

Driver off 15 I

G12 mcasp1_axr0 mcasp1_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

uart6_rxd 3 I 1

vin6a_vsync0 No 7 I 0

i2c5_sda 10 IO 1

gpio5_2 14 IO

Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS I2C

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

PU/PD 1

PU/PD 0

DSIS [15]

34

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

F12 mcasp1_axr1 mcasp1_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

uart6_txd 3 O vin6a_hsync0 No 7 I 0 i2c5_scl 10 IO 1 gpio5_3 14 IO Driver off 15 I

B13 mcasp1_axr10 mcasp1_axr10 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp6_aclkx 1 IO 0 mcasp6_aclkr 2 IO spi3_d0 3 IO 0 vin6a_d13 No 7 I 0 timer7 10 IO gpio5_12 14 IO Driver off 15 I

A12 mcasp1_axr11 mcasp1_axr11 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp6_fsx 1 IO 0 mcasp6_fsr 2 IO spi3_cs0 3 IO 1 vin6a_d12 No 7 I 0 timer8 10 IO gpio4_17 14 IO Driver off 15 I

E14 mcasp1_axr12 mcasp1_axr12 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp7_axr0 1 IO 0 spi3_cs1 3 IO 1 vin6a_d11 No 7 I 0 timer9 10 IO gpio4_18 14 IO Driver off 15 I

A13 mcasp1_axr13 mcasp1_axr13 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp7_axr1 1 IO 0 vin6a_d10 No 7 I 0 timer10 10 IO gpio6_4 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

Submit Documentation Feedback

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

G14 mcasp1_axr14 mcasp1_axr14 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp7_aclkx 1 IO 0 mcasp7_aclkr 2 IO vin6a_d9 No 7 I 0 timer11 10 IO gpio6_5 14 IO Driver off 15 I

F14 mcasp1_axr15 mcasp1_axr15 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp7_fsx 1 IO 0 mcasp7_fsr 2 IO vin6a_d8 No 7 I 0 timer12 10 IO gpio6_6 14 IO Driver off 15 I

G13 mcasp1_axr2 mcasp1_axr2 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp6_axr2 1 IO 0 uart6_ctsn 3 I 1 vout2_d2 6 O vin4a_d2 8 I 0 gpio5_4 14 IO Driver off 15 I

J11 mcasp1_axr3 mcasp1_axr3 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp6_axr3 1 IO 0 uart6_rtsn 3 O vout2_d3 6 O vin4a_d3 8 I 0 gpio5_5 14 IO Driver off 15 I

E12 mcasp1_axr4 mcasp1_axr4 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp4_axr2 1 IO 0 vout2_d4 6 O vin4a_d4 8 I 0 gpio5_6 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

36

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

F13 mcasp1_axr5 mcasp1_axr5 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp4_axr3 1 IO 0 vout2_d5 6 O vin4a_d5 8 I 0 gpio5_7 14 IO Driver off 15 I

C12 mcasp1_axr6 mcasp1_axr6 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp5_axr2 1 IO 0 vout2_d6 6 O vin4a_d6 8 I 0 gpio5_8 14 IO Driver off 15 I

D12 mcasp1_axr7 mcasp1_axr7 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp5_axr3 1 IO 0 vout2_d7 6 O vin4a_d7 8 I 0 timer4 10 IO gpio5_9 14 IO Driver off 15 I

B12 mcasp1_axr8 mcasp1_axr8 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp6_axr0 1 IO 0 spi3_sclk 3 IO 0 vin6a_d15 No 7 I 0 timer5 10 IO gpio5_10 14 IO Driver off 15 I

A11 mcasp1_axr9 mcasp1_axr9 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp6_axr1 1 IO 0 spi3_d1 3 IO 0 vin6a_d14 No 7 I 0 timer6 10 IO gpio5_11 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

Submit Documentation Feedback

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37

DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

J14 mcasp1_fsr mcasp1_fsr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp7_axr3 1 IO 0 vout2_d1 6 O vin4a_d1 8 I 0 i2c4_scl 10 IO 1 gpio5_1 14 IO Driver off 15 I

D14 mcasp1_fsx mcasp1_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

vin6a_de0 No 7 I 0 i2c3_scl 10 IO 1 gpio7_30 14 IO Driver off 15 I

E15 mcasp2_aclkr mcasp2_aclkr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp8_axr2 1 IO 0 vout2_d8 6 O vin4a_d8 8 I 0 Driver off 15 I

A19 mcasp2_aclkx mcasp2_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

vin6a_d7 No 7 I 0 Driver off 15 I

B15 mcasp2_axr0 mcasp2_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

vout2_d10 6 O vin4a_d10 8 I 0 Driver off 15 I

A15 mcasp2_axr1 mcasp2_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

vout2_d11 6 O vin4a_d11 8 I 0 Driver off 15 I

C15 mcasp2_axr2 mcasp2_axr2 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp3_axr2 1 IO 0 vin6a_d5 No 7 I 0 gpio6_8 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

38

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

A16 mcasp2_axr3 mcasp2_axr3 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp3_axr3 1 IO 0 vin6a_d4 No 7 I 0 gpio6_9 14 IO Driver off 15 I

D15 mcasp2_axr4 mcasp2_axr4 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp8_axr0 1 IO 0 vout2_d12 6 O vin4a_d12 8 I 0 gpio1_4 14 IO Driver off 15 I

B16 mcasp2_axr5 mcasp2_axr5 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp8_axr1 1 IO 0 vout2_d13 6 O vin4a_d13 8 I 0 gpio6_7 14 IO Driver off 15 I

B17 mcasp2_axr6 mcasp2_axr6 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp8_aclkx 1 IO 0 mcasp8_aclkr 2 IO vout2_d14 6 O vin4a_d14 8 I 0 gpio2_29 14 IO Driver off 15 I

A17 mcasp2_axr7 mcasp2_axr7 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp8_fsx 1 IO 0 mcasp8_fsr 2 IO vout2_d15 6 O vin4a_d15 8 I 0 gpio1_5 14 IO Driver off 15 I

A20 mcasp2_fsr mcasp2_fsr 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp8_axr3 1 IO 0 vout2_d9 6 O vin4a_d9 8 I 0 Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

Submit Documentation Feedback

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

A18 mcasp2_fsx mcasp2_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

vin6a_d6 No 7 I 0 Driver off 15 I

B18 mcasp3_aclkx mcasp3_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp3_aclkr 1 IO mcasp2_axr12 2 IO 0 uart7_rxd 3 I 1 vin6a_d3 No 7 I 0 gpio5_13 14 IO Driver off 15 I

B19 mcasp3_axr0 mcasp3_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp2_axr14 2 IO 0 uart7_ctsn 3 I 1 uart5_rxd 4 I 1 vin6a_d1 No 7 I 0 Driver off 15 I

C17 mcasp3_axr1 mcasp3_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp2_axr15 2 IO 0 uart7_rtsn 3 O uart5_txd 4 O vin6a_d0 No 7 I 0 vin5a_fld0 No 9 I 0 Driver off 15 I

F15 mcasp3_fsx mcasp3_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp3_fsr 1 IO mcasp2_axr13 2 IO 0 uart7_txd 3 O vin6a_d2 No 7 I 0 gpio5_14 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

40

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

C18 mcasp4_aclkx mcasp4_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp4_aclkr 1 IO spi3_sclk 2 IO 0 uart8_rxd 3 I 1 i2c4_sda 4 IO 1 vout2_d16 6 O vin4a_d16 8 I 0 vin5a_d15 No 9 I 0 Driver off 15 I

G16 mcasp4_axr0 mcasp4_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

spi3_d0 2 IO 0 uart8_ctsn 3 I 1 uart4_rxd 4 I 1 vout2_d18 6 O vin4a_d18 8 I 0 vin5a_d13 No 9 I 0 Driver off 15 I

D17 mcasp4_axr1 mcasp4_axr1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

spi3_cs0 2 IO 1 uart8_rtsn 3 O uart4_txd 4 O vout2_d19 6 O vin4a_d19 8 I 0 vin5a_d12 No 9 I 0 Driver off 15 I

A21 mcasp4_fsx mcasp4_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp4_fsr 1 IO spi3_d1 2 IO 0 uart8_txd 3 O i2c4_scl 4 IO 1 vout2_d17 6 O vin4a_d17 8 I 0 vin5a_d14 No 9 I 0 Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

Submit Documentation Feedback

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AA3 mcasp5_aclkx mcasp5_aclkx 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual

mcasp5_aclkr 1 IO spi4_sclk 2 IO 0 uart9_rxd 3 I 1 i2c5_sda 4 IO 1 mlb_clk 5 I 1 vout2_d20 6 O vin4a_d20 8 I 0 vin5a_d11 No 9 I 0 Driver off 15 I

AB3 mcasp5_axr0 mcasp5_axr0 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual

spi4_d0 2 IO 0 uart9_ctsn 3 I 1 uart3_rxd 4 I 1 mlb_sig 5 IO 1 vout2_d22 6 O vin4a_d22 8 I 0 vin5a_d9 No 9 I 0 Driver off 15 I

AA4 mcasp5_axr1 mcasp5_axr1 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual

spi4_cs0 2 IO 1 uart9_rtsn 3 O uart3_txd 4 O mlb_dat 5 IO 1 vout2_d23 6 O vin4a_d23 8 I 0 vin5a_d8 No 9 I 0 Driver off 15 I

AB9 mcasp5_fsx mcasp5_fsx 0 IO PD PD 15 1.8/3.3 vddshv7 Yes Dual

mcasp5_fsr 1 IO spi4_d1 2 IO 0 uart9_txd 3 O i2c5_scl 4 IO 1 vout2_d21 6 O vin4a_d21 8 I 0 vin5a_d10 No 9 I 0 Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

42

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

U4 mdio_d mdio_d 0 IO PU PU 15 1.8/3.3 vddshv9 Yes Dual

uart3_ctsn 1 I 1 mii0_txer 3 O 0 vin2a_d0 4 I 0 vin4b_d0 5 I 0 gpio5_16 14 IO Driver off 15 I

V1 mdio_mclk mdio_mclk 0 O PU PU 15 1.8/3.3 vddshv9 Yes Dual

uart3_rtsn 1 O mii0_col 3 I 0 vin2a_clk0 4 I vin4b_clk1 5 I 0 gpio5_15 14 IO

Driver off 15 I

AB2 mlbp_clk_n mlbp_clk_n 0 I 1.8 vdds_mlbp No ILVDS18 AB1 mlbp_clk_p mlbp_clk_p 0 I 1.8 vdds_mlbp No ILVDS18 AA2 mlbp_dat_n mlbp_dat_n 0 IO OFF OFF 1.8 vdds_mlbp No BMLB18 AA1 mlbp_dat_p mlbp_dat_p 0 IO OFF OFF 1.8 vdds_mlbp No BMLB18 AC2 mlbp_sig_n mlbp_sig_n 0 IO OFF OFF 1.8 vdds_mlbp No BMLB18 AC1 mlbp_sig_p mlbp_sig_p 0 IO OFF OFF 1.8 vdds_mlbp No BMLB18 W6 mmc1_clk mmc1_clk 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1

gpio6_21 14 IO

Driver off 15 I

Y6 mmc1_cmd mmc1_cmd 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1

gpio6_22 14 IO

Driver off 15 I

AA6 mmc1_dat0 mmc1_dat0 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1

gpio6_23 14 IO

Driver off 15 I

Y4 mmc1_dat1 mmc1_dat1 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1

gpio6_24 14 IO

Driver off 15 I

AA5 mmc1_dat2 mmc1_dat2 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1

gpio6_25 14 IO

Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 1

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

Y3 mmc1_dat3 mmc1_dat3 0 IO PU PU 15 1.8/3.3 vddshv8 Yes SDIO1833 PU/PD 1

gpio6_26 14 IO Driver off 15 I

W7 mmc1_sdcd mmc1_sdcd 0 I PU PU 15 1.8/3.3 vddshv8 Yes Dual

uart6_rxd 3 I 1 i2c4_sda 4 IO 1 gpio6_27 14 IO Driver off 15 I

Y9 mmc1_sdwp mmc1_sdwp 0 I PD PD 15 1.8/3.3 vddshv8 Yes Dual

uart6_txd 3 O i2c4_scl 4 IO 1 gpio6_28 14 IO Driver off 15 I

AD4 mmc3_clk mmc3_clk 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

usb3_ulpi_d5 3 IO 0 vin2b_d7 4 I 0 vin5a_d7 No 9 I 0 ehrpwm2_tripzone_input 10 IO 0 gpio6_29 14 IO Driver off 15 I

AC4 mmc3_cmd mmc3_cmd 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

spi3_sclk 1 IO 0 usb3_ulpi_d4 3 IO 0 vin2b_d6 4 I 0 vin5a_d6 No 9 I 0 eCAP2_in_PWM2_out 10 IO 0 gpio6_30 14 IO Driver off 15 I

AC7 mmc3_dat0 mmc3_dat0 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

spi3_d1 1 IO 0 uart5_rxd 2 I 1 usb3_ulpi_d3 3 IO 0 vin2b_d5 4 I 0 vin5a_d5 No 9 I 0 eQEP3A_in 10 I 0 gpio6_31 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 1

PU/PD 0

PU/PD 1

DSIS [15]

44

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AC6 mmc3_dat1 mmc3_dat1 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

spi3_d0 1 IO 0 uart5_txd 2 O usb3_ulpi_d2 3 IO 0 vin2b_d4 4 I 0 vin5a_d4 No 9 I 0 eQEP3B_in 10 I 0 gpio7_0 14 IO Driver off 15 I

AC9 mmc3_dat2 mmc3_dat2 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

spi3_cs0 1 IO 1 uart5_ctsn 2 I 1 usb3_ulpi_d1 3 IO 0 vin2b_d3 4 I 0 vin5a_d3 No 9 I 0 eQEP3_index 10 IO 0 gpio7_1 14 IO Driver off 15 I

AC3 mmc3_dat3 mmc3_dat3 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

spi3_cs1 1 IO 1 uart5_rtsn 2 O usb3_ulpi_d0 3 IO 0 vin2b_d2 4 I 0 vin5a_d2 No 9 I 0 eQEP3_strobe 10 IO 0 gpio7_2 14 IO Driver off 15 I

AC8 mmc3_dat4 mmc3_dat4 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

spi4_sclk 1 IO 0 uart10_rxd 2 I 1 usb3_ulpi_nxt 3 I 0 vin2b_d1 4 I 0 vin5a_d1 No 9 I 0 ehrpwm3A 10 O gpio1_22 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 1

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AD6 mmc3_dat5 mmc3_dat5 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

spi4_d1 1 IO 0 uart10_txd 2 O usb3_ulpi_dir 3 I 0 vin2b_d0 4 I 0 vin5a_d0 No 9 I 0 ehrpwm3B 10 O gpio1_23 14 IO Driver off 15 I

AB8 mmc3_dat6 mmc3_dat6 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

spi4_d0 1 IO 0 uart10_ctsn 2 I 1 usb3_ulpi_stp 3 O vin2b_de1 4 I vin5a_hsync0 No 9 I 0 ehrpwm3_tripzone_input 10 IO 0 gpio1_24 14 IO Driver off 15 I

AB5 mmc3_dat7 mmc3_dat7 0 IO PU PU 15 1.8/3.3 vddshv7 Yes Dual

spi4_cs0 1 IO 1 uart10_rtsn 2 O usb3_ulpi_clk 3 I 0 vin2b_clk1 4 I vin5a_vsync0 No 9 I 0 eCAP3_in_PWM3_out 10 IO 0 gpio1_25 14 IO Driver off 15 I

D21 nmin_dsp nmin_dsp 0 I PD PD 1.8/3.3 vddshv3 Yes Dual

Y11 on_off on_off 0 O PU drive 1

AG13 pcie_rxn0 pcie_rxn0 0 I OFF OFF 1.8 vdda_pcie0 SERDES AG11 pcie_rxn1 pcie_rxn1 No 0 I OFF OFF 1.8 vdda_pcie1 SERDES AH13 pcie_rxp0 pcie_rxp0 0 I OFF OFF 1.8 vdda_pcie0 SERDES AH11 pcie_rxp1 pcie_rxp1 No 0 I OFF OFF 1.8 vdda_pcie1 SERDES AG14 pcie_txn0 pcie_txn0 0 O 1.8 vdda_pcie0 SERDES AG12 pcie_txn1 pcie_txn1 No 0 O 1.8 vdda_pcie1 SERDES

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

(OFF)

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

1.8/3.3 vddshv5 Yes BC1833IHHVPU/PD

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 1

PU/PD

DSIS [15]

46

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AH14 pcie_txp0 pcie_txp0 0 O 1.8 vdda_pcie0 SERDES AH12 pcie_txp1 pcie_txp1 No 0 O 1.8 vdda_pcie1 SERDES F22 porz porz 0 I 1.8/3.3 vddshv3 Yes IHHV1833 PU/PD E23 resetn resetn 0 I PU PU 1.8/3.3 vddshv3 Yes Dual

U5 rgmii0_rxc rgmii0_rxc 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii1_txen 2 O mii0_txclk 3 I 0 vin2a_d5 4 I 0 vin4b_d5 5 I 0 usb4_ulpi_d2 6 IO 0 gpio5_26 14 IO Driver off 15 I

V5 rgmii0_rxctl rgmii0_rxctl 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii1_txd1 2 O mii0_txd3 3 O vin2a_d6 4 I 0 vin4b_d6 5 I 0 usb4_ulpi_d3 6 IO 0 gpio5_27 14 IO Driver off 15 I

W2 rgmii0_rxd0 rgmii0_rxd0 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii0_txd0 1 O mii0_txd0 3 O vin2a_fld0 4 I vin4b_fld1 5 I 0 usb4_ulpi_d7 6 IO 0 gpio5_31 14 IO Driver off 15 I

Y2 rgmii0_rxd1 rgmii0_rxd1 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii0_txd1 1 O mii0_txd1 3 O vin2a_d9 4 I 0 usb4_ulpi_d6 6 IO 0 gpio5_30 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

PU/PD 0

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

V3 rgmii0_rxd2 rgmii0_rxd2 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii0_txen 1 O mii0_txen 3 O vin2a_d8 4 I 0 usb4_ulpi_d5 6 IO 0 gpio5_29 14 IO Driver off 15 I

V4 rgmii0_rxd3 rgmii0_rxd3 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii1_txd0 2 O mii0_txd2 3 O vin2a_d7 4 I 0 vin4b_d7 5 I 0 usb4_ulpi_d4 6 IO 0 gpio5_28 14 IO Driver off 15 I

W9 rgmii0_txc rgmii0_txc 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual

uart3_ctsn 1 I 1 rmii1_rxd1 2 I 0 mii0_rxd3 3 I 0 vin2a_d3 4 I 0 vin4b_d3 5 I 0 usb4_ulpi_clk 6 I 0 spi3_d0 7 IO 0 spi4_cs2 8 IO 1 gpio5_20 14 IO Driver off 15 I

V9 rgmii0_txctl rgmii0_txctl 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual

uart3_rtsn 1 O rmii1_rxd0 2 I 0 mii0_rxd2 3 I 0 vin2a_d4 4 I 0 vin4b_d4 5 I 0 usb4_ulpi_stp 6 O spi3_cs0 7 IO 1 spi4_cs3 8 IO 1 gpio5_21 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

PU/PD

DSIS [15]

48

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

U6 rgmii0_txd0 rgmii0_txd0 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii0_rxd0 1 I 0 mii0_rxd0 3 I 0 vin2a_d10 4 I 0 usb4_ulpi_d1 6 IO 0 spi4_cs0 7 IO 1 uart4_rtsn 8 O gpio5_25 14 IO Driver off 15 I

V6 rgmii0_txd1 rgmii0_txd1 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii0_rxd1 1 I 0 mii0_rxd1 3 I 0 vin2a_vsync0 4 I vin4b_vsync1 5 I 0 usb4_ulpi_d0 6 IO 0 spi4_d0 7 IO 0 uart4_ctsn 8 IO 1 gpio5_24 14 IO Driver off 15 I

U7 rgmii0_txd2 rgmii0_txd2 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii0_rxer 1 I 0 mii0_rxer 3 I 0 vin2a_hsync0 4 I vin4b_hsync1 5 I 0 usb4_ulpi_nxt 6 I 0 spi4_d1 7 IO 0 uart4_txd 8 O gpio5_23 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

V7 rgmii0_txd3 rgmii0_txd3 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii0_crs 1 I 0 mii0_crs 3 I 0 vin2a_de0 4 I vin4b_de1 5 I 0 usb4_ulpi_dir 6 I 0 spi4_sclk 7 IO 0 uart4_rxd 8 I 1 gpio5_22 14 IO Driver off 15 I

U3 RMII_MHZ_50_CLK RMII_MHZ_50_CLK 0 IO PD PD 15 1.8/3.3 vddshv9 Yes Dual

vin2a_d11 4 I 0 gpio5_17 14 IO Driver off 15 I

F23 rstoutn rstoutn 0 O PD drive 1

E18 rtck rtck 0 O PU drive clk

gpio8_29 14 IO

AF14 rtc_iso rtc_iso 0 I 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD AE14 rtc_osc_xi_clkin32 rtc_osc_xi_clkin32 0 I 1.8 vdda_rtc No LVCMOS

AD14 rtc_osc_xo rtc_osc_xo 0 O 1.8 vdda_rtc No LVCMOS

AB17 rtc_porz rtc_porz 0 I 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD AH9 sata1_rxn0 sata1_rxn0 0 I OFF OFF 1.8 vdda_sata SATAPHY AG9 sata1_rxp0 sata1_rxp0 0 I OFF OFF 1.8 vdda_sata SATAPHY AG10 sata1_txn0 sata1_txn0 0 O 1.8 vdda_sata SATAPHY AH10 sata1_txp0 sata1_txp0 0 O 1.8 vdda_sata SATAPHY A24 spi1_cs0 spi1_cs0 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

gpio7_10 14 IO Driver off 15 I

A22 spi1_cs1 spi1_cs1 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

sata1_led 2 O spi2_cs1 3 IO 1 gpio7_11 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

(OFF)

BALL

RESET

REL.

MUXMODE

[9]

0 1.8/3.3 vddshv3 Yes Dual

I/O

VOLTAGE

VALUE [10]

1.8/3.3 vddshv3 Yes Dual

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

OSC

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

PU/PD 0

PU/PD

PU/PD 1

DSIS [15]

50

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

B21 spi1_cs2 spi1_cs2 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

uart4_rxd 1 I 1 mmc3_sdcd 2 I 1 spi2_cs2 3 IO 1 dcan2_tx 4 IO 1 mdio_mclk 5 O 1 hdmi1_hpd 6 I gpio7_12 14 IO Driver off 15 I

B20 spi1_cs3 spi1_cs3 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

uart4_txd 1 O mmc3_sdwp 2 I 0 spi2_cs3 3 IO 1 dcan2_rx 4 IO 1 mdio_d 5 IO 1 hdmi1_cec 6 IO gpio7_13 14 IO Driver off 15 I

B25 spi1_d0 spi1_d0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

gpio7_9 14 IO Driver off 15 I

F16 spi1_d1 spi1_d1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

gpio7_8 14 IO Driver off 15 I

A25 spi1_sclk spi1_sclk 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

gpio7_7 14 IO Driver off 15 I

B24 spi2_cs0 spi2_cs0 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual

uart3_rtsn 1 O uart5_txd 2 O gpio7_17 14 IO Driver off 15 I

G17 spi2_d0 spi2_d0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

uart3_ctsn 1 I 1 uart5_rxd 2 I 1 gpio7_16 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 1

PU/PD 0

PU/PD 1

PU/PD 0

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

B22 spi2_d1 spi2_d1 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

uart3_txd 1 O gpio7_15 14 IO Driver off 15 I

A26 spi2_sclk spi2_sclk 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual

uart3_rxd 1 I 1 gpio7_14 14 IO

Driver off 15 I

E20 tclk tclk 0 I PU PU 0 1.8/3.3 vddshv3 Yes IQ1833 PU/PD D23 tdi tdi 0 I PU PU 0 1.8/3.3 vddshv3 Yes Dual

gpio8_27 14 I

F19 tdo tdo 0 O PU PU 0 1.8/3.3 vddshv3 Yes Dual

gpio8_28 14 IO

F18 tms tms 0 IO OFF OFF 0 1.8/3.3 vddshv3 Yes Dual

D20 trstn trstn 0 I PD PD 1.8/3.3 vddshv3 Yes Dual

E25 uart1_ctsn uart1_ctsn 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual

uart9_rxd 2 I 1

mmc4_clk 3 IO 1

gpio7_24 14 IO

Driver off 15 I

C27 uart1_rtsn uart1_rtsn 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual

uart9_txd 2 O

mmc4_cmd 3 IO 1

gpio7_25 14 IO

Driver off 15 I

B27 uart1_rxd uart1_rxd 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual

mmc4_sdcd 3 I 1

gpio7_22 14 IO

Driver off 15 I

C26 uart1_txd uart1_txd 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual

mmc4_sdwp 3 I 0

gpio7_23 14 IO

Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

PU/PD

PU/PD 1

PU/PD

PU/PD 1

PU/PD

DSIS [15]

52

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

D27 uart2_ctsn uart2_ctsn 0 I PU PU 15 1.8/3.3 vddshv4 Yes Dual

uart3_rxd 2 I 1 mmc4_dat2 3 IO 1 uart10_rxd 4 I 1 uart1_dtrn 5 O gpio1_16 14 IO Driver off 15 I

C28 uart2_rtsn uart2_rtsn 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual

uart3_txd 1 O uart3_irtx 2 O mmc4_dat3 3 IO 1 uart10_txd 4 O uart1_rin 5 I 1 gpio1_17 14 IO Driver off 15 I

D28 uart2_rxd uart3_ctsn 1 I PU PU 15 1.8/3.3 vddshv4 Yes Dual

uart3_rctx 2 O mmc4_dat0 3 IO 1 uart2_rxd 4 I 1 uart1_dcdn 5 I 1 gpio7_26 14 IO Driver off 15 I

D26 uart2_txd uart2_txd 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual

uart3_rtsn 1 O uart3_sd 2 O mmc4_dat1 3 IO 1 uart2_txd 4 O uart1_dsrn 5 I 0 gpio7_27 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 1

PU/PD

PU/PD 1

PU/PD

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

V2 uart3_rxd uart3_rxd 0 I PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii1_crs 2 I 0 mii0_rxdv 3 I 0 vin2a_d1 4 I 0 vin4b_d1 5 I 0 spi3_sclk 7 IO 0 gpio5_18 14 IO Driver off 15 I

Y1 uart3_txd uart3_txd 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual

rmii1_rxer 2 I 0 mii0_rxclk 3 I 0 vin2a_d2 4 I 0 vin4b_d2 5 I 0 spi3_d1 7 IO 0 spi4_cs1 8 IO 1 gpio5_19 14 IO Driver off 15 I

AC12 usb1_dm usb1_dm 0 IO OFF OFF 3.3 vdda33v_us

AD12 usb1_dp usb1_dp 0 IO OFF OFF 3.3 vdda33v_us

AB10 usb1_drvvbus usb1_drvvbus 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual

timer16 7 IO gpio6_12 14 IO Driver off 15 I

AF11 usb2_dm usb2_dm 0 IO 3.3 vdda33v_usb2No USB2PHY

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

b1

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

USB3PHY

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 1

PU/PD

DSIS [15]

AE11 usb2_dp usb2_dp 0 IO 3.3 vdda33v_usb2No USB2PHY

AC10 usb2_drvvbus usb2_drvvbus 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual

timer15 7 IO gpio6_13 14 IO

Driver off 15 I

AF12 usb_rxn0 usb_rxn0 0 I OFF OFF 1.8 vdda_usb1 AE12 usb_rxp0 usb_rxp0 0 I OFF OFF 1.8 vdda_usb1 AC11 usb_txn0 usb_txn0 0 O 1.8 vdda_usb1 AD11 usb_txp0 usb_txp0 0 O 1.8 vdda_usb1

54

Voltage LVCMOS

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DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

H13, H14, J17, J18, L7, L8, N10, N13, P11, P12, P13, R11, R16, R19, T13, T16, T19, U13, U16, U8, U9, V16, V8

AA12 vdda33v_usb1 vdda33v_usb1 PWR Y12 vdda33v_usb2 vdda33v_usb2 PWR M14 vdda_abe_per vdda_abe_per PWR P16 vdda_ddr vdda_ddr PWR N11 vdda_debug vdda_debug PWR N12 vdda_dsp_eve vdda_dsp_eve PWR P15 vdda_gmac_core vdda_gmac_core PWR R14 vdda_gpu vdda_gpu PWR Y17 vdda_hdmi vdda_hdmi PWR R17 vdda_iva vdda_iva PWR N16 vdda_mpu vdda_mpu PWR AD16, AE16 vdda_osc vdda_osc PWR W14 vdda_pcie vdda_pcie PWR AA17 vdda_pcie0 vdda_pcie0 PWR AA16 vdda_pcie1 vdda_pcie1 PWR AB13 vdda_rtc vdda_rtc PWR V13 vdda_sata vdda_sata PWR AA13 vdda_usb1 vdda_usb1 PWR AB12 vdda_usb2 vdda_usb2 PWR W12 vdda_usb3 vdda_usb3 PWR P14 vdda_video vdda_video PWR G18, H17, M8, M9,

N8, P8, R8, T8, V21, V22, W17, W18

AA18, AA19, W21, Y21

J21, J22, N21, P20, P21

E3, E5, G4, G5, H8,H9vddshv1 vddshv1 PWR

vdd vdd PWR

vdds18v vdds18v PWR

vdds18v_ddr1 vdds18v_ddr1 PWR

vdds18v_ddr2 vdds18v_ddr2 PWR

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

PULL UP/DOWN TYPE [14]

DSIS [15]

N4, N5, P10, R10, R7, T4, T5

J8, K8 vddshv11 vddshv11 PWR

vddshv10 vddshv10 PWR

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SPRS950F –DECEMBER 2015–REVISED MAY 2019

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Table 4-2. Ball Characteristics

(7)

MUXMODE

[5]

14 IO

TYPE [6]

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

B6, D10, E10, H10, H11

B23, D16, D22, E16, E22, G15, H15, H16, H18, H19

C24 vddshv4 vddshv4 PWR V12 vddshv5 vddshv5 PWR AD5, AD7, AE7,

AF5 AB6, AB7 vddshv7 vddshv7 PWR W8, Y8 vddshv8 vddshv8 PWR U10, W4, W5 vddshv9 vddshv9 PWR AA21, AA22, AB21,

AB22, AB24, AB25, AC22, AD26, AG20, AG28, AH27, W16, W27

E24, G22, G23, H20, H21, H22, J27, L20, L21, M20, M21, T24, T25

AA7, Y7 vdds_mlbp vdds_mlbp PWR J13, K10, K11, K12,

K13, L10, L11, L12, M10, M11, M12, M13

U11, U12, V10, V11, V14, W10, W11, W13

U18, U19, V18, V19 vdd_iva vdd_iva PWR K17, K18, L15, L16,

L17, L18, L19, M15, M16, M17, M18, N17, N18, P17, P18, R18

AB15 vdd_rtc vdd_rtc PWR AG8 vin1a_clk0 vin1a_clk0 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vddshv2 vddshv2 PWR

vddshv3 vddshv3 PWR

vddshv6 vddshv6 PWR

vdds_ddr1 vdds_ddr1 PWR

vdds_ddr2 vdds_ddr2 PWR

vdd_dspeve vdd_dspeve PWR

vdd_gpu vdd_gpu PWR

vdd_mpu vdd_mpu PWR

(9)

vout3_d16

(9)

vout3_fld gpio2_30

Driver off 15 I

No 3 O No 4 O

Yes

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

56

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DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

(7)

MUXMODE

[5]

14 IO

TYPE [6]

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AE8 vin1a_d0 vin1a_d0 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

(9)

vout3_d7

(9)

vout3_d23 uart8_rxd No 5 I 1 ehrpwm1A No 10 O gpio3_4

Driver off 15 I

AD8 vin1a_d1 vin1a_d1 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

(9)

vout3_d6

(9)

vout3_d22 uart8_txd No 5 O ehrpwm1B No 10 O gpio3_5

Driver off 15 I

AG3 vin1a_d10 vin1a_d10 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d5 No 1 I 0

(9)

vout3_d13 kbd_row4 No 9 I 0 gpio3_14

Driver off 15 I

AG5 vin1a_d11 vin1a_d11 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d4 No 1 I 0

(9)

vout3_d12 gpmc_a23 No 5 O kbd_row5 No 9 I 0 gpio3_15

Driver off 15 I

AF2 vin1a_d12 vin1a_d12 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d3 No 1 I 0 usb3_ulpi_d7 No 2 IO 0

(9)

vout3_d11 gpmc_a24 No 5 O kbd_row6 No 9 I 0 gpio3_16

Driver off 15 I

No 3 O No 4 O

Yes

No 3 O No 4 O

Yes

No 4 O

Yes

No 4 O

Yes

No 4 O

Yes

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

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Table 4-2. Ball Characteristics

(7)

MUXMODE

[5]

14 IO

TYPE [6]

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AF6 vin1a_d13 vin1a_d13 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d2 No 1 I 0 usb3_ulpi_d6 No 2 IO 0

(9)

vout3_d10 gpmc_a25 No 5 O kbd_row7 No 9 I 0 gpio3_17

Driver off 15 I

AF3 vin1a_d14 vin1a_d14 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d1 No 1 I 0 usb3_ulpi_d5 No 2 IO 0

(9)

vout3_d9 gpmc_a26 No 5 O kbd_row8 No 9 I 0 gpio3_18

Driver off 15 I

AF4 vin1a_d15 vin1a_d15 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d0 No 1 I 0 usb3_ulpi_d4 No 2 IO 0

(9)

vout3_d8 gpmc_a27 No 5 O kbd_col0 No 9 O gpio3_19

Driver off 15 I

AF1 vin1a_d16 vin1a_d16 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d7 No 1 I 0 usb3_ulpi_d3 No 2 IO 0

(9)

vout3_d7 vin3a_d0 No 6 I 0 kbd_col1 No 9 O gpio3_20

Driver off 15 I

No 4 O

Yes

No 4 O

Yes

No 4 O

Yes

No 4 O

Yes

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

58

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

(7)

MUXMODE

[5]

14 IO

TYPE [6]

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AE3 vin1a_d17 vin1a_d17 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d6 No 1 I 0 usb3_ulpi_d2 No 2 IO 0

(9)

vout3_d6 vin3a_d1 No 6 I 0 kbd_col2 No 9 O gpio3_21

Driver off 15 I

AE5 vin1a_d18 vin1a_d18 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d5 No 1 I 0 usb3_ulpi_d1 No 2 IO 0

(9)

vout3_d5 vin3a_d2 No 6 I 0 kbd_col3 No 9 O gpio3_22

Driver off 15 I

AE1 vin1a_d19 vin1a_d19 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d4 No 1 I 0 usb3_ulpi_d0 No 2 IO 0

(9)

vout3_d4 vin3a_d3 No 6 I 0 kbd_col4 No 9 O gpio3_23

Driver off 15 I

AG7 vin1a_d2 vin1a_d2 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

(9)

vout3_d5

(9)

vout3_d21 uart8_ctsn No 5 I 1 ehrpwm1_tripzone_input No 10 IO 0 gpio3_6

Driver off 15 I

No 4 O

Yes

No 4 O

Yes

No 4 O

Yes

No 3 O No 4 O

Yes

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

(7)

MUXMODE

[5]

14 IO

TYPE [6]

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AE2 vin1a_d20 vin1a_d20 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d3 No 1 I 0 usb3_ulpi_nxt No 2 I 0

(9)

vout3_d3 vin3a_d4 No 6 I 0 kbd_col5 No 9 O gpio3_24

Driver off 15 I

AE6 vin1a_d21 vin1a_d21 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d2 No 1 I 0 usb3_ulpi_dir No 2 I 0

(9)

vout3_d2 vin3a_d5 No 6 I 0 kbd_col6 No 9 O gpio3_25

Driver off 15 I

AD2 vin1a_d22 vin1a_d22 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d1 No 1 I 0 usb3_ulpi_stp No 2 O

(9)

vout3_d1 vin3a_d6 No 6 I 0 kbd_col7 No 9 O gpio3_26

Driver off 15 I

AD3 vin1a_d23 vin1a_d23 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d0 No 1 I 0 usb3_ulpi_clk No 2 I 0

(9)

vout3_d0 vin3a_d7 No 6 I 0 kbd_col8 No 9 O gpio3_27

Driver off 15 I

No 4 O

Yes

No 4 O

Yes

No 4 O

Yes

No 4 O

Yes

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

60

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AH6 vin1a_d3 vin1a_d3 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vout3_d4 vout3_d20

(9)

No 3 O No 4 O

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

uart8_rtsn No 5 O eCAP1_in_PWM1_out No 10 IO 0 gpio3_7

Yes

(7)

14 IO

Driver off 15 I

AH3 vin1a_d4 vin1a_d4 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vout3_d3 vout3_d19

(9)

No 3 O No 4 O

Voltage LVCMOS

ehrpwm1_synci No 10 I 0 gpio3_8

Yes

(7)

14 IO

Driver off 15 I

AH5 vin1a_d5 vin1a_d5 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vout3_d2 vout3_d18

(9)

No 3 O No 4 O

Voltage LVCMOS

ehrpwm1_synco No 10 O gpio3_9

Yes

(7)

14 IO

Driver off 15 I

AG6 vin1a_d6 vin1a_d6 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vout3_d1 vout3_d17

(9)

No 3 O No 4 O

Voltage LVCMOS

eQEP2A_in No 10 I 0 gpio3_10

Yes

(7)

14 IO

Driver off 15 I

AH4 vin1a_d7 vin1a_d7 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vout3_d0 vout3_d16

(9)

No 3 O No 4 O

Voltage LVCMOS

eQEP2B_in No 10 I 0 gpio3_11

Yes

(7)

14 IO

Driver off 15 I

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

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Table 4-2. Ball Characteristics

(7)

MUXMODE

[5]

14 IO

TYPE [6]

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AG4 vin1a_d8 vin1a_d8 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d7 No 1 I 0

(9)

vout3_d15 kbd_row2 No 9 I 0 eQEP2_index No 10 IO 0 gpio3_12

Driver off 15 I

AG2 vin1a_d9 vin1a_d9 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_d6 No 1 I 0

(9)

vout3_d14 kbd_row3 No 9 I 0 eQEP2_strobe No 10 IO 0 gpio3_13

Driver off 15 I

AD9 vin1a_de0 vin1a_de0 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_hsync1 No 1 I 0

(9)

vout3_d17

(9)

vout3_de uart7_rxd No 5 I 1 timer16 No 7 IO spi3_sclk No 8 IO 0 kbd_row0 No 9 I 0 eQEP1A_in No 10 I 0 gpio3_0

Driver off 15 I

AF9 vin1a_fld0 vin1a_fld0 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_vsync1 No 1 I 0

(9)

vout3_clk uart7_txd No 5 O timer15 No 7 IO spi3_d1 No 8 IO 0 kbd_row1 No 9 I 0 eQEP1B_in No 10 I 0 gpio3_1

Driver off 15 I

No 4 O

Yes

No 4 O

Yes

No 3 O No 4 O

Yes

No 4 O

Yes

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

62

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

(7)

MUXMODE

[5]

14 IO

TYPE [6]

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AE9 vin1a_hsync0 vin1a_hsync0 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_fld1 No 1 I 0 vout3_hsync

uart7_ctsn No 5 I 1 timer14 No 7 IO spi3_d0 No 8 IO 0 eQEP1_index No 10 IO 0 gpio3_2

Driver off 15 I

AF8 vin1a_vsync0 vin1a_vsync0 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin1b_de1 No 1 I 0 vout3_vsync

uart7_rtsn No 5 O timer13 No 7 IO spi3_cs0 No 8 IO 1 eQEP1_strobe No 10 IO 0 gpio3_3

Driver off 15 I

AH7 vin1b_clk1 vin1b_clk1 No 0 I PD PD 15 1.8/3.3 vddshv6 Yes Dual

vin3a_clk0 No 6 I 0 gpio2_31

Driver off 15 I

E1 vin2a_clk0 vin2a_clk0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vout2_fld 4 O emu5 5 O kbd_row0 9 I 0 eQEP1A_in 10 I 0 gpio3_28 14 IO Driver off 15 I

(9)

No 4 O

Yes

No 4 O

Yes

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

PU/PD

DSIS [15]

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

F2 vin2a_d0 vin2a_d0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vout2_d23 4 O emu10 5 O uart9_ctsn 7 I 1 spi4_d0 8 IO 0 kbd_row4 9 I 0 ehrpwm1B 10 O gpio4_1 14 IO Driver off 15 I

F3 vin2a_d1 vin2a_d1 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vout2_d22 4 O emu11 5 O uart9_rtsn 7 O spi4_cs0 8 IO 1 kbd_row5 9 I 0 ehrpwm1_tripzone_input 10 IO 0 gpio4_2 14 IO Driver off 15 I

D3 vin2a_d10 vin2a_d10 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

mdio_mclk 3 O 1 vout2_d13 4 O kbd_col7 9 O ehrpwm2B 10 O gpio4_11 14 IO Driver off 15 I

F6 vin2a_d11 vin2a_d11 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

mdio_d 3 IO 1 vout2_d12 4 O kbd_row7 9 I 0 ehrpwm2_tripzone_input 10 IO 0 gpio4_12 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

64

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

D5 vin2a_d12 vin2a_d12 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

rgmii1_txc 3 O vout2_d11 4 O mii1_rxclk 8 I 0 kbd_col8 9 O eCAP2_in_PWM2_out 10 IO 0 gpio4_13 14 IO Driver off 15 I

C2 vin2a_d13 vin2a_d13 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

rgmii1_txctl 3 O vout2_d10 4 O mii1_rxdv 8 I 0 kbd_row8 9 I 0 eQEP3A_in 10 I 0 gpio4_14 14 IO Driver off 15 I

C3 vin2a_d14 vin2a_d14 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

rgmii1_txd3 3 O vout2_d9 4 O mii1_txclk 8 I 0 eQEP3B_in 10 I 0 gpio4_15 14 IO Driver off 15 I

C4 vin2a_d15 vin2a_d15 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

rgmii1_txd2 3 O vout2_d8 4 O mii1_txd0 8 O eQEP3_index 10 IO 0 gpio4_16 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

Submit Documentation Feedback

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

B2 vin2a_d16 vin2a_d16 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2b_d7 2 I 0 rgmii1_txd1 3 O vout2_d7 4 O vin3a_d8 6 I 0 mii1_txd1 8 O eQEP3_strobe 10 IO 0 gpio4_24 14 IO Driver off 15 I

D6 vin2a_d17 vin2a_d17 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2b_d6 2 I 0 rgmii1_txd0 3 O vout2_d6 4 O vin3a_d9 6 I 0 mii1_txd2 8 O ehrpwm3A 10 O gpio4_25 14 IO Driver off 15 I

C5 vin2a_d18 vin2a_d18 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2b_d5 2 I 0 rgmii1_rxc 3 I 0 vout2_d5 4 O vin3a_d10 6 I 0 mii1_txd3 8 O ehrpwm3B 10 O gpio4_26 14 IO Driver off 15 I

A3 vin2a_d19 vin2a_d19 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2b_d4 2 I 0 rgmii1_rxctl 3 I 0 vout2_d4 4 O vin3a_d11 6 I 0 mii1_txer 8 O 0 ehrpwm3_tripzone_input 10 IO 0 gpio4_27 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

66

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

D1 vin2a_d2 vin2a_d2 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vout2_d21 4 O emu12 5 O uart10_rxd 8 I 1 kbd_row6 9 I 0 eCAP1_in_PWM1_out 10 IO 0 gpio4_3 14 IO Driver off 15 I

B3 vin2a_d20 vin2a_d20 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2b_d3 2 I 0 rgmii1_rxd3 3 I 0 vout2_d3 4 O vin3a_de0 5 I 0 vin3a_d12 6 I 0 mii1_rxer 8 I 0 eCAP3_in_PWM3_out 10 IO 0 gpio4_28 14 IO Driver off 15 I

B4 vin2a_d21 vin2a_d21 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2b_d2 2 I 0 rgmii1_rxd2 3 I 0 vout2_d2 4 O vin3a_fld0 5 I 0 vin3a_d13 6 I 0 mii1_col 8 I 0 gpio4_29 14 IO Driver off 15 I

B5 vin2a_d22 vin2a_d22 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2b_d1 2 I 0 rgmii1_rxd1 3 I 0 vout2_d1 4 O vin3a_hsync0 5 I 0 vin3a_d14 6 I 0 mii1_crs 8 I 0 gpio4_30 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

Submit Documentation Feedback

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

A4 vin2a_d23 vin2a_d23 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2b_d0 2 I 0 rgmii1_rxd0 3 I 0 vout2_d0 4 O vin3a_vsync0 5 I 0 vin3a_d15 6 I 0 mii1_txen 8 O gpio4_31 14 IO Driver off 15 I

E2 vin2a_d3 vin2a_d3 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vout2_d20 4 O emu13 5 O uart10_txd 8 O kbd_col0 9 O ehrpwm1_synci 10 I 0 gpio4_4 14 IO Driver off 15 I

D2 vin2a_d4 vin2a_d4 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vout2_d19 4 O emu14 5 O uart10_ctsn 8 I 1 kbd_col1 9 O ehrpwm1_synco 10 O gpio4_5 14 IO Driver off 15 I

F4 vin2a_d5 vin2a_d5 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vout2_d18 4 O emu15 5 O uart10_rtsn 8 O kbd_col2 9 O eQEP2A_in 10 I 0 gpio4_6 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

68

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

C1 vin2a_d6 vin2a_d6 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vout2_d17 4 O emu16 5 O mii1_rxd1 8 I 0 kbd_col3 9 O eQEP2B_in 10 I 0 gpio4_7 14 IO Driver off 15 I

E4 vin2a_d7 vin2a_d7 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vout2_d16 4 O emu17 5 O mii1_rxd2 8 I 0 kbd_col4 9 O eQEP2_index 10 IO 0 gpio4_8 14 IO Driver off 15 I

F5 vin2a_d8 vin2a_d8 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vout2_d15 4 O emu18 5 O mii1_rxd3 8 I 0 kbd_col5 9 O eQEP2_strobe 10 IO 0 gpio4_9 14 IO Driver off 15 I

E6 vin2a_d9 vin2a_d9 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vout2_d14 4 O emu19 5 O mii1_rxd0 8 I 0 kbd_col6 9 O ehrpwm2A 10 O gpio4_10 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD 0

DSIS [15]

Submit Documentation Feedback

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69

DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

G2 vin2a_de0 vin2a_de0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2a_fld0 1 I vin2b_fld1 2 I vin2b_de1 3 I vout2_de 4 O emu6 5 O kbd_row1 9 I 0 eQEP1B_in 10 I 0 gpio3_29 14 IO Driver off 15 I

H7 vin2a_fld0 vin2a_fld0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2b_clk1 2 I vout2_clk 4 O emu7 5 O eQEP1_index 10 IO 0 gpio3_30 14 IO Driver off 15 I

G1 vin2a_hsync0 vin2a_hsync0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2b_hsync1 3 I vout2_hsync 4 O emu8 5 O uart9_rxd 7 I 1 spi4_sclk 8 IO 0 kbd_row2 9 I 0 eQEP1_strobe 10 IO 0 gpio3_31 14 IO Driver off 15 I

G6 vin2a_vsync0 vin2a_vsync0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual

vin2b_vsync1 3 I vout2_vsync 4 O emu9 5 O uart9_txd 7 O spi4_d1 8 IO 0 kbd_row3 9 I 0 ehrpwm1A 10 O gpio4_0 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

70

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

D11 vout1_clk vout1_clk 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

vin4a_fld0 3 I 0 vin3a_fld0 4 I 0 spi3_cs0 8 IO 1 gpio4_19 14 IO Driver off 15 I

F11 vout1_d0 vout1_d0 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

uart5_rxd 2 I 1 vin4a_d16 3 I 0 vin3a_d16 4 I 0 spi3_cs2 8 IO 1 gpio8_0 14 IO Driver off 15 I

G10 vout1_d1 vout1_d1 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

uart5_txd 2 O vin4a_d17 3 I 0 vin3a_d17 4 I 0 gpio8_1 14 IO Driver off 15 I

D7 vout1_d10 vout1_d10 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu3 2 O vin4a_d10 3 I 0 vin3a_d10 4 I 0 obs5 5 O obs21 6 O obs_irq2 7 O gpio8_10 14 IO Driver off 15 I

D8 vout1_d11 vout1_d11 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu10 2 O vin4a_d11 3 I 0 vin3a_d11 4 I 0 obs6 5 O obs22 6 O obs_dmarq2 7 O gpio8_11 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

Submit Documentation Feedback

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

A5 vout1_d12 vout1_d12 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu11 2 O vin4a_d12 3 I 0 vin3a_d12 4 I 0 obs7 5 O obs23 6 O gpio8_12 14 IO Driver off 15 I

C6 vout1_d13 vout1_d13 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu12 2 O vin4a_d13 3 I 0 vin3a_d13 4 I 0 obs8 5 O obs24 6 O gpio8_13 14 IO Driver off 15 I

C8 vout1_d14 vout1_d14 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu13 2 O vin4a_d14 3 I 0 vin3a_d14 4 I 0 obs9 5 O obs25 6 O gpio8_14 14 IO Driver off 15 I

C7 vout1_d15 vout1_d15 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu14 2 O vin4a_d15 3 I 0 vin3a_d15 4 I 0 obs10 5 O obs26 6 O gpio8_15 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

72

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

B7 vout1_d16 vout1_d16 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

uart7_rxd 2 I 1 vin4a_d0 3 I 0 vin3a_d0 4 I 0 gpio8_16 14 IO Driver off 15 I

B8 vout1_d17 vout1_d17 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

uart7_txd 2 O vin4a_d1 3 I 0 vin3a_d1 4 I 0 gpio8_17 14 IO Driver off 15 I

A7 vout1_d18 vout1_d18 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu4 2 O vin4a_d2 3 I 0 vin3a_d2 4 I 0 obs11 5 O obs27 6 O gpio8_18 14 IO Driver off 15 I

A8 vout1_d19 vout1_d19 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu15 2 O vin4a_d3 3 I 0 vin3a_d3 4 I 0 obs12 5 O obs28 6 O gpio8_19 14 IO Driver off 15 I

F10 vout1_d2 vout1_d2 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu2 2 O vin4a_d18 3 I 0 vin3a_d18 4 I 0 obs0 5 O obs16 6 O obs_irq1 7 O gpio8_2 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

Submit Documentation Feedback

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73

DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

C9 vout1_d20 vout1_d20 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu16 2 O vin4a_d4 3 I 0 vin3a_d4 4 I 0 obs13 5 O obs29 6 O gpio8_20 14 IO Driver off 15 I

A9 vout1_d21 vout1_d21 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu17 2 O vin4a_d5 3 I 0 vin3a_d5 4 I 0 obs14 5 O obs30 6 O gpio8_21 14 IO Driver off 15 I

B9 vout1_d22 vout1_d22 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu18 2 O vin4a_d6 3 I 0 vin3a_d6 4 I 0 obs15 5 O obs31 6 O gpio8_22 14 IO Driver off 15 I

A10 vout1_d23 vout1_d23 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu19 2 O vin4a_d7 3 I 0 vin3a_d7 4 I 0 spi3_cs3 8 IO 1 gpio8_23 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

74

Submit Documentation Feedback

Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

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DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

G11 vout1_d3 vout1_d3 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu5 2 O vin4a_d19 3 I 0 vin3a_d19 4 I 0 obs1 5 O obs17 6 O obs_dmarq1 7 O gpio8_3 14 IO Driver off 15 I

E9 vout1_d4 vout1_d4 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu6 2 O vin4a_d20 3 I 0 vin3a_d20 4 I 0 obs2 5 O obs18 6 O gpio8_4 14 IO Driver off 15 I

F9 vout1_d5 vout1_d5 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu7 2 O vin4a_d21 3 I 0 vin3a_d21 4 I 0 obs3 5 O obs19 6 O gpio8_5 14 IO Driver off 15 I

F8 vout1_d6 vout1_d6 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu8 2 O vin4a_d22 3 I 0 vin3a_d22 4 I 0 obs4 5 O obs20 6 O gpio8_6 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

Submit Documentation Feedback

Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

75

DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

www.ti.com

Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

E7 vout1_d7 vout1_d7 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

emu9 2 O vin4a_d23 3 I 0 vin3a_d23 4 I 0 gpio8_7 14 IO Driver off 15 I

E8 vout1_d8 vout1_d8 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

uart6_rxd 2 I 1 vin4a_d8 3 I 0 vin3a_d8 4 I 0 gpio8_8 14 IO Driver off 15 I

D9 vout1_d9 vout1_d9 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

uart6_txd 2 O vin4a_d9 3 I 0 vin3a_d9 4 I 0 gpio8_9 14 IO Driver off 15 I

B10 vout1_de vout1_de 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

vin4a_de0 3 I 0 vin3a_de0 4 I 0 spi3_d1 8 IO 0 gpio4_20 14 IO Driver off 15 I

B11 vout1_fld vout1_fld 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

vin4a_clk0 3 I 0 vin3a_clk0 4 I 0 spi3_cs1 8 IO 1 gpio4_21 14 IO Driver off 15 I

C11 vout1_hsync vout1_hsync 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

vin4a_hsync0 3 I 0 vin3a_hsync0 4 I 0 spi3_d0 8 IO 0 gpio4_22 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

76

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

E11 vout1_vsync vout1_vsync 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual

vin4a_vsync0 3 I 0 vin3a_vsync0 4 I 0 spi3_sclk 8 IO 0 gpio4_23 14 IO Driver off 15 I

A1, A14, A2, A23, A28, A6, AA10, AA14, AA15, AA20, AA8, AA9, AB14, AB20, AD1, AD24, AG1, AH1, AH2, AH20, AH28, AH8, B1, D13, D19, E13, E19, F1, F7, G7, G8, G9, H12, J12, J15, J28, K1, K15, K24, K25, K4, K5, L13, L14, M19, N14, N15, N19, N24, N25, P28, R1, R12, R13, R15, R21, T10, T11, T12, T14, T15, T17, T18, T21, U15, U17, U20, U21, V15, V17, W1, W15, W24, W25, W28

AD19, AE19 vssa_hdmi vssa_hdmi GND AF15 vssa_osc0 vssa_osc0 GND AC14 vssa_osc1 vssa_osc1 GND AD13, AE13 vssa_pcie vssa_pcie GND AE10 vssa_sata vssa_sata GND AA11, AB11 vssa_usb vssa_usb GND AD10 vssa_usb3 vssa_usb3 GND U14 vssa_video vssa_video GND AD17 Wakeup0 Wakeup0 0 I OFF OFF 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD

AC17 Wakeup1 Wakeup1 0 I OFF OFF 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD

vss vss GND

dcan1_rx 1 I 1 gpio1_0 14 I Driver off 15 I

dcan2_rx 1 I 1 gpio1_1 14 I Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

AB16 Wakeup2 Wakeup2 0 I OFF OFF 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD

sys_nirq2 1 I gpio1_2 14 I Driver off 15 I

AC16 Wakeup3 Wakeup3 0 I OFF OFF 15 1.8/3.3 vddshv5 Yes IHHV1833 PU/PD

sys_nirq1 1 I gpio1_3 14 I Driver off 15 I

AE15 xi_osc0 xi_osc0 0 I 1.8 vdda_osc No LVCMOS

AC15 xi_osc1 xi_osc1 0 I 1.8 vdda_osc No LVCMOS

AD15 xo_osc0 xo_osc0 0 O 1.8 vdda_osc No LVCMOS

AC13 xo_osc1 xo_osc1 0 A 1.8 vdda_osc No LVCMOS

D18 xref_clk0 xref_clk0 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp2_axr8 1 IO 0 mcasp1_axr4 2 IO 0 mcasp1_ahclkx 3 O mcasp5_ahclkx 4 O atl_clk0 5 O vin6a_d0 No 7 I 0 hdq0 8 IO 1 clkout2 9 O timer13 10 IO gpio6_17 14 IO Driver off 15 I

E17 xref_clk1 xref_clk1 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp2_axr9 1 IO 0 mcasp1_axr5 2 IO 0 mcasp2_ahclkx 3 O mcasp6_ahclkx 4 O atl_clk1 5 O vin6a_clk0 No 7 I 0 timer14 10 IO gpio6_18 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Analog

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

78

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Table 4-2. Ball Characteristics

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 74x [4]

B26 xref_clk2 xref_clk2 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp2_axr10 1 IO 0 mcasp1_axr6 2 IO 0 mcasp3_ahclkx 3 O mcasp7_ahclkx 4 O atl_clk2 5 O vout2_clk 6 O vin4a_clk0 8 I 0 timer15 10 IO gpio6_19 14 IO Driver off 15 I

C23 xref_clk3 xref_clk3 0 I PD PD 15 1.8/3.3 vddshv3 Yes Dual

mcasp2_axr11 1 IO 0 mcasp1_axr7 2 IO 0 mcasp4_ahclkx 3 O mcasp8_ahclkx 4 O atl_clk3 5 O vout2_de 6 O hdq0 7 IO 1 vin4a_de0 8 I 0 clkout3 9 O timer16 10 IO gpio6_20 14 IO Driver off 15 I

MUXMODE

[5]

TYPE [6]

(1)

(continued)

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

Voltage LVCMOS

PULL UP/DOWN TYPE [14]

PU/PD

DSIS [15]

(1) NA in this table stands for Not Applicable. (2) For more information on recommended operating conditions, see Table 5-4, Recommended Operating Conditions. (3) The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA. (4) The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the

Device TRM. (5) IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V). (6) Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.

For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification. (7) This function will not be supported on some pin-compatibleroadmap devices. Pin compatibility can be maintained in the future by not using these GPIO signals. (8) In PUx / PDy, x and y = 60 to 200 μA.

The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers. (9) The VOUT3 interface when multiplexed onto balls mapped to the VDDSHV6 supply rail is restricted to operating in 1.8V mode only (VDDSHV6 must be supplied with 1.8V). 3.3V mode is

not supported. This must be considered in the pin mux programming and VDDSHVx supply connections.

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(10) The internal pull resistors for balls K7, M7, J5, K6, J4, J6, H4, H5 are permanently disabled when sysboot15 is set to 1 as described in the section Sysboot Configuration of the Device

TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 0. If gpmc boot mode is used with SYSBOOT15=1 (not recommended) then external

pull-downs should be implemented to keep the address bus at logic-0 value during boot since the gpmc ms-address bits are high-z during boot.

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4.3 Multiplexing Characteristics

Table 4-3 describes the device multiplexing (no characteristics are available in this table).

NOTE

This table doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.4, Signal Descriptions.

NOTE

For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration section of the Device TRM.

NOTE

Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration. (Hi-Z mode is not an input signal.)

ADDRESS REGISTER NAME

80

NOTE

When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

CAUTION

The I/O timings provided in Section 7, Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in the corresponding tables.

Table 4-3. Multiplexing Characteristics

BALL

NUMBER

P25 ddr2_a6

0 1 2 3 4 5 6 7 8 9 10 14 15

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MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

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ADDRESS REGISTER NAME

BALL

NUMBER

Y23 ddr1_d26

Y19 ddr1_d21 AE15 xi_osc0 AH24 ddr1_nck AG15 ljcb_clkp AF24 ddr1_d4

U25 ddr2_wen F27 ddr2_d5 V25 ddr1_ecc_d6 M27 ddr2_dqsn3

G26 ddr2_d12 AG19 hdmi1_data2x AF21 ddr1_a4

E27 ddr2_d6

F24 ddr2_d3

H26 ddr2_d11

W23 ddr1_ecc_d3

Y27 ddr1_dqsn3 AC24 ddr1_d14

J24 ddr2_d15

R26 ddr2_a1

G27 ddr2_dqsn0 AF28 ddr1_d11 AA23 ddr1_d24 AD18 ddr1_a15

H23 ddr2_d8 AH16 hdmi1_clocky AC20 ddr1_a2 AA24 ddr1_d27

W19 ddr1_ecc_d2

L24 ddr2_d20 AG11 pcie_rxn1 AG21 ddr1_rst AE28 ddr1_dqsn1 AC11 usb_txn0

L22 ddr2_d16

U28 ddr2_casn

K22 ddr2_d22 AG25 ddr1_dqsn0

0 1 2 3 4 5 6 7 8 9 10 14 15

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Table 4-3. Multiplexing Characteristics (continued)

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

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ADDRESS REGISTER NAME

BALL

NUMBER

W20 ddr1_d17 AF14 rtc_iso AA27 ddr1_dqm3 AF25 ddr1_d0 AF23 ddr1_d6 AG18 hdmi1_data1x AG10 sata1_txn0 AF20 ddr1_rasn

V26 ddr1_dqm_ec

V20 ddr1_d16

G25 ddr2_d1 AH13 pcie_rxp0 AC18 ddr1_casn

AG9 sata1_rxp0 AH23 ddr1_csn0 AE11 usb2_dp

R25 ddr2_a0

Y24 ddr1_d28 AH15 ljcb_clkn AD20 ddr1_a0 AA25 ddr1_d30

L23 ddr2_d19

AA1 mlbp_dat_p

AD14 rtc_osc_xo

J25 ddr2_d13 AC25 ddr1_d13 AB23 ddr1_dqm1

U22 ddr2_a15

T22 ddr2_a13 AH19 hdmi1_data2y

M26 ddr2_d31 AB27 ddr1_d22 AG14 pcie_txn0

Y28 ddr1_dqs3

J20 ddr2_d23 AB19 ddr1_a3 AH10 sata1_txp0

G28 ddr2_dqs0

0 1 2 3 4 5 6 7 8 9 10 14 15

c

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Table 4-3. Multiplexing Characteristics (continued)

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

82

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ADDRESS REGISTER NAME

BALL

NUMBER

AG24 ddr1_ck AE24 ddr1_d5 AC15 xi_osc1 AC21 ddr1_a12

K28 ddr2_dqsn2

AB1 mlbp_clk_p

AF12 usb_rxn0

L28 ddr2_d27

M24 ddr2_d29

AH9 sata1_rxn0 AC26 ddr1_dqm2 AA28 ddr1_d31

H28 ddr2_dqsn1

AD23 ddr1_dqm0

E26 ddr2_d0 AE27 ddr1_dqs1 AF27 ddr1_d9

V24 ddr1_ecc_d5

K23 ddr2_dqm2

K20 ddr2_d17

T28 ddr2_ck

H24 ddr2_d10 AG27 ddr1_d10

R23 ddr2_odt0

U27 ddr2_ba1 AF22 ddr1_a8

AA2 mlbp_dat_n

U23 ddr2_ba0 AH21 ddr1_wen AE21 ddr1_a7 AC12 usb1_dm AH12 pcie_txp1

Y20 ddr1_d23 AC27 ddr1_d20 AE23 ddr1_d7

T27 ddr2_nck AG22 ddr1_cke AD27 ddr1_dqs2 AH14 pcie_txp0

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Table 4-3. Multiplexing Characteristics (continued)

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

0 1 2 3 4 5 6 7 8 9 10 14 15

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ADDRESS REGISTER NAME

BALL

NUMBER

AH26 ddr1_d3 AD21 ddr1_a10

N28 ddr2_a12

Y25 ddr1_ecc_d4 AE17 ddr1_a14 AH18 hdmi1_data1y AH22 ddr1_a5

J26 ddr2_d14

W22 ddr1_ecc_d0

V23 ddr1_ecc_d1 AE12 usb_rxp0 AE14 rtc_osc_xi_clki

AH11 pcie_rxp1

AB2 mlbp_clk_n

AG23 ddr1_a6

H27 ddr2_dqs1 AB18 ddr1_ba2 AG17 hdmi1_data0x AF26 ddr1_d1

H25 ddr2_d9

M25 ddr2_d30

AD11 usb_txp0

AC1 mlbp_sig_p

L27 ddr2_d24

V27 ddr1_dqs_ecc AF17 ddr1_ba0 AE26 ddr1_d12

G24 ddr2_dqm1

K27 ddr2_dqs2 AC19 ddr1_a1 AG13 pcie_rxn0

L26 ddr2_d25 AB28 ddr1_d18

N23 ddr2_a10

M22 ddr2_dqm3

U26 ddr2_ba2

Y26 ddr1_ecc_d7

P24 ddr2_csn0

0 1 2 3 4 5 6 7 8 9 10 14 15

n32

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Table 4-3. Multiplexing Characteristics (continued)

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

84

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ADDRESS REGISTER NAME

BALL

NUMBER

R22 ddr2_a14 AD22 ddr1_a11

N20 ddr2_a7

M23 ddr2_d28

AD28 ddr1_dqsn2

U24 ddr2_cke

P22 ddr2_a5 AE18 ddr1_ba1

F26 ddr2_d4 AE20 ddr1_odt0

N22 ddr2_vref0

E28 ddr2_d7

F25 ddr2_d2 AF11 usb2_dm

R24 ddr2_rst AD15 xo_osc0

R27 ddr2_a3 AE22 ddr1_a9

Y18 ddr1_vref0 AC13 xo_osc1

F28 ddr2_dqm0

J23 ddr2_d21

P26 ddr2_a11

M28 ddr2_dqs3 AC2 mlbp_sig_n

AD12 usb1_dp

Y22 ddr1_d25

T23 ddr2_rasn AH17 hdmi1_data0y

N27 ddr2_a9

P23 ddr2_a4 AG26 ddr1_d2 AH25 ddr1_dqs0 AG12 pcie_txn1 AF18 ddr1_a13

K21 ddr2_d18 AC28 ddr1_d19

V28 ddr1_dqsn_ec

0 1 2 3 4 5 6 7 8 9 10 14 15

c

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Table 4-3. Multiplexing Characteristics (continued)

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

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ADDRESS REGISTER NAME

0x1400 CTRL_CORE_PAD_

0x1404 CTRL_CORE_PAD_

0x1408 CTRL_CORE_PAD_

0x140C CTRL_CORE_PAD_

0x1410 CTRL_CORE_PAD_

0x1414 CTRL_CORE_PAD_

0x1418 CTRL_CORE_PAD_

0x141C CTRL_CORE_PAD_

0x1420 CTRL_CORE_PAD_

0x1424 CTRL_CORE_PAD_

0x1428 CTRL_CORE_PAD_

0x142C CTRL_CORE_PAD_

0x1430 CTRL_CORE_PAD_

0x1434 CTRL_CORE_PAD_

0x1438 CTRL_CORE_PAD_

0x143C CTRL_CORE_PAD_

0x1440 CTRL_CORE_PAD_

0x1444 CTRL_CORE_PAD_

0x1448 CTRL_CORE_PAD_

GPMC_AD0

GPMC_AD1

GPMC_AD2

GPMC_AD3

GPMC_AD4

GPMC_AD5

GPMC_AD6

GPMC_AD7

GPMC_AD8

GPMC_AD9

GPMC_AD10

GPMC_AD11

GPMC_AD12

GPMC_AD13

GPMC_AD14

GPMC_AD15

GPMC_A0

GPMC_A1

GPMC_A2

BALL

NUMBER

P27 ddr2_a8 AC23 ddr1_d8

F22 porz

L25 ddr2_d26 AG16 hdmi1_clockx

R28 ddr2_a2 AA26 ddr1_d29 AD25 ddr1_d15

M6 gpmc_ad0 vin3a_d0 vout3_d0 gpio1_6 sysboot0

M2 gpmc_ad1 vin3a_d1 vout3_d1 gpio1_7 sysboot1

L5 gpmc_ad2 vin3a_d2 vout3_d2 gpio1_8 sysboot2

M1 gpmc_ad3 vin3a_d3 vout3_d3 gpio1_9 sysboot3

L6 gpmc_ad4 vin3a_d4 vout3_d4 gpio1_10 sysboot4

L4 gpmc_ad5 vin3a_d5 vout3_d5 gpio1_11 sysboot5

L3 gpmc_ad6 vin3a_d6 vout3_d6 gpio1_12 sysboot6

L2 gpmc_ad7 vin3a_d7 vout3_d7 gpio1_13 sysboot7

L1 gpmc_ad8 vin3a_d8 vout3_d8 gpio7_18 sysboot8

K2 gpmc_ad9 vin3a_d9 vout3_d9 gpio7_19 sysboot9

J1 gpmc_ad10 vin3a_d10 vout3_d10 gpio7_28 sysboot10

J2 gpmc_ad11 vin3a_d11 vout3_d11 gpio7_29 sysboot11

H1 gpmc_ad12 vin3a_d12 vout3_d12 gpio1_18 sysboot12

J3 gpmc_ad13 vin3a_d13 vout3_d13 gpio1_19 sysboot13

H2 gpmc_ad14 vin3a_d14 vout3_d14 gpio1_20 sysboot14

H3 gpmc_ad15 vin3a_d15 vout3_d15 gpio1_21 sysboot15

R6 gpmc_a0 vin3a_d16 vout3_d16 vin4a_d0 vin4b_d0 i2c4_scl uart5_rxd gpio7_3 Driver off

T9 gpmc_a1 vin3a_d17 vout3_d17 vin4a_d1 vin4b_d1 i2c4_sda uart5_txd gpio7_4 Driver off

T6 gpmc_a2 vin3a_d18 vout3_d18 vin4a_d2 vin4b_d2 uart7_rxd uart5_ctsn gpio7_5 Driver off

0 1 2 3 4 5 6 7 8 9 10 14 15

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Table 4-3. Multiplexing Characteristics (continued)

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

86

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ADDRESS REGISTER NAME

0x144C CTRL_CORE_PAD_

0x1450 CTRL_CORE_PAD_

0x1454 CTRL_CORE_PAD_

0x1458 CTRL_CORE_PAD_

0x145C CTRL_CORE_PAD_

0x1460 CTRL_CORE_PAD_

0x1464 CTRL_CORE_PAD_

0x1468 CTRL_CORE_PAD_

0x146C CTRL_CORE_PAD_

0x1470 CTRL_CORE_PAD_

0x1474 CTRL_CORE_PAD_

0x1478 CTRL_CORE_PAD_

0x147C CTRL_CORE_PAD_

0x1480 CTRL_CORE_PAD_

0x1484 CTRL_CORE_PAD_

0x1488 CTRL_CORE_PAD_

0x148C CTRL_CORE_PAD_

0x1490 CTRL_CORE_PAD_

0x1494 CTRL_CORE_PAD_

0x1498 CTRL_CORE_PAD_

0x149C CTRL_CORE_PAD_

0x14A0 CTRL_CORE_PAD_

0x14A4 CTRL_CORE_PAD_

0x14A8 CTRL_CORE_PAD_

GPMC_A3

GPMC_A4

GPMC_A5

GPMC_A6

GPMC_A7

GPMC_A8

GPMC_A9

GPMC_A10

GPMC_A11

GPMC_A12

GPMC_A13

GPMC_A14

GPMC_A15

GPMC_A16

GPMC_A17

GPMC_A18

GPMC_A19

GPMC_A20

GPMC_A21

GPMC_A22

GPMC_A23

GPMC_A24

GPMC_A25

GPMC_A26

DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-3. Multiplexing Characteristics (continued)

BALL

NUMBER

T7 gpmc_a3 qspi1_cs2 vin3a_d19 vout3_d19 vin4a_d3 vin4b_d3 uart7_txd uart5_rtsn gpio7_6 Driver off

P6 gpmc_a4 qspi1_cs3 vin3a_d20 vout3_d20 vin4a_d4 vin4b_d4 i2c5_scl uart6_rxd gpio1_26 Driver off

R9 gpmc_a5 vin3a_d21 vout3_d21 vin4a_d5 vin4b_d5 i2c5_sda uart6_txd gpio1_27 Driver off

R5 gpmc_a6 vin3a_d22 vout3_d22 vin4a_d6 vin4b_d6 uart8_rxd uart6_ctsn gpio1_28 Driver off

P5 gpmc_a7 vin3a_d23 vout3_d23 vin4a_d7 vin4b_d7 uart8_txd uart6_rtsn gpio1_29 Driver off

N7 gpmc_a8 vin3a_hsync0 vout3_hsync vin4b_hsync1 timer12 spi4_sclk gpio1_30 Driver off

R4 gpmc_a9 vin3a_vsync0 vout3_vsync vin4b_vsync1 timer11 spi4_d1 gpio1_31 Driver off

N9 gpmc_a10 vin3a_de0 vout3_de vin4b_clk1 timer10 spi4_d0 gpio2_0 Driver off

P9 gpmc_a11 vin3a_fld0 vout3_fld vin4a_fld0 vin4b_de1 timer9 spi4_cs0 gpio2_1 Driver off

P4 gpmc_a12 vin4a_clk0 gpmc_a0 vin4b_fld1 timer8 spi4_cs1 dma_evt1 gpio2_2 Driver off

R3 gpmc_a13 qspi1_rtclk vin4a_hsync0 timer7 spi4_cs2 dma_evt2 gpio2_3 Driver off

T2 gpmc_a14 qspi1_d3 vin4a_vsync0 timer6 spi4_cs3 gpio2_4 Driver off

U2 gpmc_a15 qspi1_d2 vin4a_d8 timer5 gpio2_5 Driver off

U1 gpmc_a16 qspi1_d0 vin4a_d9 gpio2_6 Driver off

P3 gpmc_a17 qspi1_d1 vin4a_d10 gpio2_7 Driver off

R2 gpmc_a18 qspi1_sclk vin4a_d11 gpio2_8 Driver off

K7 gpmc_a19 mmc2_dat4 gpmc_a13 vin4a_d12 vin3b_d0 gpio2_9 Driver off

M7 gpmc_a20 mmc2_dat5 gpmc_a14 vin4a_d13 vin3b_d1 gpio2_10 Driver off

J5 gpmc_a21 mmc2_dat6 gpmc_a15 vin4a_d14 vin3b_d2 gpio2_11 Driver off

K6 gpmc_a22 mmc2_dat7 gpmc_a16 vin4a_d15 vin3b_d3 gpio2_12 Driver off

J7 gpmc_a23 mmc2_clk gpmc_a17 vin4a_fld0 vin3b_d4 gpio2_13 Driver off

J4 gpmc_a24 mmc2_dat0 gpmc_a18 vin3b_d5 gpio2_14 Driver off

J6 gpmc_a25 mmc2_dat1 gpmc_a19 vin3b_d6 gpio2_15 Driver off

H4 gpmc_a26 mmc2_dat2 gpmc_a20 vin3b_d7 gpio2_16 Driver off

0 1 2 3 4 5 6 7 8 9 10 14 15

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

ADDRESS REGISTER NAME

0x14AC CTRL_CORE_PAD_

0x14B0 CTRL_CORE_PAD_

0x14B4 CTRL_CORE_PAD_

0x14B8 CTRL_CORE_PAD_

0x14BC CTRL_CORE_PAD_

0x14C0 CTRL_CORE_PAD_

0x14C4 CTRL_CORE_PAD_

0x14C8 CTRL_CORE_PAD_

0x14CC CTRL_CORE_PAD_

0x14D0 CTRL_CORE_PAD_

0x14D4 CTRL_CORE_PAD_

0x14D8 CTRL_CORE_PAD_

0x14DC CTRL_CORE_PAD_V

0x14E0 CTRL_CORE_PAD_V

0x14E4 CTRL_CORE_PAD_V

0x14E8 CTRL_CORE_PAD_V

0x14EC CTRL_CORE_PAD_V

0x14F0 CTRL_CORE_PAD_V

0x14F4 CTRL_CORE_PAD_V

0x14F8 CTRL_CORE_PAD_V

0x14FC CTRL_CORE_PAD_V

0x1500 CTRL_CORE_PAD_V

0x1504 CTRL_CORE_PAD_V

0x1508 CTRL_CORE_PAD_V

GPMC_A27

GPMC_CS1

GPMC_CS0

GPMC_CS2

GPMC_CS3

GPMC_CLK

GPMC_ADVN_ALE

GPMC_OEN_REN

GPMC_WEN

GPMC_BEN0

GPMC_BEN1

GPMC_WAIT0

IN1A_CLK0

IN1B_CLK1

IN1A_DE0

IN1A_FLD0

IN1A_HSYNC0

IN1A_VSYNC0

IN1A_D0

IN1A_D1

IN1A_D2

IN1A_D3

IN1A_D4

IN1A_D5

BALL

NUMBER

H5 gpmc_a27 mmc2_dat3 gpmc_a21 vin3b_hsync1 gpio2_17 Driver off

H6 gpmc_cs1 mmc2_cmd gpmc_a22 vin4a_de0 vin3b_vsync1 gpio2_18 Driver off

T1 gpmc_cs0 gpio2_19 Driver off

P2 gpmc_cs2 qspi1_cs0 gpio2_20 Driver off

P1 gpmc_cs3 qspi1_cs1 vin3a_clk0 vout3_clk gpmc_a1 gpio2_21 Driver off

P7 gpmc_clk gpmc_cs7 clkout1 gpmc_wait1 vin4a_hsync0 vin4a_de0 vin3b_clk1 timer4 i2c3_scl dma_evt1 gpio2_22 Driver off

N1 gpmc_advn_alegpmc_cs6 clkout2 gpmc_wait1 vin4a_vsync0 gpmc_a2 gpmc_a23 timer3 i2c3_sda dma_evt2 gpio2_23 Driver off

M5 gpmc_oen_re

M3 gpmc_wen gpio2_25 Driver off

N6 gpmc_ben0 gpmc_cs4 vin1b_hsync1 vin3b_de1 timer2 dma_evt3 gpio2_26 Driver off

M4 gpmc_ben1 gpmc_cs5 vin1b_de1 vin3b_clk1 gpmc_a3 vin3b_fld1 timer1 dma_evt4 gpio2_27 Driver off

N2 gpmc_wait0 gpio2_28 Driver off

AG8 vin1a_clk0 vout3_d16 vout3_fld gpio2_30 Driver off

AH7 vin1b_clk1 vin3a_clk0 gpio2_31 Driver off

AD9 vin1a_de0 vin1b_hsync1 vout3_d17 vout3_de uart7_rxd timer16 spi3_sclk kbd_row0 eQEP1A_in gpio3_0 Driver off

AF9 vin1a_fld0 vin1b_vsync1 vout3_clk uart7_txd timer15 spi3_d1 kbd_row1 eQEP1B_in gpio3_1 Driver off

AE9 vin1a_hsync0 vin1b_fld1 vout3_hsync uart7_ctsn timer14 spi3_d0 eQEP1_index gpio3_2 Driver off

AF8 vin1a_vsync0 vin1b_de1 vout3_vsync uart7_rtsn timer13 spi3_cs0 eQEP1_strobegpio3_3 Driver off

AE8 vin1a_d0 vout3_d7 vout3_d23 uart8_rxd ehrpwm1A gpio3_4 Driver off

AD8 vin1a_d1 vout3_d6 vout3_d22 uart8_txd ehrpwm1B gpio3_5 Driver off

AG7 vin1a_d2 vout3_d5 vout3_d21 uart8_ctsn ehrpwm1_trip

AH6 vin1a_d3 vout3_d4 vout3_d20 uart8_rtsn eCAP1_in_P

AH3 vin1a_d4 vout3_d3 vout3_d19 ehrpwm1_syncigpio3_8 Driver off

AH5 vin1a_d5 vout3_d2 vout3_d18 ehrpwm1_syncogpio3_9 Driver off

0 1 2 3 4 5 6 7 8 9 10 14 15

n

Table 4-3. Multiplexing Characteristics (continued)

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

zone_input

WM1_out

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gpio2_24 Driver off

gpio3_6 Driver off

gpio3_7 Driver off

88

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ADDRESS REGISTER NAME

0x150C CTRL_CORE_PAD_V

0x1510 CTRL_CORE_PAD_V

0x1514 CTRL_CORE_PAD_V

0x1518 CTRL_CORE_PAD_V

0x151C CTRL_CORE_PAD_V

0x1520 CTRL_CORE_PAD_V

0x1524 CTRL_CORE_PAD_V

0x1528 CTRL_CORE_PAD_V

0x152C CTRL_CORE_PAD_V

0x1530 CTRL_CORE_PAD_V

0x1534 CTRL_CORE_PAD_V

0x1538 CTRL_CORE_PAD_V

0x153C CTRL_CORE_PAD_V

0x1540 CTRL_CORE_PAD_V

0x1544 CTRL_CORE_PAD_V

0x1548 CTRL_CORE_PAD_V

0x154C CTRL_CORE_PAD_V

0x1550 CTRL_CORE_PAD_V

0x1554 CTRL_CORE_PAD_V

0x1558 CTRL_CORE_PAD_V

0x155C CTRL_CORE_PAD_V

0x1560 CTRL_CORE_PAD_V

0x1564 CTRL_CORE_PAD_V

0x1568 CTRL_CORE_PAD_V

IN1A_D6

IN1A_D7

IN1A_D8

IN1A_D9

IN1A_D10

IN1A_D11

IN1A_D12

IN1A_D13

IN1A_D14

IN1A_D15

IN1A_D16

IN1A_D17

IN1A_D18

IN1A_D19

IN1A_D20

IN1A_D21

IN1A_D22

IN1A_D23

IN2A_CLK0

IN2A_DE0

IN2A_FLD0

IN2A_HSYNC0

IN2A_VSYNC0

IN2A_D0

DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-3. Multiplexing Characteristics (continued)

BALL

NUMBER

AG6 vin1a_d6 vout3_d1 vout3_d17 eQEP2A_in gpio3_10 Driver off

AH4 vin1a_d7 vout3_d0 vout3_d16 eQEP2B_in gpio3_11 Driver off

AG4 vin1a_d8 vin1b_d7 vout3_d15 kbd_row2 eQEP2_index gpio3_12 Driver off

AG2 vin1a_d9 vin1b_d6 vout3_d14 kbd_row3 eQEP2_strobegpio3_13 Driver off

AG3 vin1a_d10 vin1b_d5 vout3_d13 kbd_row4 gpio3_14 Driver off

AG5 vin1a_d11 vin1b_d4 vout3_d12 gpmc_a23 kbd_row5 gpio3_15 Driver off

AF2 vin1a_d12 vin1b_d3 usb3_ulpi_d7 vout3_d11 gpmc_a24 kbd_row6 gpio3_16 Driver off

AF6 vin1a_d13 vin1b_d2 usb3_ulpi_d6 vout3_d10 gpmc_a25 kbd_row7 gpio3_17 Driver off

AF3 vin1a_d14 vin1b_d1 usb3_ulpi_d5 vout3_d9 gpmc_a26 kbd_row8 gpio3_18 Driver off

AF4 vin1a_d15 vin1b_d0 usb3_ulpi_d4 vout3_d8 gpmc_a27 kbd_col0 gpio3_19 Driver off

AF1 vin1a_d16 vin1b_d7 usb3_ulpi_d3 vout3_d7 vin3a_d0 kbd_col1 gpio3_20 Driver off

AE3 vin1a_d17 vin1b_d6 usb3_ulpi_d2 vout3_d6 vin3a_d1 kbd_col2 gpio3_21 Driver off

AE5 vin1a_d18 vin1b_d5 usb3_ulpi_d1 vout3_d5 vin3a_d2 kbd_col3 gpio3_22 Driver off

AE1 vin1a_d19 vin1b_d4 usb3_ulpi_d0 vout3_d4 vin3a_d3 kbd_col4 gpio3_23 Driver off

AE2 vin1a_d20 vin1b_d3 usb3_ulpi_nxt vout3_d3 vin3a_d4 kbd_col5 gpio3_24 Driver off

AE6 vin1a_d21 vin1b_d2 usb3_ulpi_dir vout3_d2 vin3a_d5 kbd_col6 gpio3_25 Driver off

AD2 vin1a_d22 vin1b_d1 usb3_ulpi_stp vout3_d1 vin3a_d6 kbd_col7 gpio3_26 Driver off

AD3 vin1a_d23 vin1b_d0 usb3_ulpi_clk vout3_d0 vin3a_d7 kbd_col8 gpio3_27 Driver off

E1 vin2a_clk0 vout2_fld emu5 kbd_row0 eQEP1A_in gpio3_28 Driver off

G2 vin2a_de0 vin2a_fld0 vin2b_fld1 vin2b_de1 vout2_de emu6 kbd_row1 eQEP1B_in gpio3_29 Driver off

H7 vin2a_fld0 vin2b_clk1 vout2_clk emu7 eQEP1_index gpio3_30 Driver off

G1 vin2a_hsync0 vin2b_hsync1 vout2_hsync emu8 uart9_rxd spi4_sclk kbd_row2 eQEP1_strobegpio3_31 Driver off

G6 vin2a_vsync0 vin2b_vsync1 vout2_vsync emu9 uart9_txd spi4_d1 kbd_row3 ehrpwm1A gpio4_0 Driver off

F2 vin2a_d0 vout2_d23 emu10 uart9_ctsn spi4_d0 kbd_row4 ehrpwm1B gpio4_1 Driver off

0 1 2 3 4 5 6 7 8 9 10 14 15

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

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DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

ADDRESS REGISTER NAME

0x156C CTRL_CORE_PAD_V

0x1570 CTRL_CORE_PAD_V

0x1574 CTRL_CORE_PAD_V

0x1578 CTRL_CORE_PAD_V

0x157C CTRL_CORE_PAD_V

0x1580 CTRL_CORE_PAD_V

0x1584 CTRL_CORE_PAD_V

0x1588 CTRL_CORE_PAD_V

0x158C CTRL_CORE_PAD_V

0x1590 CTRL_CORE_PAD_V

0x1594 CTRL_CORE_PAD_V

0x1598 CTRL_CORE_PAD_V

0x159C CTRL_CORE_PAD_V

0x15A0 CTRL_CORE_PAD_V

0x15A4 CTRL_CORE_PAD_V

0x15A8 CTRL_CORE_PAD_V

0x15AC CTRL_CORE_PAD_V

0x15B0 CTRL_CORE_PAD_V

0x15B4 CTRL_CORE_PAD_V

0x15B8 CTRL_CORE_PAD_V

0x15BC CTRL_CORE_PAD_V

0x15C0 CTRL_CORE_PAD_V

0x15C4 CTRL_CORE_PAD_V

0x15C8 CTRL_CORE_PAD_V

IN2A_D1

IN2A_D2

IN2A_D3

IN2A_D4

IN2A_D5

IN2A_D6

IN2A_D7

IN2A_D8

IN2A_D9

IN2A_D10

IN2A_D11

IN2A_D12

IN2A_D13

IN2A_D14

IN2A_D15

IN2A_D16

IN2A_D17

IN2A_D18

IN2A_D19

IN2A_D20

IN2A_D21

IN2A_D22

IN2A_D23

OUT1_CLK

BALL

NUMBER

F3 vin2a_d1 vout2_d22 emu11 uart9_rtsn spi4_cs0 kbd_row5 ehrpwm1_trip

D1 vin2a_d2 vout2_d21 emu12 uart10_rxd kbd_row6 eCAP1_in_P

E2 vin2a_d3 vout2_d20 emu13 uart10_txd kbd_col0 ehrpwm1_syncigpio4_4 Driver off

D2 vin2a_d4 vout2_d19 emu14 uart10_ctsn kbd_col1 ehrpwm1_syncogpio4_5 Driver off

F4 vin2a_d5 vout2_d18 emu15 uart10_rtsn kbd_col2 eQEP2A_in gpio4_6 Driver off

C1 vin2a_d6 vout2_d17 emu16 mii1_rxd1 kbd_col3 eQEP2B_in gpio4_7 Driver off

E4 vin2a_d7 vout2_d16 emu17 mii1_rxd2 kbd_col4 eQEP2_index gpio4_8 Driver off

F5 vin2a_d8 vout2_d15 emu18 mii1_rxd3 kbd_col5 eQEP2_strobegpio4_9 Driver off

E6 vin2a_d9 vout2_d14 emu19 mii1_rxd0 kbd_col6 ehrpwm2A gpio4_10 Driver off

D3 vin2a_d10 mdio_mclk vout2_d13 kbd_col7 ehrpwm2B gpio4_11 Driver off

F6 vin2a_d11 mdio_d vout2_d12 kbd_row7 ehrpwm2_trip

D5 vin2a_d12 rgmii1_txc vout2_d11 mii1_rxclk kbd_col8 eCAP2_in_P

C2 vin2a_d13 rgmii1_txctl vout2_d10 mii1_rxdv kbd_row8 eQEP3A_in gpio4_14 Driver off

C3 vin2a_d14 rgmii1_txd3 vout2_d9 mii1_txclk eQEP3B_in gpio4_15 Driver off

C4 vin2a_d15 rgmii1_txd2 vout2_d8 mii1_txd0 eQEP3_index gpio4_16 Driver off

B2 vin2a_d16 vin2b_d7 rgmii1_txd1 vout2_d7 vin3a_d8 mii1_txd1 eQEP3_strobegpio4_24 Driver off

D6 vin2a_d17 vin2b_d6 rgmii1_txd0 vout2_d6 vin3a_d9 mii1_txd2 ehrpwm3A gpio4_25 Driver off

C5 vin2a_d18 vin2b_d5 rgmii1_rxc vout2_d5 vin3a_d10 mii1_txd3 ehrpwm3B gpio4_26 Driver off

A3 vin2a_d19 vin2b_d4 rgmii1_rxctl vout2_d4 vin3a_d11 mii1_txer ehrpwm3_trip

B3 vin2a_d20 vin2b_d3 rgmii1_rxd3 vout2_d3 vin3a_de0 vin3a_d12 mii1_rxer eCAP3_in_P

B4 vin2a_d21 vin2b_d2 rgmii1_rxd2 vout2_d2 vin3a_fld0 vin3a_d13 mii1_col gpio4_29 Driver off

B5 vin2a_d22 vin2b_d1 rgmii1_rxd1 vout2_d1 vin3a_hsync0 vin3a_d14 mii1_crs gpio4_30 Driver off

A4 vin2a_d23 vin2b_d0 rgmii1_rxd0 vout2_d0 vin3a_vsync0 vin3a_d15 mii1_txen gpio4_31 Driver off

D11 vout1_clk vin4a_fld0 vin3a_fld0 spi3_cs0 gpio4_19 Driver off

0 1 2 3 4 5 6 7 8 9 10 14 15

Table 4-3. Multiplexing Characteristics (continued)

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

zone_input

WM1_out

zone_input

WM2_out

zone_input

WM3_out

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gpio4_2 Driver off

gpio4_3 Driver off

gpio4_12 Driver off

gpio4_13 Driver off

gpio4_27 Driver off

gpio4_28 Driver off

90

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ADDRESS REGISTER NAME

0x15CC CTRL_CORE_PAD_V

0x15D0 CTRL_CORE_PAD_V

0x15D4 CTRL_CORE_PAD_V

0x15D8 CTRL_CORE_PAD_V

0x15DC CTRL_CORE_PAD_V

0x15E0 CTRL_CORE_PAD_V

0x15E4 CTRL_CORE_PAD_V

0x15E8 CTRL_CORE_PAD_V

0x15EC CTRL_CORE_PAD_V

0x15F0 CTRL_CORE_PAD_V

0x15F4 CTRL_CORE_PAD_V

0x15F8 CTRL_CORE_PAD_V

0x15FC CTRL_CORE_PAD_V

0x1600 CTRL_CORE_PAD_V

0x1604 CTRL_CORE_PAD_V

0x1608 CTRL_CORE_PAD_V

0x160C CTRL_CORE_PAD_V

0x1610 CTRL_CORE_PAD_V

0x1614 CTRL_CORE_PAD_V

0x1618 CTRL_CORE_PAD_V

0x161C CTRL_CORE_PAD_V

0x1620 CTRL_CORE_PAD_V

0x1624 CTRL_CORE_PAD_V

0x1628 CTRL_CORE_PAD_V

OUT1_DE

OUT1_FLD

OUT1_HSYNC

OUT1_VSYNC

OUT1_D0

OUT1_D1

OUT1_D2

OUT1_D3

OUT1_D4

OUT1_D5

OUT1_D6

OUT1_D7

OUT1_D8

OUT1_D9

OUT1_D10

OUT1_D11

OUT1_D12

OUT1_D13

OUT1_D14

OUT1_D15

OUT1_D16

OUT1_D17

OUT1_D18

OUT1_D19

DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-3. Multiplexing Characteristics (continued)

BALL

NUMBER

B10 vout1_de vin4a_de0 vin3a_de0 spi3_d1 gpio4_20 Driver off

B11 vout1_fld vin4a_clk0 vin3a_clk0 spi3_cs1 gpio4_21 Driver off

C11 vout1_hsync vin4a_hsync0 vin3a_hsync0 spi3_d0 gpio4_22 Driver off

E11 vout1_vsync vin4a_vsync0 vin3a_vsync0 spi3_sclk gpio4_23 Driver off

F11 vout1_d0 uart5_rxd vin4a_d16 vin3a_d16 spi3_cs2 gpio8_0 Driver off

G10 vout1_d1 uart5_txd vin4a_d17 vin3a_d17 gpio8_1 Driver off

F10 vout1_d2 emu2 vin4a_d18 vin3a_d18 obs0 obs16 obs_irq1 gpio8_2 Driver off

G11 vout1_d3 emu5 vin4a_d19 vin3a_d19 obs1 obs17 obs_dmarq1 gpio8_3 Driver off

E9 vout1_d4 emu6 vin4a_d20 vin3a_d20 obs2 obs18 gpio8_4 Driver off

F9 vout1_d5 emu7 vin4a_d21 vin3a_d21 obs3 obs19 gpio8_5 Driver off

F8 vout1_d6 emu8 vin4a_d22 vin3a_d22 obs4 obs20 gpio8_6 Driver off

E7 vout1_d7 emu9 vin4a_d23 vin3a_d23 gpio8_7 Driver off

E8 vout1_d8 uart6_rxd vin4a_d8 vin3a_d8 gpio8_8 Driver off

D9 vout1_d9 uart6_txd vin4a_d9 vin3a_d9 gpio8_9 Driver off

D7 vout1_d10 emu3 vin4a_d10 vin3a_d10 obs5 obs21 obs_irq2 gpio8_10 Driver off

D8 vout1_d11 emu10 vin4a_d11 vin3a_d11 obs6 obs22 obs_dmarq2 gpio8_11 Driver off

A5 vout1_d12 emu11 vin4a_d12 vin3a_d12 obs7 obs23 gpio8_12 Driver off

C6 vout1_d13 emu12 vin4a_d13 vin3a_d13 obs8 obs24 gpio8_13 Driver off

C8 vout1_d14 emu13 vin4a_d14 vin3a_d14 obs9 obs25 gpio8_14 Driver off

C7 vout1_d15 emu14 vin4a_d15 vin3a_d15 obs10 obs26 gpio8_15 Driver off

B7 vout1_d16 uart7_rxd vin4a_d0 vin3a_d0 gpio8_16 Driver off

B8 vout1_d17 uart7_txd vin4a_d1 vin3a_d1 gpio8_17 Driver off

A7 vout1_d18 emu4 vin4a_d2 vin3a_d2 obs11 obs27 gpio8_18 Driver off

A8 vout1_d19 emu15 vin4a_d3 vin3a_d3 obs12 obs28 gpio8_19 Driver off

0 1 2 3 4 5 6 7 8 9 10 14 15

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

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Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

91

DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

ADDRESS REGISTER NAME

0x162C CTRL_CORE_PAD_V

0x1630 CTRL_CORE_PAD_V

0x1634 CTRL_CORE_PAD_V

0x1638 CTRL_CORE_PAD_V

0x163C CTRL_CORE_PAD_

0x1640 CTRL_CORE_PAD_

0x1644 CTRL_CORE_PAD_R

0x1648 CTRL_CORE_PAD_U

0x164C CTRL_CORE_PAD_U

0x1650 CTRL_CORE_PAD_R

0x1654 CTRL_CORE_PAD_R

0x1658 CTRL_CORE_PAD_R

0x165C CTRL_CORE_PAD_R

0x1660 CTRL_CORE_PAD_R

0x1664 CTRL_CORE_PAD_R

0x1668 CTRL_CORE_PAD_R

0x166C CTRL_CORE_PAD_R

0x1670 CTRL_CORE_PAD_R

0x1674 CTRL_CORE_PAD_R

0x1678 CTRL_CORE_PAD_R

0x167C CTRL_CORE_PAD_R

0x1680 CTRL_CORE_PAD_U

0x1684 CTRL_CORE_PAD_U

0x1688 CTRL_CORE_PAD_

OUT1_D20

OUT1_D21

OUT1_D22

OUT1_D23

MDIO_MCLK

MDIO_D

MII_MHZ_50_CLK

ART3_RXD

ART3_TXD

GMII0_TXC

GMII0_TXCTL

GMII0_TXD3

GMII0_TXD2

GMII0_TXD1

GMII0_TXD0

GMII0_RXC

GMII0_RXCTL

GMII0_RXD3

GMII0_RXD2

GMII0_RXD1

GMII0_RXD0

SB1_DRVVBUS

SB2_DRVVBUS

GPIO6_14

BALL

NUMBER

C9 vout1_d20 emu16 vin4a_d4 vin3a_d4 obs13 obs29 gpio8_20 Driver off

A9 vout1_d21 emu17 vin4a_d5 vin3a_d5 obs14 obs30 gpio8_21 Driver off

B9 vout1_d22 emu18 vin4a_d6 vin3a_d6 obs15 obs31 gpio8_22 Driver off

A10 vout1_d23 emu19 vin4a_d7 vin3a_d7 spi3_cs3 gpio8_23 Driver off

V1 mdio_mclk uart3_rtsn mii0_col vin2a_clk0 vin4b_clk1 gpio5_15 Driver off

U4 mdio_d uart3_ctsn mii0_txer vin2a_d0 vin4b_d0 gpio5_16 Driver off

U3 RMII_MHZ_50

V2 uart3_rxd rmii1_crs mii0_rxdv vin2a_d1 vin4b_d1 spi3_sclk gpio5_18 Driver off

Y1 uart3_txd rmii1_rxer mii0_rxclk vin2a_d2 vin4b_d2 spi3_d1 spi4_cs1 gpio5_19 Driver off

W9 rgmii0_txc uart3_ctsn rmii1_rxd1 mii0_rxd3 vin2a_d3 vin4b_d3 usb4_ulpi_clk spi3_d0 spi4_cs2 gpio5_20 Driver off

V9 rgmii0_txctl uart3_rtsn rmii1_rxd0 mii0_rxd2 vin2a_d4 vin4b_d4 usb4_ulpi_stp spi3_cs0 spi4_cs3 gpio5_21 Driver off

V7 rgmii0_txd3 rmii0_crs mii0_crs vin2a_de0 vin4b_de1 usb4_ulpi_dir spi4_sclk uart4_rxd gpio5_22 Driver off

U7 rgmii0_txd2 rmii0_rxer mii0_rxer vin2a_hsync0 vin4b_hsync1 usb4_ulpi_nxt spi4_d1 uart4_txd gpio5_23 Driver off

V6 rgmii0_txd1 rmii0_rxd1 mii0_rxd1 vin2a_vsync0 vin4b_vsync1 usb4_ulpi_d0 spi4_d0 uart4_ctsn gpio5_24 Driver off

U6 rgmii0_txd0 rmii0_rxd0 mii0_rxd0 vin2a_d10 usb4_ulpi_d1 spi4_cs0 uart4_rtsn gpio5_25 Driver off

U5 rgmii0_rxc rmii1_txen mii0_txclk vin2a_d5 vin4b_d5 usb4_ulpi_d2 gpio5_26 Driver off

V5 rgmii0_rxctl rmii1_txd1 mii0_txd3 vin2a_d6 vin4b_d6 usb4_ulpi_d3 gpio5_27 Driver off

V4 rgmii0_rxd3 rmii1_txd0 mii0_txd2 vin2a_d7 vin4b_d7 usb4_ulpi_d4 gpio5_28 Driver off

V3 rgmii0_rxd2 rmii0_txen mii0_txen vin2a_d8 usb4_ulpi_d5 gpio5_29 Driver off

Y2 rgmii0_rxd1 rmii0_txd1 mii0_txd1 vin2a_d9 usb4_ulpi_d6 gpio5_30 Driver off

W2 rgmii0_rxd0 rmii0_txd0 mii0_txd0 vin2a_fld0 vin4b_fld1 usb4_ulpi_d7 gpio5_31 Driver off

AB10 usb1_drvvbus timer16 gpio6_12 Driver off

AC10 usb2_drvvbus timer15 gpio6_13 Driver off

E21 gpio6_14 mcasp1_axr8 dcan2_tx uart10_rxd vout2_hsync vin4a_hsync0 i2c3_sda timer1 gpio6_14 Driver off

0 1 2 3 4 5 6 7 8 9 10 14 15

_CLK

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Table 4-3. Multiplexing Characteristics (continued)

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

vin2a_d11 gpio5_17 Driver off

92

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ADDRESS REGISTER NAME

0x168C CTRL_CORE_PAD_

0x1690 CTRL_CORE_PAD_

0x1694 CTRL_CORE_PAD_X

0x1698 CTRL_CORE_PAD_X

0x169C CTRL_CORE_PAD_X

0x16A0 CTRL_CORE_PAD_X

0x16A4 CTRL_CORE_PAD_

0x16A8 CTRL_CORE_PAD_

0x16AC CTRL_CORE_PAD_

0x16B0 CTRL_CORE_PAD_

0x16B4 CTRL_CORE_PAD_

0x16B8 CTRL_CORE_PAD_

0x16BC CTRL_CORE_PAD_

0x16C0 CTRL_CORE_PAD_

0x16C4 CTRL_CORE_PAD_

0x16C8 CTRL_CORE_PAD_

0x16CC CTRL_CORE_PAD_

0x16D0 CTRL_CORE_PAD_

0x16D4 CTRL_CORE_PAD_

0x16D8 CTRL_CORE_PAD_

0x16DC CTRL_CORE_PAD_

0x16E0 CTRL_CORE_PAD_

0x16E4 CTRL_CORE_PAD_

0x16E8 CTRL_CORE_PAD_

GPIO6_15

GPIO6_16

REF_CLK0

REF_CLK1

REF_CLK2

REF_CLK3

MCASP1_ACLKX

MCASP1_FSX

MCASP1_ACLKR

MCASP1_FSR

MCASP1_AXR0

MCASP1_AXR1

MCASP1_AXR2

MCASP1_AXR3

MCASP1_AXR4

MCASP1_AXR5

MCASP1_AXR6

MCASP1_AXR7

MCASP1_AXR8

MCASP1_AXR9

MCASP1_AXR10

MCASP1_AXR11

MCASP1_AXR12

MCASP1_AXR13

DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-3. Multiplexing Characteristics (continued)

BALL

NUMBER

F20 gpio6_15 mcasp1_axr9 dcan2_rx uart10_txd vout2_vsync vin4a_vsync0 i2c3_scl timer2 gpio6_15 Driver off

F21 gpio6_16 mcasp1_axr1

D18 xref_clk0 mcasp2_axr8 mcasp1_axr4 mcasp1_ahclkxmcasp5_ahclkxatl_clk0 vin6a_d0 hdq0 clkout2 timer13 gpio6_17 Driver off

E17 xref_clk1 mcasp2_axr9 mcasp1_axr5 mcasp2_ahclkxmcasp6_ahclkxatl_clk1 vin6a_clk0 timer14 gpio6_18 Driver off

B26 xref_clk2 mcasp2_axr10mcasp1_axr6 mcasp3_ahclkxmcasp7_ahclkxatl_clk2 vout2_clk vin4a_clk0 timer15 gpio6_19 Driver off

C23 xref_clk3 mcasp2_axr11mcasp1_axr7 mcasp4_ahclkxmcasp8_ahclkxatl_clk3 vout2_de hdq0 vin4a_de0 clkout3 timer16 gpio6_20 Driver off

C14 mcasp1_aclkx vin6a_fld0 i2c3_sda gpio7_31 Driver off

D14 mcasp1_fsx vin6a_de0 i2c3_scl gpio7_30 Driver off

B14 mcasp1_aclkr mcasp7_axr2 vout2_d0 vin4a_d0 i2c4_sda gpio5_0 Driver off

J14 mcasp1_fsr mcasp7_axr3 vout2_d1 vin4a_d1 i2c4_scl gpio5_1 Driver off

G12 mcasp1_axr0 uart6_rxd vin6a_vsync0 i2c5_sda gpio5_2 Driver off

F12 mcasp1_axr1 uart6_txd vin6a_hsync0 i2c5_scl gpio5_3 Driver off

G13 mcasp1_axr2 mcasp6_axr2 uart6_ctsn vout2_d2 vin4a_d2 gpio5_4 Driver off

J11 mcasp1_axr3 mcasp6_axr3 uart6_rtsn vout2_d3 vin4a_d3 gpio5_5 Driver off

E12 mcasp1_axr4 mcasp4_axr2 vout2_d4 vin4a_d4 gpio5_6 Driver off

F13 mcasp1_axr5 mcasp4_axr3 vout2_d5 vin4a_d5 gpio5_7 Driver off

C12 mcasp1_axr6 mcasp5_axr2 vout2_d6 vin4a_d6 gpio5_8 Driver off

D12 mcasp1_axr7 mcasp5_axr3 vout2_d7 vin4a_d7 timer4 gpio5_9 Driver off

B12 mcasp1_axr8 mcasp6_axr0 spi3_sclk vin6a_d15 timer5 gpio5_10 Driver off

A11 mcasp1_axr9 mcasp6_axr1 spi3_d1 vin6a_d14 timer6 gpio5_11 Driver off

B13 mcasp1_axr10mcasp6_aclkx mcasp6_aclkr spi3_d0 vin6a_d13 timer7 gpio5_12 Driver off

A12 mcasp1_axr11mcasp6_fsx mcasp6_fsr spi3_cs0 vin6a_d12 timer8 gpio4_17 Driver off

E14 mcasp1_axr12mcasp7_axr0 spi3_cs1 vin6a_d11 timer9 gpio4_18 Driver off

A13 mcasp1_axr13mcasp7_axr1 vin6a_d10 timer10 gpio6_4 Driver off

0 1 2 3 4 5 6 7 8 9 10 14 15

0

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

vout2_fld vin4a_fld0 clkout1 timer3 gpio6_16 Driver off

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93

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SPRS950F –DECEMBER 2015–REVISED MAY 2019

ADDRESS REGISTER NAME

0x16EC CTRL_CORE_PAD_

0x16F0 CTRL_CORE_PAD_

0x16F4 CTRL_CORE_PAD_

0x16F8 CTRL_CORE_PAD_

0x16FC CTRL_CORE_PAD_

0x1700 CTRL_CORE_PAD_

0x1704 CTRL_CORE_PAD_

0x1708 CTRL_CORE_PAD_

0x170C CTRL_CORE_PAD_

0x1710 CTRL_CORE_PAD_

0x1714 CTRL_CORE_PAD_

0x1718 CTRL_CORE_PAD_

0x171C CTRL_CORE_PAD_

0x1720 CTRL_CORE_PAD_

0x1724 CTRL_CORE_PAD_

0x1728 CTRL_CORE_PAD_

0x172C CTRL_CORE_PAD_

0x1730 CTRL_CORE_PAD_

0x1734 CTRL_CORE_PAD_

0x1738 CTRL_CORE_PAD_

0x173C CTRL_CORE_PAD_

0x1740 CTRL_CORE_PAD_

0x1744 CTRL_CORE_PAD_

0x1748 CTRL_CORE_PAD_

MCASP1_AXR14

MCASP1_AXR15

MCASP2_ACLKX

MCASP2_FSX

MCASP2_ACLKR

MCASP2_FSR

MCASP2_AXR0

MCASP2_AXR1

MCASP2_AXR2

MCASP2_AXR3

MCASP2_AXR4

MCASP2_AXR5

MCASP2_AXR6

MCASP2_AXR7

MCASP3_ACLKX

MCASP3_FSX

MCASP3_AXR0

MCASP3_AXR1

MCASP4_ACLKX

MCASP4_FSX

MCASP4_AXR0

MCASP4_AXR1

MCASP5_ACLKX

MCASP5_FSX

BALL

NUMBER

G14 mcasp1_axr14mcasp7_aclkx mcasp7_aclkr vin6a_d9 timer11 gpio6_5 Driver off

F14 mcasp1_axr15mcasp7_fsx mcasp7_fsr vin6a_d8 timer12 gpio6_6 Driver off

A19 mcasp2_aclkx vin6a_d7 Driver off

A18 mcasp2_fsx vin6a_d6 Driver off

E15 mcasp2_aclkr mcasp8_axr2 vout2_d8 vin4a_d8 Driver off

A20 mcasp2_fsr mcasp8_axr3 vout2_d9 vin4a_d9 Driver off

B15 mcasp2_axr0 vout2_d10 vin4a_d10 Driver off

A15 mcasp2_axr1 vout2_d11 vin4a_d11 Driver off

C15 mcasp2_axr2 mcasp3_axr2 vin6a_d5 gpio6_8 Driver off

A16 mcasp2_axr3 mcasp3_axr3 vin6a_d4 gpio6_9 Driver off

D15 mcasp2_axr4 mcasp8_axr0 vout2_d12 vin4a_d12 gpio1_4 Driver off

B16 mcasp2_axr5 mcasp8_axr1 vout2_d13 vin4a_d13 gpio6_7 Driver off

B17 mcasp2_axr6 mcasp8_aclkx mcasp8_aclkr vout2_d14 vin4a_d14 gpio2_29 Driver off

A17 mcasp2_axr7 mcasp8_fsx mcasp8_fsr vout2_d15 vin4a_d15 gpio1_5 Driver off

B18 mcasp3_aclkx mcasp3_aclkr mcasp2_axr12uart7_rxd vin6a_d3 gpio5_13 Driver off

F15 mcasp3_fsx mcasp3_fsr mcasp2_axr13uart7_txd vin6a_d2 gpio5_14 Driver off

B19 mcasp3_axr0 mcasp2_axr14uart7_ctsn uart5_rxd vin6a_d1 Driver off

C17 mcasp3_axr1 mcasp2_axr15uart7_rtsn uart5_txd vin6a_d0 vin5a_fld0 Driver off

C18 mcasp4_aclkx mcasp4_aclkr spi3_sclk uart8_rxd i2c4_sda vout2_d16 vin4a_d16 vin5a_d15 Driver off

A21 mcasp4_fsx mcasp4_fsr spi3_d1 uart8_txd i2c4_scl vout2_d17 vin4a_d17 vin5a_d14 Driver off

G16 mcasp4_axr0 spi3_d0 uart8_ctsn uart4_rxd vout2_d18 vin4a_d18 vin5a_d13 Driver off

D17 mcasp4_axr1 spi3_cs0 uart8_rtsn uart4_txd vout2_d19 vin4a_d19 vin5a_d12 Driver off

AA3 mcasp5_aclkx mcasp5_aclkr spi4_sclk uart9_rxd i2c5_sda mlb_clk vout2_d20 vin4a_d20 vin5a_d11 Driver off

AB9 mcasp5_fsx mcasp5_fsr spi4_d1 uart9_txd i2c5_scl vout2_d21 vin4a_d21 vin5a_d10 Driver off

0 1 2 3 4 5 6 7 8 9 10 14 15

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Table 4-3. Multiplexing Characteristics (continued)

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

94

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ADDRESS REGISTER NAME

0x174C CTRL_CORE_PAD_

0x1750 CTRL_CORE_PAD_

0x1754 CTRL_CORE_PAD_

0x1758 CTRL_CORE_PAD_

0x175C CTRL_CORE_PAD_

0x1760 CTRL_CORE_PAD_

0x1764 CTRL_CORE_PAD_

0x1768 CTRL_CORE_PAD_

0x176C CTRL_CORE_PAD_

0x1770 CTRL_CORE_PAD_

0x1774 CTRL_CORE_PAD_

0x1778 CTRL_CORE_PAD_

0x177C CTRL_CORE_PAD_

0x1780 CTRL_CORE_PAD_

0x1784 CTRL_CORE_PAD_

0x1788 CTRL_CORE_PAD_

0x178C CTRL_CORE_PAD_

0x1790 CTRL_CORE_PAD_

0x1794 CTRL_CORE_PAD_

0x1798 CTRL_CORE_PAD_

0x179C CTRL_CORE_PAD_

0x17A0 CTRL_CORE_PAD_

0x17A4 CTRL_CORE_PAD_S

0x17A8 CTRL_CORE_PAD_S

MCASP5_AXR0

MCASP5_AXR1

MMC1_CLK

MMC1_CMD

MMC1_DAT0

MMC1_DAT1

MMC1_DAT2

MMC1_DAT3

MMC1_SDCD

MMC1_SDWP

GPIO6_10

GPIO6_11

MMC3_CLK

MMC3_CMD

MMC3_DAT0

MMC3_DAT1

MMC3_DAT2

MMC3_DAT3

MMC3_DAT4

MMC3_DAT5

MMC3_DAT6

MMC3_DAT7

PI1_SCLK

PI1_D1

DRA756,DRA755,DRA754,DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-3. Multiplexing Characteristics (continued)

BALL

NUMBER

AB3 mcasp5_axr0 spi4_d0 uart9_ctsn uart3_rxd mlb_sig vout2_d22 vin4a_d22 vin5a_d9 Driver off

AA4 mcasp5_axr1 spi4_cs0 uart9_rtsn uart3_txd mlb_dat vout2_d23 vin4a_d23 vin5a_d8 Driver off

W6 mmc1_clk gpio6_21 Driver off

Y6 mmc1_cmd gpio6_22 Driver off

AA6 mmc1_dat0 gpio6_23 Driver off

Y4 mmc1_dat1 gpio6_24 Driver off

AA5 mmc1_dat2 gpio6_25 Driver off

Y3 mmc1_dat3 gpio6_26 Driver off

W7 mmc1_sdcd uart6_rxd i2c4_sda gpio6_27 Driver off

Y9 mmc1_sdwp uart6_txd i2c4_scl gpio6_28 Driver off

AC5 gpio6_10 mdio_mclk i2c3_sda usb3_ulpi_d7 vin2b_hsync1 vin5a_clk0 ehrpwm2A gpio6_10 Driver off

AB4 gpio6_11 mdio_d i2c3_scl usb3_ulpi_d6 vin2b_vsync1 vin5a_de0 ehrpwm2B gpio6_11 Driver off

AD4 mmc3_clk usb3_ulpi_d5 vin2b_d7 vin5a_d7 ehrpwm2_trip

AC4 mmc3_cmd spi3_sclk usb3_ulpi_d4 vin2b_d6 vin5a_d6 eCAP2_in_P

AC7 mmc3_dat0 spi3_d1 uart5_rxd usb3_ulpi_d3 vin2b_d5 vin5a_d5 eQEP3A_in gpio6_31 Driver off

AC6 mmc3_dat1 spi3_d0 uart5_txd usb3_ulpi_d2 vin2b_d4 vin5a_d4 eQEP3B_in gpio7_0 Driver off

AC9 mmc3_dat2 spi3_cs0 uart5_ctsn usb3_ulpi_d1 vin2b_d3 vin5a_d3 eQEP3_index gpio7_1 Driver off

AC3 mmc3_dat3 spi3_cs1 uart5_rtsn usb3_ulpi_d0 vin2b_d2 vin5a_d2 eQEP3_strobegpio7_2 Driver off

AC8 mmc3_dat4 spi4_sclk uart10_rxd usb3_ulpi_nxt vin2b_d1 vin5a_d1 ehrpwm3A gpio1_22 Driver off

AD6 mmc3_dat5 spi4_d1 uart10_txd usb3_ulpi_dir vin2b_d0 vin5a_d0 ehrpwm3B gpio1_23 Driver off

AB8 mmc3_dat6 spi4_d0 uart10_ctsn usb3_ulpi_stp vin2b_de1 vin5a_hsync0 ehrpwm3_trip

AB5 mmc3_dat7 spi4_cs0 uart10_rtsn usb3_ulpi_clk vin2b_clk1 vin5a_vsync0 eCAP3_in_P

A25 spi1_sclk gpio7_7 Driver off

F16 spi1_d1 gpio7_8 Driver off

0 1 2 3 4 5 6 7 8 9 10 14 15

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

zone_input

WM2_out

zone_input

WM3_out

gpio6_29 Driver off

gpio6_30 Driver off

gpio1_24 Driver off

gpio1_25 Driver off

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95

DRA756,DRA755,DRA754,DRA752 DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F –DECEMBER 2015–REVISED MAY 2019

ADDRESS REGISTER NAME

0x17AC CTRL_CORE_PAD_S

0x17B0 CTRL_CORE_PAD_S

0x17B4 CTRL_CORE_PAD_S

0x17B8 CTRL_CORE_PAD_S

0x17BC CTRL_CORE_PAD_S

0x17C0 CTRL_CORE_PAD_S

0x17C4 CTRL_CORE_PAD_S

0x17C8 CTRL_CORE_PAD_S

0x17CC CTRL_CORE_PAD_S

0x17D0 CTRL_CORE_PAD_D

0x17D4 CTRL_CORE_PAD_D

0x17E0 CTRL_CORE_PAD_U

0x17E4 CTRL_CORE_PAD_U

0x17E8 CTRL_CORE_PAD_U

0x17EC CTRL_CORE_PAD_U

0x17F0 CTRL_CORE_PAD_U

0x17F4 CTRL_CORE_PAD_U

0x17F8 CTRL_CORE_PAD_U

0x17FC CTRL_CORE_PAD_U

0x1800 CTRL_CORE_PAD_I

0x1804 CTRL_CORE_PAD_I

0x1808 CTRL_CORE_PAD_I

0x180C CTRL_CORE_PAD_I

0x1818 CTRL_CORE_PAD_

PI1_D0

PI1_CS0

PI1_CS1

PI1_CS2

PI1_CS3

PI2_SCLK

PI2_D1

PI2_D0

PI2_CS0

CAN1_TX

CAN1_RX

ART1_RXD

ART1_TXD

ART1_CTSN

ART1_RTSN

ART2_RXD

ART2_TXD

ART2_CTSN

ART2_RTSN

2C1_SDA

2C1_SCL

2C2_SDA

2C2_SCL

WAKEUP0

BALL

NUMBER

B25 spi1_d0 gpio7_9 Driver off

A24 spi1_cs0 gpio7_10 Driver off

A22 spi1_cs1 sata1_led spi2_cs1 gpio7_11 Driver off

B21 spi1_cs2 uart4_rxd mmc3_sdcd spi2_cs2 dcan2_tx mdio_mclk hdmi1_hpd gpio7_12 Driver off

B20 spi1_cs3 uart4_txd mmc3_sdwp spi2_cs3 dcan2_rx mdio_d hdmi1_cec gpio7_13 Driver off

A26 spi2_sclk uart3_rxd gpio7_14 Driver off

B22 spi2_d1 uart3_txd gpio7_15 Driver off

G17 spi2_d0 uart3_ctsn uart5_rxd gpio7_16 Driver off

B24 spi2_cs0 uart3_rtsn uart5_txd gpio7_17 Driver off

G20 dcan1_tx uart8_rxd mmc2_sdcd hdmi1_hpd gpio1_14 Driver off

G19 dcan1_rx uart8_txd mmc2_sdwp sata1_led hdmi1_cec gpio1_15 Driver off

B27 uart1_rxd mmc4_sdcd gpio7_22 Driver off

C26 uart1_txd mmc4_sdwp gpio7_23 Driver off

E25 uart1_ctsn uart9_rxd mmc4_clk gpio7_24 Driver off

C27 uart1_rtsn uart9_txd mmc4_cmd gpio7_25 Driver off

D28 uart3_ctsn uart3_rctx mmc4_dat0 uart2_rxd uart1_dcdn gpio7_26 Driver off

D26 uart2_txd uart3_rtsn uart3_sd mmc4_dat1 uart2_txd uart1_dsrn gpio7_27 Driver off

D27 uart2_ctsn uart3_rxd mmc4_dat2 uart10_rxd uart1_dtrn gpio1_16 Driver off

C28 uart2_rtsn uart3_txd uart3_irtx mmc4_dat3 uart10_txd uart1_rin gpio1_17 Driver off

C21 i2c1_sda

C20 i2c1_scl

C25 i2c2_sda hdmi1_ddc_sc

F17 i2c2_scl hdmi1_ddc_sd

AD17 Wakeup0 dcan1_rx gpio1_0 Driver off

0 1 2 3 4 5 6 7 8 9 10 14 15

l

a

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Table 4-3. Multiplexing Characteristics (continued)

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

Driver off

96

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SPRS950F –DECEMBER 2015–REVISED MAY 2019

Table 4-3. Multiplexing Characteristics (continued)

ADDRESS REGISTER NAME

0x181C CTRL_CORE_PAD_

0x1820 CTRL_CORE_PAD_

0x1824 CTRL_CORE_PAD_

0x1828 CTRL_CORE_PAD_

0x182C CTRL_CORE_PAD_R

0x1830 CTRL_CORE_PAD_TMSF18 tms

0x1834 CTRL_CORE_PAD_TDID23 tdi gpio8_27

0x1838 CTRL_CORE_PAD_TDOF19 tdo gpio8_28

WAKEUP1

WAKEUP2

WAKEUP3

ON_OFF

TC_PORZ

BALL

NUMBER

AC17 Wakeup1 dcan2_rx gpio1_1 Driver off

AB16 Wakeup2 sys_nirq2 gpio1_2 Driver off

AC16 Wakeup3 sys_nirq1 gpio1_3 Driver off

Y11 on_off

AB17 rtc_porz

0 1 2 3 4 5 6 7 8 9 10 14 15

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

0x183C CTRL_CORE_PAD_T

0x1840 CTRL_CORE_PAD_T

0x1844 CTRL_CORE_PAD_R

0x1848 CTRL_CORE_PAD_E

0x184C CTRL_CORE_PAD_E

0x185C CTRL_CORE_PAD_R

0x1860 CTRL_CORE_PAD_N

0x1864 CTRL_CORE_PAD_R

CLK

RSTN

TCK

MU0

MU1

ESETN

MIN_DSP

STOUTN

E20 tclk

D20 trstn

E18 rtck gpio8_29

G21 emu0 gpio8_30

D24 emu1 gpio8_31

E23 resetn

D21 nmin_dsp

F23 rstoutn

1. NA in table stands for Not Applicable.

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4.4 Signal Descriptions

Many signals are available on multiple pins, according to the software configuration of the pin multiplexing options.

1. SIGNAL NAME: The name of the signal passing through the pin.

The subsystem multiplexing signals are not described in Table 4-2 and Table 4-3.

2. DESCRIPTION: Description of the signal

3. TYPE: Signal direction and type: – I = Input

– O = Output – IO = Input or output – D = Open Drain – DS = Differential – A = Analog – PWR = Power – GND = Ground

4. BALL: Associated ball(s) bottom

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NOTE

For more information, see the Control Module / Control Module Register Manual section of the device TRM.

4.4.1 Video Input Ports (VIP)

NOTE

For more information, see the Video Input Port (VIP) section of the device TRM.

CAUTION

The I/O timings provided in Section 7, Timing Requirements and Switching Characteristics are applicable for all combinations of signals for vin1, vin5 and

vin6. However, the timings are only valid for vin2, vin3, and vin4 if signals within a single IOSET are used. The IOSETs are defined in the Table 7-4, Table 7-5 and Table 7-6.

Table 4-4. VIP Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL

Video Input 1

vin1a_clk0 Video Input 1 Port A Clock input.Input clock for 8-bit 16-bit or 24-bit Port A video

vin1a_de0 Video Input 1 Data Enable input

vin1a_fld0 Video Input 1 Port A Field ID input vin1a_hsync0 Video Input 1 Port A Horizontal Sync input vin1a_vsync0 Video Input 1 Port A Vertical Sync input

vin1a_d0 Video Input 1 Port A Data input vin1a_d1 Video Input 1 Port A Data input vin1a_d2 Video Input 1 Port A Data input

capture. Input data is sampled on the CLK0 edge.

(1)

(1) (1) (1) (1)

I AG8

I AD9 I AF9 I AE9 I AF8 I AE8 I AD8 I AG7

98

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Table 4-4. VIP Signal Descriptions (continued)

SIGNAL NAME DESCRIPTION TYPE BALL

vin1a_d3 Video Input 1 Port A Data input vin1a_d4 Video Input 1 Port A Data input vin1a_d5 Video Input 1 Port A Data input vin1a_d6 Video Input 1 Port A Data input vin1a_d7 Video Input 1 Port A Data input vin1a_d8 Video Input 1 Port A Data input

vin1a_d9 Video Input 1 Port A Data input vin1a_d10 Video Input 1 Port A Data input vin1a_d11 Video Input 1 Port A Data input vin1a_d12 Video Input 1 Port A Data input vin1a_d13 Video Input 1 Port A Data input vin1a_d14 Video Input 1 Port A Data input vin1a_d15 Video Input 1 Port A Data input vin1a_d16 Video Input 1 Port A Data input vin1a_d17 Video Input 1 Port A Data input vin1a_d18 Video Input 1 Port A Data input vin1a_d19 Video Input 1 Port A Data input vin1a_d20 Video Input 1 Port A Data input vin1a_d21 Video Input 1 Port A Data input vin1a_d22 Video Input 1 Port A Data input vin1a_d23 Video Input 1 Port A Data input

vin1b_hsync1 Video Input 1 Port B Horizontal Sync input vin1b_vsync1 Video Input 1 Port B Vertical Sync input

vin1b_fld1 Video Input 1 Port B Field ID input vin1b_de1 Video Input 1 Port B Data Enable input vin1b_clk1 Video Input 1 Port B Clock input

vin1b_d0 Video Input 1 Port B Data input

vin1b_d1 Video Input 1 Port B Data input

vin1b_d2 Video Input 1 Port B Data input

vin1b_d3 Video Input 1 Port B Data input

vin1b_d4 Video Input 1 Port B Data input

vin1b_d5 Video Input 1 Port B Data input

vin1b_d6 Video Input 1 Port B Data input

vin1b_d7 Video Input 1 Port B Data input

Video Input 2

vin2a_clk0 Video Input 2 Port A Clock input. I E1 / V1 vin2a_de0 Video Input 2 Port A Data Enable input I G2 / V7 vin2a_fld0 Video Input 2 Port A Field ID input I H7 / G2 / W2

vin2a_hsync0 Video Input 2 Port A Horizontal Sync input I G1 / U7 vin2a_vsync0 Video Input 2 Port A Vertical Sync input I G6 / V6

vin2a_d0 Video Input 2 Port A Data input I F2 / U4

vin2a_d1 Video Input 2 Port A Data input I F3 / V2

vin2a_d2 Video Input 2 Port A Data input I D1 / Y1

vin2a_d3 Video Input 2 Port A Data input I E2 / W9

vin2a_d4 Video Input 2 Port A Data input I D2 / V9

vin2a_d5 Video Input 2 Port A Data input I F4 / U5

vin2a_d6 Video Input 2 Port A Data input I C1 / V5

(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)

(1)

(1) (1) (1) (1) (1) (1) (1) (1) (1)

I AH6 I AH3 I AH5 I AG6 I AH4 I AG4 I AG2 I AG3 I AG5 I AF2 I AF6 I AF3 I AF4 I AF1 I AE3 I AE5 I AE1 I AE2 I AE6 I AD2 I AD3 I N6 / AD9 I AF9 I AE9 I AF8 / M4 I AH7 I AF4 / AD3 I AF3 / AD2 I AF6 / AE6 I AF2 / AE2 I AG5 / AE1 I AG3 / AE5 I AG2 / AE3 I AG4 / AF1

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Table 4-4. VIP Signal Descriptions (continued)

SIGNAL NAME DESCRIPTION TYPE BALL

vin2a_d7 Video Input 2 Port A Data input I E4 / V4 vin2a_d8 Video Input 2 Port A Data input I F5 / V3

vin2a_d9 Video Input 2 Port A Data input I E6 / Y2 vin2a_d10 Video Input 2 Port A Data input I D3 / U6 vin2a_d11 Video Input 2 Port A Data input I F6 / U3 vin2a_d12 Video Input 2 Port A Data input I D5 vin2a_d13 Video Input 2 Port A Data input I C2 vin2a_d14 Video Input 2 Port A Data input I C3 vin2a_d15 Video Input 2 Port A Data input I C4 vin2a_d16 Video Input 2 Port A Data input I B2 vin2a_d17 Video Input 2 Port A Data input I D6 vin2a_d18 Video Input 2 Port A Data input I C5 vin2a_d19 Video Input 2 Port A Data input I A3 vin2a_d20 Video Input 2 Port A Data input I B3 vin2a_d21 Video Input 2 Port A Data input I B4 vin2a_d22 Video Input 2 Port A Data input I B5 vin2a_d23 Video Input 2 Port A Data input I A4 vin2b_clk1 Video Input 2 Port B Clock input I AB5 / H7 vin2b_de1 Video Input 2 Port B Data Enable input I AB8 / G2 vin2b_fld1 Video Input 2 Port B Field ID input I G2

vin2b_hsync1 Video Input 2 Port B Horizontal Sync input I AC5 / G1 vin2b_vsync1 Video Input 2 Port B Vertical Sync input I AB4 / G6

vin2b_d0 Video Input 2 Port B Data input I AD6 / A4

vin2b_d1 Video Input 2 Port B Data input I AC8 / B5

vin2b_d2 Video Input 2 Port B Data input I AC3 / B4

vin2b_d3 Video Input 2 Port B Data input I AC9 / B3

vin2b_d4 Video Input 2 Port B Data input I AC6 / A3

vin2b_d5 Video Input 2 Port B Data input I AC7 / C5

vin2b_d6 Video Input 2 Port B Data input I AC4 / D6

vin2b_d7 Video Input 2 Port B Data input I AD4 / B2

Video Input 3

vin3a_clk0 Video Input 3 Port A Clock input I B11 / AH7 / P1 vin3a_de0 Video Input 3 Port A Data Enable input I N9 / B3 / B10 vin3a_fld0 Video Input 3 Port A Field ID input I P9 / B4 / D11

vin3a_hsync0 Video Input 3 Port A Horizontal Sync input I N7 / B5 / C11 vin3a_vsync0 Video Input 3 Port A Vertical Sync input I R4 / A4 / E11

vin3a_d0 Video Input 3 Port A Data input I M6 / AF1 / B7

vin3a_d1 Video Input 3 Port A Data input I M2 / AE3 / B8

vin3a_d2 Video Input 3 Port A Data input I L5 / AE5 / A7

vin3a_d3 Video Input 3 Port A Data input I M1 / AE1 / A8

vin3a_d4 Video Input 3 Port A Data input I L6 / AE2 / C9

vin3a_d5 Video Input 3 Port A Data input I L4 / AE6 / A9

vin3a_d6 Video Input 3 Port A Data input I L3 / AD2 / B9

vin3a_d7 Video Input 3 Port A Data input I L2 / AD3 / A10

vin3a_d8 Video Input 3 Port A Data input I L1 / B2 / E8

vin3a_d9 Video Input 3 Port A Data input I K2 / D6 / D9 vin3a_d10 Video Input 3 Port A Data input I J1 / C5 / D7

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Datasheet DRA756, DRA755, DRA754, DRA752, DRA751 Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Device Overview

1.1 Features

1.2 Applications

1.3 Description

1.4 Functional Block Diagram

Table of Contents

2 Revision History

3 Device Comparison

3.1 Related Products

4 Terminal Configuration and Functions

4.1 Terminal Assignment

4.1.1 Unused Balls Connection Requirements

4.2 Ball Characteristics

4.3 Multiplexing Characteristics

4.4 Signal Descriptions

4.4.1 Video Input Ports (VIP)