TEXAS INSTRUMENTS DDC112 Technical data

®

D

D

C1

12

D

®

D

C

11

2

SBAS085B – JANUARY 2000 – REVISED OCTOBER 2004

Dual Current Input 20-Bit

ANALOG-TO-DIGITAL CONVERTER

DDC112

FEATURES

● MONOLITHIC CHARGE MEASUREMENT A/D

CONVERTER

● DIGITAL FILTER NOISE REDUCTION:

3.2ppm, rms

● INTEGRAL LINEARITY:

±0.005% Reading ±0.5ppm FSR

● HIGH PRECISION, TRUE INTEGRATING FUNC-

TION

● PROGRAMMABLE FULL-SCALE

● SINGLE SUPPLY

● CASCADABLE OUTPUT

APPLICATIONS

● DIRECT PHOTOSENSOR DIGITIZATION

● CT SCANNER DAS

● INFRARED PYROMETER

● PRECISION PROCESS CONTROL

● LIQUID/GAS CHROMATOGRAPHY

● BLOOD ANALYSIS

Protected by US Patent #5841310

DESCRIPTION

The DDC112 is a dual input, wide dynamic range, charge­digitizing analog-to-digital (A/D) converter with 20-bit resolu­tion. Low-level current output devices, such as photosensors,
can be directly connected to its inputs. Charge integration is
continuous as each input uses two integrators; while one is
being digitized, the other is integrating.

For each of its two inputs, the DDC112 combines current-to­voltage conversion, continuous integration, programmable
full-scale range, A/D conversion, and digital filtering to achieve
a precision, wide dynamic range digital result. In addition to
the internal programmable full-scale ranges, external integrat­ing capacitors allow an additional user-settable full-scale
range of up to 1000pC.

To provide single-supply operation, the internal A/D converter
utilizes a differential input, with the positive input tied to V
When the integration capacitor is reset at the beginning of
each integration cycle, the capacitor charges to V
charge is removed in proportion to the input current. At the
end of the integration cycle, the remaining voltage is com­pared to V

REF

.

The high-speed serial shift register which holds the result of
the last conversion can be configured to allow multiple DDC112
units to be cascaded, minimizing interconnections. The
DDC112 is available in an SO-28 or TQFP-32 package and is
offered in two performance grades.

REF

REF

. This

.

AGNDAV

DD

CAP1A
CAP1A

IN1

CAP1B
CAP1B

CAP2A
CAP2A

IN2

CAP2B
CAP2B

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

CHANNEL 1

Dual

Switched

Integrator

CHANNEL 2

Dual

Switched

Integrator

V

REF

∆Σ

Modulator

www.ti.com

Digital

Filter

TEST

DGNDDV

DD

DCLK

DVALID

Digital

Input/Output

Control

CLK

CONV

Copyright © 2000-2004, Texas Instruments Incorporated

DXMIT
DOUT
DIN

RANGE2
RANGE1
RANGE0

ABSOLUTE MAXIMUM RATINGS

AVDD to DVDD.......................................................................–0.3V to +6V

AV

to AGND ..................................................................... –0.3V to +6V

DD

DV

to DGND ..................................................................... –0.3V to +6V

DD

AGND to DGND ............................................................................... ±0.3V

V

Voltage to AGND ........................................... –0.3V to AVDD + 0.3V

REF

Digital Input Voltage to DGND .............................. –0.3V to DV

Digital Output Voltage to DGND ........................... –0.3V to DV

Package Power Dissipation ............................................. (T

Maximum Junction Temperature (T
Thermal Resistance, SO,
Thermal Resistance, TQFP,

Lead Temperature (soldering, 10s)............................................... +300°C

NOTE: (1) Stresses above those listed under
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

JMAX

θ

....................................................+150°C/W

JA

θ

................................................+100°C/W

JA

(1)

+ 0.3V

DD

+ 0.3V

DD

– TA)/

) ...................................... +150°C

Absolute Maximum Ratings

JMAX

θ

may

JA

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru­ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE/ORDERING INFORMATION

MAXIMUM SPECIFICATION

PRODUCT LINEARITY ERROR RANGE PACKAGE-LEAD DESIGNATOR NUMBER

DDC112U

INTEGRAL TEMPERATURE PACKAGE ORDERING TRANSPORT

±0.025% Reading ±1.0ppm FSR

(1)

(2)

–40°C to +85°C SO-28 DW DDC112U Rails

MEDIA

"""""DDC112U/1K Tape and Reel

DDC112UK

±0.025% Reading ±1.0ppm FSR

0°C to +70°C SO-28 DW DDC112UK Rails

"""""DDC112UK/1K Tape and Reel

DDC112Y ±0.025% Reading ±1.0ppm FSR –40°C to +85°C TQFP-32 PJT DDC112Y/250 Tape and Reel

"""""DDC112Y/2K Tape and Reel

DDC112YK ±0.025% Reading ±1.0ppm FSR 0°C to +70°C TQFP-32 PJT DDC112YK/250 Tape and Reel

"""""DDC112YK/2K Tape and Reel

NOTES: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data shee t. (2) Models with a slash
(/) are available only in Tape and Reel in the quantities indicated (/1K indicates 1000 devices per reel). Ordering 1000 pieces of
piece Tape and Reel.

DDC112U/1K

will get a single 1000-

2

www.ti.com

DDC112

SBAS085B

ELECTRICAL CHARACTERISTICS

At TA = +25°C, AVDD = DVDD = +5V, DDC112U, Y: T
operation, and internal integration capacitors, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ANALOG INPUTS

External, Positive Full-Scale

Range 0 C

Internal, Positive Full-Scale

Range 1 47.5 50 52.5 ✻✻✻ pC
Range 2 95 100 105 ✻✻✻ pC
Range 3 142.5 150 157.5 ✻✻✻ pC
Range 4 190 200 210 ✻✻✻ pC
Range 5 237.5 250 262.5 ✻✻✻ pC
Range 6 285 300 315 ✻✻✻ pC
Range 7 332.5 350 367.5 ✻✻✻ pC

Negative Full-Scale Input –0.4% of Positive FS ✻ pC

DYNAMIC CHARACTERISTICS

Conversion Rate 2 3 kHz
Integration Time, T
Integration Time, T
System Clock Input (CLK) 1 10 12 ✻✻15 MHz

INT
INT

Non-Continuous Mode 50 ✻ µs

Data Clock (DCLK) 12 15 MHz

ACCURACY

Noise, Low-Level Current Input

Differential Linearity Error ±0.005% Reading ±0.5ppm
Integral Linearity Error

(1)

C

SENSOR

C

SENSOR

C

SENSOR

(4)

No Missing Codes 20 ✻ Bits
Input Bias Current T
Range Error Range 5 (250pC) 5 ✻ % of FSR
Range Error Match
Range Sensitivity to V
Offset Error Range 5, (250pC) ±200 ✻ ±600 ppm of FSR
Offset Error Match
DC Bias Voltage

(5)

REF

(5)

(6)

(Input VOS) ±0.05 ±2 ✻✻ mV

V

Power-Supply Rejection Ratio ±25 ±200 ✻✻ppm of FSR/V
Internal Test Signal 13 ✻ pC
Internal Test Accuracy ±10 ✻ %

PERFORMANCE OVER TEMPERATURE

Offset Drift ±0.5 ±3
Offset Drift Stability ±0.2 ✻ ±0.7
DC Bias Voltage Drift Applied to Sensor Input 3 ±1 µV/°C
Input Bias Current Drift +25°C to +45°C 0.01 1
Input Bias Current T
Range Drift
Range Drift Match

(7)

(5)

REFERENCE

Voltage 4.000 4.096 4.200 ✻✻✻ V
Input Current

(8)

DIGITAL INPUT/OUTPUT

Logic Levels

V

IH

V

IL

V

OH

V

OL

Input Current, I
Data Format

IN

(9)

POWER-SUPPLY REQUIREMENTS

Power-Supply Voltage AV
Supply Current

Analog Current AV
Digital Current DV

Total Power Dissipation 80 100 85 130 mW

TEMPERATURE RANGE

Specified Performance –40 +85 0 +70 °C
Storage –60 +100 ✻✻°C

✻ Specifications same as DDC112U, Y.
NOTES: (1) Input is less than 1% of full scale. (2) C
(4) A best-fit line is used in measuring linearity. (5) Matching between side A and side B, not input 1 to input 2. (6) Voltage produced by the DDC112 at its input which
is applied to the sensor. (7) Range drift does not include external reference drift. (8) Input reference current decreases with increasing T
section). (9) Data format is Straight Binary with a small offset (see the

= 500µs, CLK = 10MHz, DDC112UK, YK: T

INT

= 333.3µs, CLK = 15MHz, V

INT

= +4.096V, continuous mode

REF

DDC112U, Y DDC112UK, YK

= 250pF 1000 ✻ pC

EXT

Continuous Mode 500 1,000,000 333.3 ✻ µs

(2)

= 0pF, Range 5 (250pC) 3.2 ✻

ppm of FSR

(3)

, rms
= 25pF, Range 5 (250pC) 3.8 ✻ ppm of FSR, rms
= 50pF, Range 5 (250pC) 4.2 6.0 ✻ 7 ppm of FSR, rms

FSR (max) ✻

±0.005% Reading ±0.5ppm

FSR (typ) ✻

±0.025% Reading ±1.0ppm

FSR (max) ✻

= +25°C 0.1 10 ✻✻ pA

A

All Ranges 0.1 0.5 ✻✻% of FSR

= 4.096 ±0.1V 1:1 ✻

REF

±100 ✻ ppm of FSR

(10)

ppm of FSR/°C

(10)

ppm of FSR/minute

(10)

= +75°C250

A

Range 5 (250pC) 25 0 25 50

(10)

✻✻ pA/°C
✻✻ pA

(10)

ppm/°C

Range 5 (250pC) ±0.05 ✻ ppm/°C

T

= 500µs 150 225 275 µA

INT

4.0

–0.3 +0.8 ✻✻V

DV

DD

+ 0.3

✻✻V

IOH = –500µA 4.5 ✻ V

IOL = 500µA 0.4 ✻ V

–10 +10 ✻✻µA

Straight Binary ✻

and DV

DD

DD

= +5V 14.8 15.2 mA

DD

= +5V 1.2 1.8 mA

DD

is the capacitance seen at the DDC112 inputs from wiring, photodiode, etc. (3) FSR is Full-Scale Range.

SENSOR

4.75 5.25 ✻✻V

Data Retrieval

section). (10) Ensured by design but not production tested.

INT

(see the

Voltage Reference

DDC112

SBAS085B

www.ti.com

3

PIN CONFIGURATION

Top View SO

IN1

AGND
CAP1B
CAP1B
CAP1A
CAP1A

AV

TEST

CONV

CLK

DCLK

DXMIT

DIN

DV

1
2
3
4
5
6
7

DD

DD

DDC112U

8

9
10
11
12
13
14

28

IN2

27

AGND

26

CAP2B

25

CAP2B

24

CAP2A

23

CAP2A

22

V

REF

21

AGND

20

RANGE2 (MSB)

19

RANGE1

18

RANGE0 (LSB)

17

DVALID

16

DOUT

15

DGND

PIN DESCRIPTIONS

PIN LABEL DESCRIPTION

1 IN1 Input 1: analog input for Integrators 1A and 1B. The

2 AGND Analog Ground
3 CAP1B External Capacitor for Integrator 1B
4 CAP1B External Capacitor for Integrator 1B
5 CAP1A External Capacitor for Integrator 1A
6 CAP1A External Capacitor for Integrator 1A
7AV
8 TEST Test Control Input. When HIGH, a test charge is applied

9 CONV Controls which side of the integrator is connected to

10 CLK System Clock Input, 10MHz Nominal
11 DCLK Serial Data Clock Input. This input operates the serial I/

12 DXMIT Serial Data Transmit Enable Input. When LOW, this

13 DIN Serial Digital Input. Used to cascade multiple DDC112s.
14 DV
15 DGND Digital Ground
16 DOUT Serial Data Output, Hi-Z when DXMIT is HIGH
17 DVALID Data Valid Output. A LOW value indicates valid data is

18 RANGE0 Range Control Input 0 (least significant bit)
19 RANGE1 Range Control Input 1
20 RANGE2 Range Control Input 2 (most significant bit)
21 AGND Analog Ground
22 V
23 CAP2A External Capacitor for Integrator 2A
24 CAP2A External Capacitor for Integrator 2A
25 CAP2B External Capacitor for Integrator 2B
26 CAP2B External Capacitor for Integrator 2B
27 AGND Analog Ground
28 IN2 Input 2: analog input for Integrators 2A and 2B. The

integrator that is active is set by the CONV input.

Analog Supply, +5V Nominal

DD

to the A or B integrators on the next CONV transition.

input. In continuous mode; CONV HIGH → side A is
integrating, CONV LOW → side B is integrating. CONV
must be synchronized with CLK (see Figure 2).

O shift register.

input enables the internal serial shift register.

Digital Supply, +5V Nominal

DD

available in the serial I/O register.

External Reference Input, +4.096V Nominal

REF

integrator that is active is set by the CONV input.

4

www.ti.com

DDC112

SBAS085B

DDC112

SBAS085B

5

TYPICAL CHARACTERISTICS

At TA = +25°C, characterization done with Range 5 (250pC), T

= 500µs, V

INT

= +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted.

REF

70

60

50

Range 0

40

(C

EXT

30

20

Noise (ppm of FSR, rms)

10

0

200 8000 1000600400

5

4.5
C

SENSOR

= 50pF

4

3.5

3

C

= 0pF

SENSOR

2.5

2

1.5

1

Noise (ppm of FSR, rms)

0.5

Range 5

0

30 4020 9010 10070 80 1050 60

NOISE vs C

SENSOR

Range 1

= 250pF)

Range 7

C

(pF)

SENSOR

NOISE vs INPUT LEVEL

Input Level (% of Full-Scale)

Range 2

6

5

C

= 50pF

SENSOR

4

C

= 0pF

SENSOR

NOISE vs T

INT

3

2

Noise (ppm of FSR, rms)

Range 5

1

0

1 10000.1 10010

T

(ms)

INT

NOISE vs TEMPERATURE

9
8

Range 1

7
6
5
4
3
2

Noise (ppm of FSR, rms)

C

= 0pF

SENSOR

1

Range 2

Range 3

Range 7

0

–40 –15 10 35 60 85

Temperature (°C)

2000

1500

1000

500

0

Range Drift (ppm)

–500

–1000

–1500

–40 –15 10 35 60 85

6

RANGE DRIFT vs TEMPERATURE

Ranges 1 - 7

(Internal Integration Capacitor)

Temperature (°C)

www.ti.com

IB vs TEMPERATURE

10

All Ranges

1

(pA)

B

I

0.1

0.01
25 35 45 55 65 75 85

Temperature (°C)

DDC112

SBAS085B

DDC112

SBAS085B

7

THEORY OF OPERATION

The basic operation of the DDC112 is illustrated in
The device contains two identical input channels where each
performs the function of current-to-voltage integration fol­lowed by a multiplexed analog-to-digital (A/D) conversion.
Each input has two integrators so that the current-to-voltage
integration can be continuous in time. The output of the four
integrators are switched to one delta-sigma (∆Σ) converter
via a four input multiplexer. With the DDC112 in the continu­ous integration mode, the output of the integrators from one
side of both of the inputs will be digitized while the other two
integrators are in the integration mode as illustrated in the
timing diagram in Figure 2. This integration and A/D conver­sion process is controlled by the system clock, CLK. With a
10MHz system clock, the integrator combined with the delta­sigma converter accomplishes a single 20-bit conversion in
approximately 220µs. The results from side A and side B of
each signal input are stored in a serial output shift register.

Figure 1.

The DVALID

output goes LOW when the shift register

contains valid data.
The digital interface of the DDC112 provides the digital

results via a synchronous serial interface consisting of a data
clock (DCLK), a transmit enable pin (
(DVALID

), a serial data output pin (DOUT), and a serial data

DXMIT

), a valid data pin

input pin (DIN). The DDC112 contains only one A/D con­verter, so the conversion process is interleaved between the
two inputs, as shown in Figure 2. The integration and
conversion process is fundamentally independent of the data
retrieval process. Consequently, the CLK frequency and
DCLK frequencies need not be the same. DIN is only used
when multiple converters are cascaded and should be tied to
DGND otherwise. Depending on T

, CLK, and DCLK, it is

INT

possible to daisy-chain over 100 converters. This greatly
simplifies the interconnection and routing of the digital out­puts in cases where a large number of converters are
needed.

CAP1A
CAP1A

IN1

CAP1B
CAP1B

CAP2A
CAP2A

IN2

CAP2B
CAP2B

FIGURE 1. Block Diagram.

IN1, Integrator A

DD

Input 1

Dual

Switched

Integrator

Input 2

Dual

Switched

Integrator

Integrate

AGNDAV

V

REF

∆Σ

Modulator

Digital

Filter

TEST

Control

CONV

Integrate

DD

Digital

Input/Output

CLK

DGNDDV

DCLK

DVALID
DXMIT
DOUT
DIN

RANGE2
RANGE1
RANGE0

IN1, Integrator B

IN2, Integrator A

IN2, Integrator B

Conversion in Progress

DVALID

Integrate

IN1B IN2B IN1A

Integrate

Integrate

Integrate

IN2A IN1B IN2B IN1A

FIGURE 2. Basic Integration and Conversion Timing for the DDC112 (continuous mode).

8

www.ti.com

Integrate

Integrate

IN2A

DDC112

SBAS085B

DDC112

SBAS085B

9

CONV

CLK

S

INTA

S

INTB

S

REF1

S

REF2

S

RESET

S

A/D1A

Configuration of

Integrator A

V

REF

WaitConvert WaitConvertIntegrate

Reset

Wait

Integrator A

Voltage Output

FIGURE 4. Basic Integrator Timing Diagram as Illustrated in Figure 3.

S

S

REF2

REF2

S

S

S

S

REF1

A/D

REF1

A/D

V

REF

To Converter

V

REF

To Converter

IN

IN

S

INT

IN

S

RESET

a) Reset Configuration

S

INT

IN

S

RESET

c) Integrate Configuration

C

F

C

F

S

INT

S

RESET

b) Wait Configuration

S

INT

S

RESET

Wait

Reset

S

S

REF1

REF2

V

REF

C

F

To Converter

S

A/D

S

REF2

S

REF1

V

REF

C

F

To Converter

S

A/D

d) Convert Configuration

FIGURE 5. Diagrams for the Four Configurations of the Front End Integrators of the DDC112.

10

www.ti.com

DDC112

SBAS085B