The DDC112 is a dual input, wide dynamic range, chargedigitizing analog-to-digital (A/D) converter with 20-bit resolution. Low-level current output devices, such as photosensors,
can be directly connected to its inputs. Charge integration is
continuous as each input uses two integrators; while one is
being digitized, the other is integrating.
For each of its two inputs, the DDC112 combines current-tovoltage conversion, continuous integration, programmable
full-scale range, A/D conversion, and digital filtering to achieve
a precision, wide dynamic range digital result. In addition to
the internal programmable full-scale ranges, external integrating capacitors allow an additional user-settable full-scale
range of up to 1000pC.
To provide single-supply operation, the internal A/D converter
utilizes a differential input, with the positive input tied to V
When the integration capacitor is reset at the beginning of
each integration cycle, the capacitor charges to V
charge is removed in proportion to the input current. At the
end of the integration cycle, the remaining voltage is compared to V
REF
.
The high-speed serial shift register which holds the result of
the last conversion can be configured to allow multiple DDC112
units to be cascaded, minimizing interconnections. The
DDC112 is available in an SO-28 or TQFP-32 package and is
offered in two performance grades.
REF
REF
. This
.
AGNDAV
DD
CAP1A
CAP1A
IN1
CAP1B
CAP1B
CAP2A
CAP2A
IN2
CAP2B
CAP2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
AVDD to DVDD.......................................................................–0.3V to +6V
AV
to AGND ..................................................................... –0.3V to +6V
DD
DV
to DGND ..................................................................... –0.3V to +6V
DD
AGND to DGND ............................................................................... ±0.3V
V
Voltage to AGND ........................................... –0.3V to AVDD + 0.3V
REF
Digital Input Voltage to DGND .............................. –0.3V to DV
Digital Output Voltage to DGND ........................... –0.3V to DV
Package Power Dissipation ............................................. (T
Maximum Junction Temperature (T
Thermal Resistance, SO,
Thermal Resistance, TQFP,
Lead Temperature (soldering, 10s)............................................... +300°C
NOTE: (1) Stresses above those listed under
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
DDC112Y±0.025% Reading ±1.0ppm FSR–40°C to +85°CTQFP-32PJTDDC112Y/250Tape and Reel
"""""DDC112Y/2KTape and Reel
DDC112YK±0.025% Reading ±1.0ppm FSR0°C to +70°CTQFP-32PJTDDC112YK/250Tape and Reel
"""""DDC112YK/2KTape and Reel
NOTES: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data shee t. (2) Models with a slash
(/) are available only in Tape and Reel in the quantities indicated (/1K indicates 1000 devices per reel). Ordering 1000 pieces of
piece Tape and Reel.
DDC112U/1K
will get a single 1000-
2
www.ti.com
DDC112
SBAS085B
ELECTRICAL CHARACTERISTICS
At TA = +25°C, AVDD = DVDD = +5V, DDC112U, Y: T
operation, and internal integration capacitors, unless otherwise noted.
PARAMETERCONDITIONSMINTYPMAXMINTYPMAXUNITS
ANALOG INPUTS
External, Positive Full-Scale
Range 0C
Internal, Positive Full-Scale
Range 147.55052.5✻✻✻ pC
Range 295100105✻✻✻ pC
Range 3142.5150157.5✻✻✻ pC
Range 4190200210✻✻✻ pC
Range 5237.5250262.5✻✻✻ pC
Range 6285300315✻✻✻ pC
Range 7332.5350367.5✻✻✻ pC
Negative Full-Scale Input–0.4% of Positive FS✻pC
DYNAMIC CHARACTERISTICS
Conversion Rate23kHz
Integration Time, T
Integration Time, T
System Clock Input (CLK)11012✻✻15MHz
INT
INT
Non-Continuous Mode50✻µs
Data Clock (DCLK)1215MHz
ACCURACY
Noise, Low-Level Current Input
Differential Linearity Error±0.005% Reading ±0.5ppm
Integral Linearity Error
(1)
C
SENSOR
C
SENSOR
C
SENSOR
(4)
No Missing Codes20✻Bits
Input Bias CurrentT
Range ErrorRange 5 (250pC)5✻% of FSR
Range Error Match
Range Sensitivity to V
Offset ErrorRange 5, (250pC)±200✻±600ppm of FSR
Offset Error Match
DC Bias Voltage
(5)
REF
(5)
(6)
(Input VOS)±0.05±2✻✻mV
V
Power-Supply Rejection Ratio±25±200✻✻ppm of FSR/V
Internal Test Signal13✻pC
Internal Test Accuracy±10✻%
PERFORMANCE OVER TEMPERATURE
Offset Drift±0.5±3
Offset Drift Stability±0.2✻±0.7
DC Bias Voltage DriftApplied to Sensor Input3±1µV/°C
Input Bias Current Drift+25°C to +45°C0.011
Input Bias CurrentT
Range Drift
Range Drift Match
✻ Specifications same as DDC112U, Y.
NOTES: (1) Input is less than 1% of full scale. (2) C
(4) A best-fit line is used in measuring linearity. (5) Matching between side A and side B, not input 1 to input 2. (6) Voltage produced by the DDC112 at its input which
is applied to the sensor. (7) Range drift does not include external reference drift. (8) Input reference current decreases with increasing T
section). (9) Data format is Straight Binary with a small offset (see the
= 500µs, CLK = 10MHz, DDC112UK, YK: T
INT
= 333.3µs, CLK = 15MHz, V
INT
= +4.096V, continuous mode
REF
DDC112U, YDDC112UK, YK
= 250pF1000✻pC
EXT
Continuous Mode5001,000,000333.3✻µs
(2)
= 0pF, Range 5 (250pC)3.2✻
ppm of FSR
(3)
, rms
= 25pF, Range 5 (250pC)3.8✻ppm of FSR, rms
= 50pF, Range 5 (250pC)4.26.0✻7ppm of FSR, rms
FSR (max)✻
±0.005% Reading ±0.5ppm
FSR (typ)✻
±0.025% Reading ±1.0ppm
FSR (max)✻
= +25°C0.110✻✻pA
A
All Ranges0.10.5✻✻% of FSR
= 4.096 ±0.1V1:1✻
REF
±100✻ppm of FSR
(10)
ppm of FSR/°C
(10)
ppm of FSR/minute
(10)
= +75°C250
A
Range 5 (250pC)2502550
(10)
✻✻ pA/°C
✻✻pA
(10)
ppm/°C
Range 5 (250pC)±0.05✻ppm/°C
T
= 500µs150225275µA
INT
4.0
–0.3+0.8✻✻V
DV
DD
+ 0.3
✻✻V
IOH = –500µA4.5✻V
IOL = 500µA0.4✻V
–10+10✻✻µA
Straight Binary✻
and DV
DD
DD
= +5V14.815.2mA
DD
= +5V1.21.8mA
DD
is the capacitance seen at the DDC112 inputs from wiring, photodiode, etc. (3) FSR is Full-Scale Range.
SENSOR
4.755.25✻✻V
Data Retrieval
section). (10) Ensured by design but not production tested.
INT
(see the
Voltage Reference
DDC112
SBAS085B
www.ti.com
3
PIN CONFIGURATION
Top ViewSO
IN1
AGND
CAP1B
CAP1B
CAP1A
CAP1A
AV
TEST
CONV
CLK
DCLK
DXMIT
DIN
DV
1
2
3
4
5
6
7
DD
DD
DDC112U
8
9
10
11
12
13
14
28
IN2
27
AGND
26
CAP2B
25
CAP2B
24
CAP2A
23
CAP2A
22
V
REF
21
AGND
20
RANGE2 (MSB)
19
RANGE1
18
RANGE0 (LSB)
17
DVALID
16
DOUT
15
DGND
PIN DESCRIPTIONS
PINLABELDESCRIPTION
1IN1Input 1: analog input for Integrators 1A and 1B. The
2AGNDAnalog Ground
3CAP1BExternal Capacitor for Integrator 1B
4CAP1BExternal Capacitor for Integrator 1B
5CAP1AExternal Capacitor for Integrator 1A
6CAP1AExternal Capacitor for Integrator 1A
7AV
8TESTTest Control Input. When HIGH, a test charge is applied
9CONVControls which side of the integrator is connected to
10CLKSystem Clock Input, 10MHz Nominal
11DCLKSerial Data Clock Input. This input operates the serial I/
12DXMITSerial Data Transmit Enable Input. When LOW, this
13DINSerial Digital Input. Used to cascade multiple DDC112s.
14DV
15DGNDDigital Ground
16DOUTSerial Data Output, Hi-Z when DXMIT is HIGH
17DVALID Data Valid Output. A LOW value indicates valid data is
18RANGE0 Range Control Input 0 (least significant bit)
19RANGE1 Range Control Input 1
20RANGE2 Range Control Input 2 (most significant bit)
21AGNDAnalog Ground
22V
23CAP2A External Capacitor for Integrator 2A
24CAP2A External Capacitor for Integrator 2A
25CAP2B External Capacitor for Integrator 2B
26CAP2B External Capacitor for Integrator 2B
27AGNDAnalog Ground
28IN2Input 2: analog input for Integrators 2A and 2B. The
integrator that is active is set by the CONV input.
Analog Supply, +5V Nominal
DD
to the A or B integrators on the next CONV transition.
input. In continuous mode; CONV HIGH → side A is
integrating, CONV LOW → side B is integrating. CONV
must be synchronized with CLK (see Figure 2).
O shift register.
input enables the internal serial shift register.
Digital Supply, +5V Nominal
DD
available in the serial I/O register.
External Reference Input, +4.096V Nominal
REF
integrator that is active is set by the CONV input.
4
www.ti.com
DDC112
SBAS085B
DDC112
SBAS085B
5
TYPICAL CHARACTERISTICS
At TA = +25°C, characterization done with Range 5 (250pC), T
The basic operation of the DDC112 is illustrated in
The device contains two identical input channels where each
performs the function of current-to-voltage integration followed by a multiplexed analog-to-digital (A/D) conversion.
Each input has two integrators so that the current-to-voltage
integration can be continuous in time. The output of the four
integrators are switched to one delta-sigma (∆Σ) converter
via a four input multiplexer. With the DDC112 in the continuous integration mode, the output of the integrators from one
side of both of the inputs will be digitized while the other two
integrators are in the integration mode as illustrated in the
timing diagram in Figure 2. This integration and A/D conversion process is controlled by the system clock, CLK. With a
10MHz system clock, the integrator combined with the deltasigma converter accomplishes a single 20-bit conversion in
approximately 220µs. The results from side A and side B of
each signal input are stored in a serial output shift register.
Figure 1.
The DVALID
output goes LOW when the shift register
contains valid data.
The digital interface of the DDC112 provides the digital
results via a synchronous serial interface consisting of a data
clock (DCLK), a transmit enable pin (
(DVALID
), a serial data output pin (DOUT), and a serial data
DXMIT
), a valid data pin
input pin (DIN). The DDC112 contains only one A/D converter, so the conversion process is interleaved between the
two inputs, as shown in Figure 2. The integration and
conversion process is fundamentally independent of the data
retrieval process. Consequently, the CLK frequency and
DCLK frequencies need not be the same. DIN is only used
when multiple converters are cascaded and should be tied to
DGND otherwise. Depending on T
, CLK, and DCLK, it is
INT
possible to daisy-chain over 100 converters. This greatly
simplifies the interconnection and routing of the digital outputs in cases where a large number of converters are
needed.
CAP1A
CAP1A
IN1
CAP1B
CAP1B
CAP2A
CAP2A
IN2
CAP2B
CAP2B
FIGURE 1. Block Diagram.
IN1, Integrator A
DD
Input 1
Dual
Switched
Integrator
Input 2
Dual
Switched
Integrator
Integrate
AGNDAV
V
REF
∆Σ
Modulator
Digital
Filter
TEST
Control
CONV
Integrate
DD
Digital
Input/Output
CLK
DGNDDV
DCLK
DVALID
DXMIT
DOUT
DIN
RANGE2
RANGE1
RANGE0
IN1, Integrator B
IN2, Integrator A
IN2, Integrator B
Conversion in Progress
DVALID
Integrate
IN1BIN2BIN1A
Integrate
Integrate
Integrate
IN2AIN1BIN2BIN1A
FIGURE 2. Basic Integration and Conversion Timing for the DDC112 (continuous mode).
8
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Integrate
Integrate
IN2A
DDC112
SBAS085B
DDC112
SBAS085B
9
CONV
CLK
S
INTA
S
INTB
S
REF1
S
REF2
S
RESET
S
A/D1A
Configuration of
Integrator A
V
REF
WaitConvertWaitConvertIntegrate
Reset
Wait
Integrator A
Voltage Output
FIGURE 4. Basic Integrator Timing Diagram as Illustrated in Figure 3.
S
S
REF2
REF2
S
S
S
S
REF1
A/D
REF1
A/D
V
REF
To Converter
V
REF
To Converter
IN
IN
S
INT
IN
S
RESET
a) Reset Configuration
S
INT
IN
S
RESET
c) Integrate Configuration
C
F
C
F
S
INT
S
RESET
b) Wait Configuration
S
INT
S
RESET
Wait
Reset
S
S
REF1
REF2
V
REF
C
F
To Converter
S
A/D
S
REF2
S
REF1
V
REF
C
F
To Converter
S
A/D
d) Convert Configuration
FIGURE 5. Diagrams for the Four Configurations of the Front End Integrators of the DDC112.
10
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DDC112
SBAS085B
DDC112
SBAS085B
11
A low-pass filter to reduce noise connects it to an operational amplifier configured as a buffer. This amplifier should
have a unity-gain bandwidth greater than 4MHz, low noise,
and input/output common-mode ranges that support V
REF
Following the buffer are capacitors placed close to the
DDC112 V
pin. Even though the circuit in Figure 6 might
REF
appear to be unstable due to the large output capacitors, it
works well for most operational amplifiers. It is NOT recommended that series resistance be placed in the output lead
to improve stability since this can cause droop in V
REF
which
produces large offsets.
DDC112 Frequency Response
The frequency response of the DDC112 is set by the front end
integrators and is that of a traditional continuous time integrator, as shown in Figure 7. By adjusting T
, the user can
INT
change the 3dB bandwidth and the location of the notches in
the response. The frequency response of the ∆Σ converter that
follows the front end integrator is of no consequence because
the converter samples a held signal from the integrators. That
is, the input to the ∆Σ converter is always a DC signal. Since
the output of the front end integrators are sampled, aliasing can
occur. Whenever the frequency of the input signal exceeds
one-half of the sampling rate, the signal will
fold
back down to
lower frequencies.
Test Mode
When TEST is used, pins IN1 and IN2 are grounded and
packets
of approximately 13pC charge are transferred to the
0
.
–10
–20
–30
Gain (dB)
–40
–50
0.1
T
INT
1
T
INT
Frequency
10
T
INT
FIGURE 7. Frequency Response of the DDC112.
integration capacitors of both Input 1 and Input 2. This fixed
charge can be transferred to the integration capacitors either
once during an integration cycle or multiple times. In the case
where multiple packets are transferred during one integration
period, the 13pC charge is additive. This mode can be used
in both the continuous and noncontinuous mode timing. The
timing diagrams for test mode are shown in Figure 8. The top
three lines in Figure 8 define the timing when one packet of
13pC is sent to the integration capacitors. The bottom three
lines define the timing when multiple packets are sent to the
integration capacitors.
100
T
INT
Action
CONV
TEST
Action
CONV
TEST
Test Mode Disabled
Integrate B
Test Mode Disabled
Integrate B Integrate A
Integrate A
Test Mode Enabled
13pC into B13pC into A13pC into B13pC into A
t
1
Test Mode Enabled
13pC into B26pC into A39pC into B52pC into A
t
4
t
1
t
3
t
5
Test Mode Disabled
Integrate B Integrate A
t
2
Test Mode Disabled
Integrate B Integrate A
t
2
t
4
FIGURE 8. Timing Diagram of the Test Mode of the DDC112.
CLK = 10MHzCLK = 15MHz
SYMBOLDESCRIPTIONMINTYPMAXMINTYPMAXUNITS
t
1
t
2
t
3
t
4
t
5
Setup Time for Test Mode Enable100100ns
Setup Time for Test Mode Disable100100ns
Hold Time for Test Mode Enable100100ns
From Rising Edge of TEST to the Edge of CONV5.43.6µs
while Test Mode Enabled
Rising Edge to Rising Edge of TEST5.43.6µs
TABLE III. Timing for the DDC112 in the Test Mode.
12
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DDC112
SBAS085B
DDC112
SBAS085B
13
During the cont mode, mbsy is not active when CONV
toggles. The non-integrating side is always ready to begin
integrating when the other side finishes its integration. Consequently, keeping track of the current status of CONV is all
that is needed to know the current state. Cont mode operation corresponds to states 3-6. Two of the states, 3 and 6,
only perform an integration (no m/r/az cycle).
mbsy becomes important when operating in the ncont mode;
states 1, 2, 7, and 8. Whenever CONV is toggled while mbsy
is active, the DDC112 will enter or remain in either ncont
state 1 (or 8). After mbsy goes inactive, state 2 (or 7) is
entered. This state prepares the appropriate side for integration. As mentioned above, in the ncont states, the inputs to
the DDC112 are grounded.
One interesting observation from the state diagram is that the
integrations always alternate between sides A and B. This
relationship holds for any CONV pattern and is independent
of the mode. States 2 and 7 insure this relationship during the
ncont mode.
When power is first applied to the DDC112, the beginning
state is either 1 or 8, depending on the initial level of CONV.
For CONV held HIGH at power-up, the beginning state is 1.
Conversely, for CONV held LOW at power-up, the beginning
state is 8. In general, there is a symmetry in the state
diagram between states 1-8, 2-7, 3-6, and 4-5. Inverting
CONV results in the states progressing through their symmetrical match.
TIMING EXAMPLES
Cont Mode
A few timing diagrams will now be discussed to help illustrate
the operation of the state machine. These are shown in
Figures 10 through 19. Table V gives generalized timing
specifications in units of CLK periods. Values in µs for
Table V can be easily found for a given CLK. For example,
if CLK = 10MHz, then a CLK period = 0.1µs. t
in Table V
6
would then be 479.4µs.
SYMBOL DESCRIPTIONVALUE (CLK periods)
Cont mode m/r/az cycle.4794
t
6
t
Cont mode data ready.4212(t
7
t
1st ncont mode data ready.4212 ±3
8
t
2nd ncont mode data ready.4548
9
t
Ncont mode m/r/az cycle.9108
10
4212 ±3(t
> 4794)
INT
= 4794)
INT
T ABLE V . Timing Specifications Generalized in CLK Periods.
Figure 10 shows a few integration cycles beginning with
initial power-up for a cont mode example. The top signal is
CONV and is supplied by the user. The next line indicates the
current state in the state diagram. The following two traces
show when integrations and measurement cycles are underway. The internal signal mbsy is shown next. Finally, DVALID
is given. As described in the data sheet, DVALID goes active
LOW when data is ready to be retrieved from the DDC112.
It stays LOW until
DXMIT
is taken LOW by the user. In Figure
10 and the following timing diagrams, it is assumed that
DXMIT
it taken LOW soon after DVALID goes LOW. The text
below the DVALID
pulse indicates the side of the data and
arrows help match the data to the corresponding integration.
The signals shown in Figures 10 through 19 are drawn at
approximately the same scale.
In Figure 10, the first state is ncont state 1. The DDC112
always powers up in the ncont mode. In this case, the first
state is 1 because CONV is initially HIGH. After the first two
states, cont mode operation is reached and the states begin
toggling between 4 and 5. From now on, the input is being
continuously integrated, either by side A or side B. The time
needed for the m/r/az cycle, t
, is the same time that
6
CONV
State
Integration
Status
m/r/az
Status
mbsy
DVALID
SYMBOL
t
6
t
7
t = 0
Power-Up
DESCRIPTIONVALUE (CLK = 10MHz)VALUE (CLK = 15MHz)
Cont mode m/r/az cycle.479.4µs319.6µs
Cont mode data ready.421.2µs(T
421.2 ±0.3µs(T
432154
Integrate BIntegrate AIntegrate AIntegrate B
m/r/az Am/r/az Bm/r/az A
t
6
t
7
Side A
FIGURE 10. Continuous Mode Timing (CONV HIGH at power-up).
14
www.ti.com
Data
> 479.4µs)280.8µs(T
INT
= 479.4µs)280.8 ±0.2µs(T
INT
Side B
Data
Side A
Data
> 319.6µs)
INT
= 319.6µs)
INT
DDC112
SBAS085B
DDC112
SBAS085B
15
Ncont Mode
Figure 13 illustrates operation in the ncont mode. The
integrations come in pairs (that is, sides A/B or sides B/A)
followed by a time during which no integrations occur.
During that time, the previous integrations are being measured, reset and auto-zeroed. Before the DDC112 can
advance to states 3 or 6, both sides A and B must be
finished with the m/r/az cycle which takes time t
m/r/az cycles are completed, time t
is needed to prepare
11
the next side for integration. This time is required for the
ncont mode because the m/r/az cycle of the ncont mode is
slightly different from that of the cont mode. After the first
integration ends, DVALID
CONV
goes LOW in time t8. This is the
. When the
10
same time as in the cont mode. The second data will be
ready in time t
after the first data is ready. One result of the
9
naming convention used in this application bulletin is that
when the DDC112 is operating in the
through both
ncont mode states
ncont mode
and
cont mode states
, it passes
. For
example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4, 1,
2, 3, 4...where 3 and 4 are cont mode states.
Ncont mode
by definition means that for some portion of the time, neither
side A nor B is integrating. States that perform an integration
are labeled
called
cont mode states
ncont mode states
while those that do not are
. Since integrations are performed
in the ncont mode, just not continuously, some cont mode
states must be used in an ncont mode state pattern.
State
Integration
Status
m/r/az
Status
mbsy
DVALID
SYMBOL
t
8
t
9
t
10
t
11
23134412
t
11
Int BInt AInt BInt A
m/r/az Bm/r/az A
t
10
t
9
t
8
Side A
Data
DESCRIPTIONVALUE (CLK = 10MHz)VALUE (CLK = 15MHz)
1st ncont mode data ready.421.2 ±0.3µs280.8 ±0.2µs
2nd ncont mode data ready.454.8µs303.2µs
Ncont mode m/r/az cycle.910.8µs607.2µs
Prepare side for integration.≥ 24.0µs≥ 24.0µs
Side B
Data
m/r/az Am/r/az B
Side A
Data
Side B
Data
FIGURE 13. Non-Continuous Mode Timing.
16
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DDC112
SBAS085B
DDC112
SBAS085B
17
Looking at the state diagram, one can see that the CONV
pattern needed to generate a given state progression is not
unique. Upon entering states 1 or 8, the DDC112 remains in
those states until mbsy goes LOW, independent of CONV.
As long as the m/r/az cycle is underway, the state machine
ignores CONV (see Figure 9). The top two signals are
different CONV patterns that produce the same state.
This feature can be a little confusing at first, but it does allow
flexibility in generating ncont mode CONV patterns. For
example, the DDC112 Evaluation Fixture operates in the
ncont mode by generating a square wave with pulse width
< t
. Figure 17 illustrates operation in the ncont mode using
6
CONV1
CONV2
mbsy
a 50% duty cycle CONV signal with T
= 1620 CLK
INT
periods. Care must be exercised when using a square wave
to generate CONV. There are certain integration
times that
must be avoided since they produce very short intervals for
state 2 (or state 7 if CONV is inverted). As seen in the state
diagram, the state progresses from 2 to 3 as soon as CONV
is HIGH. The state machine does not insure that the duration
of state 2 is long enough to properly prepare the next side
for integration (t
). This must be done by the user with
11
proper timing of CONV. For example, if CONV is a square
wave with T
CLK periods long, therefore, t
= 3042 CLK periods, state 2 will only be 18
INT
will not be met.
11
State
FIGURE 16. Equivalent CONV Signals in Non-Continuous Mode.
CONV
State
Integration
Status
mbsy
DVALID
Int A
Side A
Data
23134412
2313441
Int BInt AInt B
Side B
Data
Side A
Data
FIGURE 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal.
18
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DDC112
SBAS085B
DDC112
SBAS085B
19
SPECIAL CONSIDERATIONS
NCONT MODE INTEGRATION TIME
The DDC112 uses a relatively fast clock. For CLK = 10MHz,
this allows T
should be synchronized to CLK. However, for the internal
measurement, reset and auto-zero operations, a slower
clock is more efficient. The DDC112 divides CLK by six and
uses this slower clock with a period of 600ns to run the m/r/
az cycle and data ready logic.
Because of the divider, it is possible for the integration time
to be a non-integer number of slow clock periods.
example, if T
there will be 833 1/3 slow clocks in an integration period. This
non-integer relationship between T
period causes the number of rising and falling slow clock
edges within an integration period to change from integration
to integration. The digital coupling of these edges to the
integrators will in turn change from integration to integration
which produces noise. The change in the clock edges is not
random, but will repeat every 3 integrations. The coupling
noise on the integrators appears as a tone with a frequency
equal to the rate at which the coupling repeats.
To avoid this problem in cont mode, the internal slow clock
is shut down after the m/r/az cycle is complete when it is no
longer needed. It starts up again just after the next integration begins. Since the slow clock is always off when CONV
toggles, the same number of slow clock edges fall within an
integration period regardless of its length. Therefore,
T
≥ 4794 CLK periods will not produce the coupling
INT
problem described above.
For the ncont mode however, the slow clock must always be
left running. The m/r/az cycle is not completed before an
integration ends. It is then possible to have digital coupling to
the integrators. The digital coupling noise depends heavily on
the layout of the printed circuit board used for the DDC112.
For solid grounds and power supplies with good bypassing,
it is possible to greatly reduce the coupling. However, for
ensuring the best performance in the ncont mode, the integration time should be chosen to be an integer multiple of
1/(2f
SLOWCLOCK
should be an integer multiple of 300ns—T
A better choice would be T
DATA READY
The DVALID signal which indicates that data is ready is
generated using the internal slow clock. The phase relationship between this clock and CLK is set when power is first
applied and is random. Since CONV is synchronized with
CLK, it will have a random phase relationship with respect to
the slow clock. When T
shut down as described above. This shutdown process
synchronizes the internal clock with CONV so that the time
between when CONV toggles to when
(t
and t8) is fixed.
7
to be adjusted in steps of 100ns since CONV
INT
= 5000 CLK periods (500µs for CLK = 10MHz),
INT
and the slow clock
INT
). For CLK = 10MHz, the integration time
= 100µs is not.
= 99µs.
INT
> t6, the slow clock will temporarily
INT
INT
DVALID
goes LOW
For
For T
≤ t6, the internal slow clock, is not allowed to shut
INT
down and the synchronization never occurs. Therefore, the
time between CONV toggling and DVALID
indicating data is
ready has uncertainty due to the random phase relationship
between CONV and the slow clock. This variation is
±1/(2f
SLOWCLOCK
) or ±3/f
. The timing to the second DVALID
CLK
in the ncont mode will not have a variation since it is
triggered off the first data ready (t
) and both are derived
9
from the slow clock.
Polling DVALID
to determine when data is ready eliminates
any concern about the variation in timing since the readback
is automatically adjusted as needed. If the data readback is
triggered off the toggling of CONV directly (instead of polling), then waiting the maximum value of t
or t8 insures that
7
data will always be ready before readback occurs.
Data Retrieval
In the continuous and noncontinuous modes of operation,
the data from the last conversion is available for retrieval with
the falling edge of DVALID
of
DXMIT
in combination with the data clock (DCLK) will
(see Figure 22). The falling edge
initiate the serial transmission of the data from the DDC112.
Typically, data is retrieved from the DDC112 as soon as
DVALID
falls and completed before the next CONV transition
from HIGH to LOW or LOW to HIGH occurs. If this is not the
case, care should be taken to stop activity on DCLK and
consequently DOUT by at least 10µs around a CONV transition. If this caution is ignored it is possible that the integration that is being initiated by CONV will have additional noise
introduced.
The serial output data at DOUT is transmitted in Straight
Binary Code per Table VIII. An output offset has been built
into the DDC112 to allow for the measurement of input
signals near and below zero. Board leakage up to
≈–0.4%
of the positive full-scale can be tolerated before the digital
output clips to all zeroes.
Multiple DDC112 units can be connected in serial or parallel
configurations, as illustrated in Figures 20 and 21.
DOUT can be used with DIN to
devices together to minimize wiring. In this mode of operation, the serial data output is shifted through multiple DDC112s,
as illustrated in Figure 20.
R
prevents DIN from floating when
PULLUP
Care should be taken to keep the capacitive load on DOUT
as low as possible when running CLK=15MHz.
daisy-chain
several DDC112
DXMIT
is HIGH.
20
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DDC112
SBAS085B
DDC112
SBAS085B
21
CLK
DVALID
DXMIT
DCLK
t
18
t
14
t
20
(1)
t
26
t
22
DIN
t
21
DOUT
NOTE: (1) Disable DCLK (preferably LOW) when DXMIT is HIGH.
Output Disabled
Output Disabled
Input A
Bit 1
MSB
Output Enabled
Output Enabled
t
22A, t22B
t
24
Input E
Bit 20
Input F
LSBLSBOutput DisabledMSB
Bit 1
t
25
Input F
Bit 20
t
23
Output Disabled
FIGURE 23. Timing Diagram When Using the DIN Function of the DDC112.
CLK = 10MHzCLK = 15MHz
SYMBOLDESCRIPTIONMINTYPMAXMINTYPMAXUNITS
t
24
t
25
t
26
Set-Up Time From DIN to Rising Edge of DCLK105ns
Hold Time For DIN After Rising Edge of DCLK1010ns
Hold Time for DXMIT HIGH Before Falling21.33µs
Edge of DVALID
TABLE X. Timing for the DDC112 Data Retrieval Using DIN.
RETRIEVAL
(CONTINUOUS MODE)
This is the most straightforward method. Data retrieval begins soon after DVALID
CONV toggles, see Figure 24. For best performance, data
retrieval must stop t
the most appropriate for longer integration times. The maximum time available for readback is T
For DCLK and CLK = 10MHz, the maximum number of
DDC112s that can be daisy-chained together is:
Where τ
T
= 1000µs and DCLK = 10MHz, the maximum number of
INT
BEFORE
CONV TOGGLES
goes LOW and finishes before
before CONV toggles. This method is
28
– t27 – t28.
INT
Ts
–.431 240µ
INT
τ
DCLK
is the period of the data clock. For example, if
DCLK
RETRIEVAL
AFTER
CONV TOGGLES
(CONTINUOUS MODE)
For shorter integration times, more time is available if data
retrieval begins after CONV toggles and ends before the new
data is ready. Data retrieval must wait t
before beginning. Figure 25 shows an example of this. The
maximum time available for retrieval is t
(421.2µs – 10µs – 2µs for CLK = 10MHz), regardless of T
The maximum number of DDC112s that can be daisychained together is:
409 240. µs
τ
DCLK
For DCLK = 10MHz, the maximum number of DDC112s is
102.
after CONV toggles
29
– t29 – t
27
DDC112s is:
INT
26
.
22
1000431 2
µµ
ss
–.
40 100
()()
ns
142 2142112
=→
.
DDCs
www.ti.com
DDC112
SBAS085B
DDC112
SBAS085B
23
RETRIEVAL
BEFORE
AND
AFTER
CONV
TOGGLES (CONTINUOUS MODE)
For the absolute maximum time for data retrieval, data can
be retrieved
before and after
CONV toggles. Nearly all of T
INT
is available for data retrieval. Figure 26 illustrates how this is
done by combining the two previous methods. You must
pause the retrieval during CONV toggling to prevent digital
noise, as discussed previously, and finish before the next
data is ready. The maximum number of DDC112s that can
be daisy-chained together is:
Tss
––202
µµ
INT
40
τ
DCLK
For T
= 500µs and DCLK = 10MHz, the maximum number
INT
of DDC112s is 119.
RETRIEVAL: NONCONTINUOUS MODE
Retrieving in noncontinuous mode is slightly different as
compared with the continuous mode. As shown in Figure 27
and described in detail in Application Bulletin SBAA024
(available for download at www.ti.com), DVALID
in time t
shorter than this time, all of t
after the first integration completes. If T
30
is available to retrieve data
31
before the other side’s data is ready. For T
goes LOW
> t30, the first
INT
INT
is
integration’s data is ready before the second integration
completes. Data retrieval must be delayed until the second
integration completes leaving less time available for retrieval.
The time available is t
31
– (T
– t30). The second integration’s
INT
data must be retrieved before the next round of integrations
begin. This time is highly dependent on the pattern used to
generate CONV. As with the continuous mode, data retrieval
must halt before and after CONV toggles (t
completed before new data is ready (t
and t29) and be
28
).
26
POWER-UP SEQUENCING
Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they should
never exceed AV
up is used to determine which side (A or B) will be integrated
first. Before integrations can begin though, CONV must
toggle; see Figure 28.
or DVDD. The level of CONV at power-
DD
CONV
DVALID
DXMIT
DCLK
DOUT
SYMBOLDESCRIPTIONMINTYPMAXMINTYPMAXUNITS
t
26
t
28
t
29
••••••••••••••••••
•••••••••
Hold Time for DXMIT HIGH Before Falling21.33µs
Data Retrieval Shutdown Before Edge of CONV1010µs
Data Retrieval Start-Up After dge of CONV1010µs
T
INT
Edge of DVALID
T
INT
t
29
t
28
Side B
Data
t
26
•••••••••
Side A
Data
CLK = 10MHzCLK = 15MHz
T
INT
FIGURE 26. Readback
24
Before and After
CONV Toggles.
www.ti.com
DDC112
SBAS085B
DDC112
SBAS085B
25
Input shielding practices should be taken into consideration
when designing the circuit layout for the DDC112. The inputs
to the DDC112 are high impedance and extremely sensitive
to extraneous noise. Leakage currents between the PCB
traces can exceed the input bias current of the DDC112 if
shielding is not implemented. Figure 30 illustrates an acceptable approach to this problem. A PC ground plane is placed
around the inputs of the DDC112. This shield helps minimize
coupled noise into the input pins. Additionally, the pins that
V
+
S
AV
DV
AV
DV
DD
DDC112
DD
DD
DDC112
DD
10µF
+
V
DD
10µF
V
+
S
10µF
< 10Ω
0.1µF
0.1µF
Separate +5V Supplies
0.1µF
0.1µF
are used for the external integration capacitors should be
guarded by a ground plane when the external capacitors are
used.
The approach above reduces leakage affects by surrounding
these sensitive pins with a low impedance analog ground.
Leakage currents from other portions of the circuit will flow
harmlessly to the low impedance analog ground rather than
into the analog input stage of the DDC112.
IN1IN2
Analog
Ground
Analog
Ground
Shield
external
caps when
used
Analog
Power
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DDC112U
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Analog
Ground
Shield
external
caps when
used
Analog
Ground
One +5V Supply
FIGURE 29. Power Supply Connection Options.
Digital I/O
and
Digital Power
Digital I/O
and
Digital Power
FIGURE 30. Recommended Shield for DDC112U Layout
Design.
26
www.ti.com
DDC112
SBAS085B
PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2007
PACKAGING INFORMATION
Orderable DeviceStatus
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
DDC112UACTIVESOICDW2820Green (RoHS &
no Sb/Br)
DDC112U/1KACTIVESOICDW281000 Green (RoHS &
no Sb/Br)
DDC112U/1KG4ACTIVESOICDW281000 Green (RoHS &
no Sb/Br)
DDC112UG4ACTIVESOICDW2820Green (RoHS &
no Sb/Br)
DDC112UKACTIVESOICDW2820Green (RoHS &
no Sb/Br)
DDC112UK/1KACTIVESOICDW281000 Green (RoHS &
no Sb/Br)
DDC112UK/1KG4ACTIVESOICDW281000 Green (RoHS &
no Sb/Br)
DDC112UKG4ACTIVESOICDW2820Green (RoHS &
no Sb/Br)
DDC112Y/250ACTIVETQFPPJT32250 Green (RoHS &
no Sb/Br)
DDC112Y/250G4ACTIVETQFPPJT32250 Green (RoHS &
no Sb/Br)
DDC112Y/2KACTIVETQFPPJT322000 Green (RoHS &
no Sb/Br)
DDC112Y/2KG4ACTIVETQFPPJT322000 Green (RoHS &
no Sb/Br)
DDC112YK/250ACTIVETQFPPJT32250 Green (RoHS &
no Sb/Br)
DDC112YK/250G4ACTIVETQFPPJT32250 Green (RoHS&
no Sb/Br)
DDC112YK/2KACTIVETQFPPJT322000 Green (RoHS &
no Sb/Br)
DDC112YK/2KG4ACTIVETQFPPJT322000 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined asfollows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the devicewill be discontinued, and alifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but isnot in production. Samples mayor may not be available.
OBSOLETE: TI has discontinued the production ofthe device.
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information andadditional product content details.
TBD: The Pb-Free/Green conversion plan has notbeen defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products aresuitable for use in specifiedlead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed0.1% by weight in homogeneousmaterial)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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