Texas Instruments DDC112, DDC112YK Datasheet

DDC112

Dual Current Input 20-Bit

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● MONOLITHIC CHARGE MEASUREMENT A/D

CONVERTER

● DIGITAL FILTER NOISE REDUCTION:

3.2ppm, rms

● INTEGRAL LINEARITY:

±0.005% Reading ±0.5ppm FSR

● HIGH PRECISION, TRUE INTEGRATING FUNC-

TION

● PROGRAMMABLE FULL-SCALE

● SINGLE SUPPLY

● CASCADABLE OUTPUT

APPLICATIONS

● DIRECT PHOTOSENSOR DIGITIZATION

● CT SCANNER DAS

● INFRARED PYROMETER

● PRECISION PROCESS CONTROL

● LIQUID/GAS CHROMATOGRAPHY

● BLOOD ANALYSIS

DESCRIPTION

The DDC112 is a dual input, wide dynamic range, charge­digitizing analog-to-digital (A/D) converter with 20-bit resolu­tion. Low-level current output devices, such as photosensors,
can be directly connected to its inputs. Charge integration is
continuous as each input uses two integrators; while one is
being digitized, the other is integrating.

For each of its two inputs, the DDC112 combines current-to­voltage conversion, continuous integration, programmable
full-scale range, A/D conversion, and digital filtering to achieve
a precision, wide dynamic range digital result. In addition to
the internal programmable full-scale ranges, external integrat­ing capacitors allow an additional user-settable full-scale
range of up to 1000pC.

To provide single-supply operation, the internal A/D converter
utilizes a differential input, with the positive input tied to V

REF

.
When the integration capacitor is reset at the beginning of
each integration cycle, the capacitor charges to V

REF

. This
charge is removed in proportion to the input current. At the
end of the integration cycle, the remaining voltage is com­pared to V

REF

.

The high-speed serial shift register which holds the result of
the last conversion can be configured to allow multiple DDC112
units to be cascaded, minimizing interconnections. The
DDC112 is available in an SO-28 or TQFP-32 package and is
offered in two performance grades.

Protected by US Patent #5841310

Dual

Switched

Integrator

Dual

Switched

Integrator

∆Σ

Modulator

Digital

Filter

Control

Digital

Input/Output

DVALID
DXMIT
DOUT
DIN

DCLK

RANGE2
RANGE1
RANGE0

TEST

CONV

CLK

CAP1A
CAP1A

CAP1B
CAP1B

CAP2A
CAP2A

CAP2B
CAP2B

IN2

IN1

V

REF

DGNDDV

DD

AGNDAV

DD

CHANNEL 1

CHANNEL 2

SBAS085B – JANUARY 2000 – REVISED OCTOBER 2004

D

D

C1

12

®

D

D

C

11

2

®

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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright © 2000-2004, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

DDC112

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AVDD to DVDD.......................................................................–0.3V to +6V

AV

DD

to AGND ..................................................................... –0.3V to +6V

DV

DD

to DGND ..................................................................... –0.3V to +6V

AGND to DGND ............................................................................... ±0.3V

V

REF

Voltage to AGND ........................................... –0.3V to AVDD + 0.3V

Digital Input Voltage to DGND .............................. –0.3V to DV

DD

+ 0.3V

Digital Output Voltage to DGND ........................... –0.3V to DV

DD

+ 0.3V

Package Power Dissipation ............................................. (T

JMAX

– TA)/

θ

JA

Maximum Junction Temperature (T

JMAX

) ...................................... +150°C

Thermal Resistance, SO,

θ

JA

....................................................+150°C/W

Thermal Resistance, TQFP,

θ

JA

................................................+100°C/W

Lead Temperature (soldering, 10s) ............................................... +300°C

NOTE: (1) Stresses above those listed under

Absolute Maximum Ratings

may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

(1)

PACKAGE/ORDERING INFORMATION

(1)

MAXIMUM SPECIFICATION

INTEGRAL TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT LINEARITY ERROR RANGE PACKAGE-LEAD DESIGNATOR NUMBER

(2)

MEDIA

DDC112U

±0.025% Reading ±1.0ppm FSR

–40°C to +85°C SO-28 DW DDC112U Rails

"""""DDC112U/1K Tape and Reel

DDC112UK

±0.025% Reading ±1.0ppm FSR

0°C to +70°C SO-28 DW DDC112UK Rails

"""""DDC112UK/1K Tape and Reel

DDC112Y ±0.025% Reading ±1.0ppm FSR –40°C to +85°C TQFP-32 PJT DDC112Y/250 Tape and Reel

"""""DDC112Y/2K Tape and Reel

DDC112YK ±0.025% Reading ±1.0ppm FSR 0°C to +70°C TQFP-32 PJT DDC112YK/250 Tape and Reel

"""""DDC112YK/2K Tape and Reel

NOTES: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. (2) Models with a slash
(/) are available only in Tape and Reel in the quantities indicated (/1K indicates 1000 devices per reel). Ordering 1000 pieces of

DDC112U/1K

will get a single 1000-

piece Tape and Reel.

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru­ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

DDC112

3

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ELECTRICAL CHARACTERISTICS

At TA = +25°C, AVDD = DVDD = +5V, DDC112U, Y: T

INT

= 500µs, CLK = 10MHz, DDC112UK, YK: T

INT

= 333.3µs, CLK = 15MHz, V

REF

= +4.096V, continuous mode

operation, and internal integration capacitors, unless otherwise noted.

✻ Specifications same as DDC112U, Y.
NOTES: (1) Input is less than 1% of full scale. (2) C

SENSOR

is the capacitance seen at the DDC112 inputs from wiring, photodiode, etc. (3) FSR is Full-Scale Range.
(4) A best-fit line is used in measuring linearity. (5) Matching between side A and side B, not input 1 to input 2. (6) Voltage produced by the DDC112 at its input which
is applied to the sensor. (7) Range drift does not include external reference drift. (8) Input reference current decreases with increasing T

INT

(see the

Voltage Reference

section). (9) Data format is Straight Binary with a small offset (see the

Data Retrieval

section). (10) Ensured by design but not production tested.

DDC112U, Y DDC112UK, YK

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ANALOG INPUTS

External, Positive Full-Scale

Range 0 C

EXT

= 250pF 1000 ✻ pC

Internal, Positive Full-Scale

Range 1 47.5 50 52.5 ✻✻✻ pC
Range 2 95 100 105 ✻✻✻ pC
Range 3 142.5 150 157.5 ✻✻✻ pC
Range 4 190 200 210 ✻✻✻ pC
Range 5 237.5 250 262.5 ✻✻✻ pC
Range 6 285 300 315 ✻✻✻ pC
Range 7 332.5 350 367.5 ✻✻✻ pC

Negative Full-Scale Input –0.4% of Positive FS ✻ pC

DYNAMIC CHARACTERISTICS

Conversion Rate 2 3 kHz
Integration Time, T

INT

Continuous Mode 500 1,000,000 333.3 ✻ µs

Integration Time, T

INT

Non-Continuous Mode 50 ✻ µs
System Clock Input (CLK) 1 10 12 ✻✻15 MHz
Data Clock (DCLK) 12 15 MHz

ACCURACY

Noise, Low-Level Current Input

(1)

C

SENSOR

(2)

= 0pF, Range 5 (250pC) 3.2 ✻

ppm of FSR

(3)

, rms

C

SENSOR

= 25pF, Range 5 (250pC) 3.8 ✻ ppm of FSR, rms

C

SENSOR

= 50pF, Range 5 (250pC) 4.2 6.0 ✻ 7 ppm of FSR, rms

Differential Linearity Error ±0.005% Reading ±0.5ppm

FSR (max) ✻

Integral Linearity Error

(4)

±0.005% Reading ±0.5ppm

FSR (typ) ✻

±0.025% Reading ±1.0ppm

FSR (max) ✻
No Missing Codes 20 ✻ Bits
Input Bias Current T

A

= +25°C 0.1 10 ✻✻ pA
Range Error Range 5 (250pC) 5 ✻ % of FSR
Range Error Match

(5)

All Ranges 0.1 0.5 ✻✻% of FSR

Range Sensitivity to V

REF

V

REF

= 4.096 ±0.1V 1:1 ✻
Offset Error Range 5, (250pC) ±200 ✻ ±600 ppm of FSR
Offset Error Match

(5)

±100 ✻ ppm of FSR

DC Bias Voltage

(6)

(Input VOS) ±0.05 ±2 ✻✻ mV
Power-Supply Rejection Ratio ±25 ±200 ✻✻ppm of FSR/V
Internal Test Signal 13 ✻ pC
Internal Test Accuracy ±10 ✻ %

PERFORMANCE OVER TEMPERATURE

Offset Drift ±0.5 ±3

(10)

ppm of FSR/°C

Offset Drift Stability ±0.2 ✻ ±0.7

(10)

ppm of FSR/minute
DC Bias Voltage Drift Applied to Sensor Input 3 ±1 µV/°C
Input Bias Current Drift +25°C to +45°C 0.01 1

(10)

✻✻ pA/°C

Input Bias Current T

A

= +75°C250

(10)

✻✻ pA

Range Drift

(7)

Range 5 (250pC) 25 0 25 50

(10)

ppm/°C

Range Drift Match

(5)

Range 5 (250pC) ±0.05 ✻ ppm/°C

REFERENCE

Voltage 4.000 4.096 4.200 ✻✻✻ V
Input Current

(8)

T

INT

= 500µs 150 225 275 µA

DIGITAL INPUT/OUTPUT

Logic Levels

V

IH

4.0

DV

DD

+ 0.3

✻✻V

V

IL

–0.3 +0.8 ✻✻V

V

OH

IOH = –500µA 4.5 ✻ V

V

OL

IOL = 500µA 0.4 ✻ V

Input Current, I

IN

–10 +10 ✻✻µA

Data Format

(9)

Straight Binary ✻

POWER-SUPPLY REQUIREMENTS

Power-Supply Voltage AV

DD

and DV

DD

4.75 5.25 ✻✻V

Supply Current

Analog Current AV

DD

= +5V 14.8 15.2 mA

Digital Current DV

DD

= +5V 1.2 1.8 mA

Total Power Dissipation 80 100 85 130 mW

TEMPERATURE RANGE

Specified Performance –40 +85 0 +70 °C
Storage –60 +100 ✻✻°C

DDC112

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PIN DESCRIPTIONS

PIN LABEL DESCRIPTION

1 IN1 Input 1: analog input for Integrators 1A and 1B. The

integrator that is active is set by the CONV input.
2 AGND Analog Ground
3 CAP1B External Capacitor for Integrator 1B
4 CAP1B External Capacitor for Integrator 1B
5 CAP1A External Capacitor for Integrator 1A
6 CAP1A External Capacitor for Integrator 1A
7AV

DD

Analog Supply, +5V Nominal
8 TEST Test Control Input. When HIGH, a test charge is applied

to the A or B integrators on the next CONV transition.
9 CONV Controls which side of the integrator is connected to

input. In continuous mode; CONV HIGH → side A is

integrating, CONV LOW → side B is integrating. CONV

must be synchronized with CLK (see Figure 2).

10 CLK System Clock Input, 10MHz Nominal
11 DCLK Serial Data Clock Input. This input operates the serial I/

O shift register.

12 DXMIT Serial Data Transmit Enable Input. When LOW, this

input enables the internal serial shift register.

13 DIN Serial Digital Input. Used to cascade multiple DDC112s.
14 DV

DD

Digital Supply, +5V Nominal

15 DGND Digital Ground
16 DOUT Serial Data Output, Hi-Z when DXMIT is HIGH
17 DVALID Data Valid Output. A LOW value indicates valid data is

available in the serial I/O register.

18 RANGE0 Range Control Input 0 (least significant bit)
19 RANGE1 Range Control Input 1
20 RANGE2 Range Control Input 2 (most significant bit)
21 AGND Analog Ground
22 V

REF

External Reference Input, +4.096V Nominal

23 CAP2A External Capacitor for Integrator 2A
24 CAP2A External Capacitor for Integrator 2A
25 CAP2B External Capacitor for Integrator 2B
26 CAP2B External Capacitor for Integrator 2B
27 AGND Analog Ground
28 IN2 Input 2: analog input for Integrators 2A and 2B. The

integrator that is active is set by the CONV input.

PIN CONFIGURATION

Top View SO

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

IN2
AGND
CAP2B
CAP2B
CAP2A
CAP2A
V

REF

AGND
RANGE2 (MSB)
RANGE1
RANGE0 (LSB)
DVALID
DOUT
DGND

IN1

AGND
CAP1B
CAP1B
CAP1A
CAP1A

AV

DD

TEST

CONV

CLK

DCLK

DXMIT

DIN

DV

DD

DDC112U

DDC112

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CAP1A
CAP1A

AV

DD

NC
NC

TEST

CONV

CLK

CAP2A
CAP2A
V

REF

AGND
NC
NC
RANGE2 (MSB)
RANGE1

1
2
3
4
5
6
7
8

24
23
22
21
20
19
18
17

DDC112Y

CAP1B

CAP1B

AGND

IN1

IN2

AGND

CAP2B

CAP2B

32

31

30

29

28

27

26

25

DCLK

DXMIT

DIN

DV

DD

DGND

DOUT

DVALID

RANGE0 (LSB)

9

10

11

12

13

14

15

16

PIN CONFIGURATION

Top View TQFP

PIN DESCRIPTIONS

PIN LABEL DESCRIPTION

1 CAP1A External Capacitor for Integrator 1A
2 CAP1A External Capacitor for Integrator 1A
3AV

DD

Analog Supply, +5V Nominal
4 NC No Connection
5 NC No Connection
6 TEST Test Control Input. When HIGH, a test charge is

applied to the A or B integrators on the next CONV

transition.
7 CONV Controls which side of the integrator is connected to

input. In continuous mode; CONV HIGH side A is

integrating, CONV LOW side B is integrating CONV

must be synchronized with CLK (see text).
8 CLK System Clock Input, 10MHz Nominal
9 DCLK Serial Data Clock Input. This input operates the

serial I/O shift register.

10 DXMIT Serial Data Transmit Enable Input. When LOW, this

input enables the internal serial shift register.

11 DIN Serial Digital Input. Used to cascade multiple

DDC112s.

12 DV

DD

Digital Supply, +5V Nominal

13 DGND Digital Ground
14 DOUT Serial Data Output, Hi-Z when DXMIT is HIGH

PIN LABEL DESCRIPTION

15 DVALID Data Valid Output. A LOW value indicates valid data is

available in the serial I/O register.
16 RANGE0 Range Control Input 0 (least significant bit)
17 RANGE1 Range Control Input 1
18 RANGE2 Range Control Input 2. (most significant bit)
19 NC No Connection
20 NC No Connection
21 AGND Analog Ground
22 V

REF

External Reference Input, +4.096V Nominal
23 CAP2A External Capacitor for Integrator 2A
24 CAP2A External Capacitor for Integrator 2A
25 CAP2B External Capacitor for Integrator 2B
26 CAP2B External Capacitor for Integrator 2B
27 AGND Analog Ground
28 IN2 Input 2: analog input for Integrators 2A and 2B. The

integrator that is active is set by the CONV input.
29 IN1 Input 1: analog input for Integrators 1A and 1B. The

integrator that is active is set by the CONV input.
30 AGND Analog Ground
31 CAP1B External Capacitor for Integrator 1B
32 CAP1B External Capacitor for Integrator 1B

DDC112

6

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NOISE vs T

INT

1 10000.1 10010

T

INT

(ms)

Noise (ppm of FSR, rms)

0

1

2

3

4

5

6

C

SENSOR

= 50pF

C

SENSOR

= 0pF

Range 5

TYPICAL CHARACTERISTICS

At TA = +25°C, characterization done with Range 5 (250pC), T

INT

= 500µs, V

REF

= +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted.

NOISE vs C

SENSOR

200 8000 1000600400

C

SENSOR

(pF)

Noise (ppm of FSR, rms)

0

10

20

30

40

50

60

70

Range 7

Range 2

Range 1

Range 0

(C

EXT

= 250pF)

NOISE vs INPUT LEVEL

30 4020 9010 10070 80 1050 60

Input Level (% of Full-Scale)

Noise (ppm of FSR, rms)

5

4.5
4

3.5
3

2.5
2

1.5
1

0.5
0

C

SENSOR

= 50pF

C

SENSOR

= 0pF

Range 5

NOISE vs TEMPERATURE

9
8
7
6
5
4
3
2
1
0

–40 –15 10 35 60 85

Temperature (°C)

Noise (ppm of FSR, rms)

Range 1

Range 2

Range 7

Range 3

C

SENSOR

= 0pF

RANGE DRIFT vs TEMPERATURE

–40 –15 10 35 60 85

Temperature (°C)

Range Drift (ppm)

Ranges 1 - 7

(Internal Integration Capacitor)

2000

1500

1000

500

0

–500

–1000

–1500

IB vs TEMPERATURE

25 35 45 55 65 75 85

Temperature (°C)

I

B

(pA)

All Ranges

10

1

0.1

0.01

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TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, characterization done with Range 5 (250pC), T

INT

= 500µs, V

REF

= +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted.

600

POWER-SUPPLY REJECTION RATIO vs FREQUENCY

0 10025 7550

Frequency (KHz)

PSRR (ppm of FSR/V)

0

100

200

300

400

500

INPUT VOS vs RANGE

36

35

34

33

32

31

30

1234567

Range

V

OS

(µV)

DIGITAL SUPPLY CURRENT vs TEMPERATURE

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–40 –15 10 35 60 85

Temperature (°C)

Current (mA)

ANALOG SUPPLY CURRENT vs TEMPERATURE

18
16
14
12
10

8
6
4
2
0

–40 –15 10 35 60 85

Temperature (°C)

Current (mA)

OFFSET DRIFT vs TEMPERATURE

25 35 45 55 65 75 85

Temperature (°C)

Offset Drift (ppm of FSR)

100

50

0

–50

–100

All Ranges

CROSSTALK vs FREQUENCY

0

–20

–40

–60

–80

–100

–120

–140

0 100 200 300 400 500

Frequency (Hz)

Separation (dB)

Separation Measured

Between Inputs 1 and 2

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THEORY OF OPERATION

The basic operation of the DDC112 is illustrated in

Figure 1.
The device contains two identical input channels where each
performs the function of current-to-voltage integration fol­lowed by a multiplexed analog-to-digital (A/D) conversion.
Each input has two integrators so that the current-to-voltage
integration can be continuous in time. The output of the four
integrators are switched to one delta-sigma (∆Σ) converter
via a four input multiplexer. With the DDC112 in the continu­ous integration mode, the output of the integrators from one
side of both of the inputs will be digitized while the other two
integrators are in the integration mode as illustrated in the
timing diagram in Figure 2. This integration and A/D conver­sion process is controlled by the system clock, CLK. With a
10MHz system clock, the integrator combined with the delta­sigma converter accomplishes a single 20-bit conversion in
approximately 220µs. The results from side A and side B of
each signal input are stored in a serial output shift register.

The DVALID

output goes LOW when the shift register

contains valid data.
The digital interface of the DDC112 provides the digital

results via a synchronous serial interface consisting of a data
clock (DCLK), a transmit enable pin (

DXMIT

), a valid data pin

(DVALID

), a serial data output pin (DOUT), and a serial data
input pin (DIN). The DDC112 contains only one A/D con­verter, so the conversion process is interleaved between the
two inputs, as shown in Figure 2. The integration and
conversion process is fundamentally independent of the data
retrieval process. Consequently, the CLK frequency and
DCLK frequencies need not be the same. DIN is only used
when multiple converters are cascaded and should be tied to
DGND otherwise. Depending on T

INT

, CLK, and DCLK, it is
possible to daisy-chain over 100 converters. This greatly
simplifies the interconnection and routing of the digital out­puts in cases where a large number of converters are
needed.

Dual

Switched

Integrator

Dual

Switched

Integrator

∆Σ

Modulator

Digital

Filter

Control

Digital

Input/Output

DVALID
DXMIT
DOUT
DIN

DCLK

RANGE2
RANGE1
RANGE0

TEST

CONV

CLK

CAP1A
CAP1A

CAP1B
CAP1B

CAP2A
CAP2A

CAP2B
CAP2B

IN2

IN1

V

REF

DGNDDV

DD

AGNDAV

DD

Input 1

Input 2

IN1, Integrator A

IN1, Integrator B

IN2, Integrator A

IN2, Integrator B

Conversion in Progress

DVALID

IN1B IN2B IN1A

Integrate

Integrate

Integrate

Integrate

Integrate

Integrate

Integrate

Integrate

IN2A IN1B IN2B IN1A

IN2A

FIGURE 2. Basic Integration and Conversion Timing for the DDC112 (continuous mode).

FIGURE 1. Block Diagram.

DDC112

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DEVICE OPERATION
Basic Integration Cycle

The fundamental topology of the front end of the DDC112 is
a classical analog integrator, as shown in Figure 3. In this
diagram, only Input 1 is shown. This representation of the
input stage consists of an operational amplifier, a selectable
feedback capacitor network (C

F

), and several switches that
implement the integration cycle. The timing relationships of
all of the switches shown in Figure 3 are illustrated in
Figure 4. Figure 4 is used to conceptualize the operation of
the integrator input stage of the DDC112 and should not be
used as an exact timing tool for design. Block diagrams of
the reset, integrate, converter, and wait states of the inte­grator section of the DDC112 are shown in Figure 5. This
internal switching network is controlled externally with the
convert command (CONV), range selection pins (RANGE0­RANGE2), and the system clock (CLK). For the best noise
performance, CONV must be synchronized with the rising
edge of CLK. It is recommended CONV toggle within ±10ns
of the rising edge of CLK.

The noninverting inputs of the integrators are internally
referenced to ground. Consequently, the DDC112 analog
ground should be as clean as possible. The range switches,
along with the internal and external capacitors (C

F

) are
shown in parallel between the inverting input and output of
the operational amplifier. Table I shows the value of the
integration capacitor (C

F

) for each range. At the beginning of

a conversion, the switches S

A/D

, S

INTA

, S

INTB

, S

REF1

, S

REF2

,

and S

RESET

are set (see Figure 4).

At the completion of an A/D conversion, the charge on the
integration capacitor (C

F

) is reset with S

REF1

and

C

F

INPUT RANGE

RANGE2 RANGE1 RANGE0 (pF, typ) (pC, typ)

0 0 0 External Up to 1000

12.5 to 250
0 0 1 12.5 –0.2 to 50
01025 –0.4 to 100
0 1 1 37.5 –0.6 to 150
10050 –0.8 to 200
1 0 1 62.5 –0.1 to 250
11075 –1.2 to 300
1 1 1 87.5 –1.4 to 350

TABLE I. Range Selection of the DDC112.

FIGURE 3. Basic Integrator Configuration for Input 1 Shown with a 250pC (CF = 62.5pF) Input Range.

S

RESET

(see Figures 4 and 5a). This is done during the reset
time. In this manner, the selected capacitor is charged to the
reference voltage, V

REF

. Once the integration capacitor is

charged, S

REF1

, and S

RESET

are switched so that V

REF

is no
longer connected to the amplifier circuit while it waits to begin
integrating (see Figure 5b). With the rising edge on CONV,
S

INTA

closes which begins the integration of Channel A. This
puts the integrator stage into its integrate mode (see
Figure 5c).

Charge from the input signal is collected on the integration
capacitor causing the voltage output of the amplifier to
decrease. A falling edge CONV stops the integration by
switching the input signal from side A to side B (S

INTA

and

S

INTB

). Prior to the falling edge of CONV, the signal on side
B was converted by the A/D converter and reset during the
time that side A was integrating. With the falling edge of
CONV, side B starts integrating the input signal. Now the
output voltage of side A’s operational amplifier is presented
to the input of the ∆Σ A/D converter (see Figure 5d).

50pF

CAP1ACAP1A

25pF

12.5pF

V

REF

RANGE2

RANGE1

RANGE0

To Converter

S

RESET

S

REF2

S

A/D1A

S

INTA

S

REF1

S

INTB

IN1

ESD

Protection

Diode

Input

Current

Integrator A

Integrator B (same as A)

Photodiode

DDC112

10

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FIGURE 5. Diagrams for the Four Configurations of the Front End Integrators of the DDC112.

FIGURE 4. Basic Integrator Timing Diagram as Illustrated in Figure 3.

To Converter

S

RESET

S

REF2

S

A/D

V

REF

S

REF1

S

INT

IN

C

F

a) Reset Configuration

To Converter

S

RESET

S

REF2

S

A/D

V

REF

S

REF1

S

INT

IN

C

F

c) Integrate Configuration

To Converter

S

RESET

S

REF2

S

A/D

V

REF

S

REF1

S

INT

IN

C

F

d) Convert Configuration

To Converter

S

RESET

S

REF2

S

A/D

V

REF

S

REF1

S

INT

IN

C

F

b) Wait Configuration

S

A/D1A

V

REF

Integrator A

Voltage Output

Configuration of

Integrator A

WaitConvert WaitConvertIntegrate

S

REF1

S

REF2

S

INTA

S

INTB

S

RESET

CONV

CLK

Wait

Reset

Wait

Reset

DDC112

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Determining the Integration Capacitor (CF) Value

The value of the integrator’s feedback capacitor, the integra­tion period, and the reference voltage determine the positive
full-scale (+FS) value of the DDC112. The approximate
positive full-scale value of the DDC112 is given by the
following equations:

QIT

QVC

I

VC

T

or

C

IT

V

IN IN INT

FS

REF F

FS

REF F

INT

F

FS

INT

REF

=×
=

(

)

×

=

(

)

×

=

×

096

096

096

.

.

(. )

The

0.96

factor allows the front end integrators to reach full­scale without having to completely swing to ground. The
negative full-scale (–FS) range is approximately 0.4% of the
positive full-scale range. For example, Range 5 has a nomi­nal +FS range of 250pC. The –FS range is then approxi­mately –1pC. This relationship holds for external capacitors
as well and is independent of V

REF

(for V

REF

within the

allowable range, see the Electrical Characteristics table).

Integration Capacitors

There are seven different capacitors available on-chip for
each side of each channel in the DDC112. These internal
capacitors are trimmed in production to achieve the specified
performance for range error of the DDC112. The range
control pins (RANGE0-RANGE2) change the capacitor value
for all four integrators. Consequently, both inputs and both
sides of each input will always have the same full-scale
range unless external capacitors are used.

External integration capacitors may be used instead of the
internal capacitors values by setting [RANGE2-RANGE0 =
000]. The external capacitor pin connections are summa­rized in Table II. Usually, all four external capacitors are
equal in value; however, it is possible to have differing pairs
of external capacitors between Input 1 and Input 2 of the
DDC112. Regardless of the selected value of the capacitor,
it is strongly recommended that the capacitors for sides A
and B be the same.

INTEGRATOR

DDC112U, UK DDC112Y, YK Channel Side

5 and 6 1 and 2 1 A

3 and 4 31 and 32 1 B
23 and 24 23 and 24 2 A
25 and 26 25 and 26 2 B

TABLE II. External Capacitor Connections with Range Con-

figuration of RANGE2-RANGE0 = 000.

Since the range accuracy depends on the characteristics of
the integration capacitor, they must be carefully selected. An
external integration capacitor should have low-voltage coef­ficient, temperature coefficient, memory, and leakage cur­rent. The optimum selection depends on the requirements of
the specific application. Suitable types include chip-on-glass
(COG) ceramic, polycarbonate, polystyrene, and silver mica.

Voltage Reference

The external voltage reference is used to reset the integra­tion capacitors before an integration cycle begins. It is also
used by the ∆Σ converter while the converter is measuring
the voltage stored on the integrators after an integration
cycle ends. During this sampling, the external reference must
supply charge needed by the ∆Σ converter. For an integration
time of 500µs, this charge translates to an average V

REF

current of approximately 150µA. The amount of charge
needed by the ∆Σ converter is independent of the integration
time; therefore, increasing the integration time lowers the
average current. For example, an integration time of 1000µs
lowers to average V

REF

current to 75µA.

It is critical that V

REF

be stable during the different modes of
operation in Figure 5. The ∆Σ converter measures the volt­age on the integrator with respect to V

REF

. Since the

integrator’s capacitors are initially reset to V

REF

, any droop in

V

REF

from the time the capacitors are reset to the time when
the converter measures the integrator’s output will introduce
an offset. It is also important that V

REF

be stable over longer

periods of time as changes in V

REF

correspond directly to

changes in the full-scale range. Finally, V

REF

should intro-

duce as little additional noise as possible.
For reasons mentioned above, it is strongly recommended

that the external reference source be buffered with an
operational amplifier, as shown in Figure 6. In this circuit,
the voltage reference is generated by a 4.096V reference.

FIGURE 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the DDC112.

0.10µF

+5V

10kΩ

10µF

4

3

3

2

1

2

7

6

+

0.10µF

0.1µF

10µF

+

OPA350

To V

REF

Pin 22 of

the DDC112

REF3040

+5V

0.47µF

EXTERNAL CAPACITOR PINS

DDC112

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CLK = 10MHz CLK = 15MHz

SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS

t

1

Setup Time for Test Mode Enable 100 100 ns

t

2

Setup Time for Test Mode Disable 100 100 ns

t

3

Hold Time for Test Mode Enable 100 100 ns

t

4

From Rising Edge of TEST to the Edge of CONV 5.4 3.6 µs

while Test Mode Enabled

t

5

Rising Edge to Rising Edge of TEST 5.4 3.6 µs

A low-pass filter to reduce noise connects it to an opera­tional amplifier configured as a buffer. This amplifier should
have a unity-gain bandwidth greater than 4MHz, low noise,
and input/output common-mode ranges that support V

REF

.
Following the buffer are capacitors placed close to the
DDC112 V

REF

pin. Even though the circuit in Figure 6 might
appear to be unstable due to the large output capacitors, it
works well for most operational amplifiers. It is NOT recom­mended that series resistance be placed in the output lead
to improve stability since this can cause droop in V

REF

which

produces large offsets.

DDC112 Frequency Response

The frequency response of the DDC112 is set by the front end
integrators and is that of a traditional continuous time integra­tor, as shown in Figure 7. By adjusting T

INT

, the user can
change the 3dB bandwidth and the location of the notches in
the response. The frequency response of the ∆Σ converter that
follows the front end integrator is of no consequence because
the converter samples a held signal from the integrators. That
is, the input to the ∆Σ converter is always a DC signal. Since
the output of the front end integrators are sampled, aliasing can
occur. Whenever the frequency of the input signal exceeds
one-half of the sampling rate, the signal will

fold

back down to

lower frequencies.

Test Mode

When TEST is used, pins IN1 and IN2 are grounded and

packets

of approximately 13pC charge are transferred to the

FIGURE 8. Timing Diagram of the Test Mode of the DDC112.

TABLE III. Timing for the DDC112 in the Test Mode.

integration capacitors of both Input 1 and Input 2. This fixed
charge can be transferred to the integration capacitors either
once during an integration cycle or multiple times. In the case
where multiple packets are transferred during one integration
period, the 13pC charge is additive. This mode can be used
in both the continuous and noncontinuous mode timing. The
timing diagrams for test mode are shown in Figure 8. The top
three lines in Figure 8 define the timing when one packet of
13pC is sent to the integration capacitors. The bottom three
lines define the timing when multiple packets are sent to the
integration capacitors.

FIGURE 7. Frequency Response of the DDC112.

0

–10

–20

–30

–40

–50

0.1

T

INT

100
T

INT

1

T

INT

10

T

INT

Frequency

Gain (dB)

t

1

t

1

t

3

t

4

t

4

t

5

t

2

Integrate B

Action

CONV

TEST

Action

CONV

TEST

Integrate A

Test Mode Disabled

13pC into B 13pC into A 13pC into B 13pC into A

Test Mode Disabled

Test Mode Enabled

Integrate B Integrate A

Integrate B Integrate A

Test Mode Disabled

13pC into B 26pC into A 39pC into B 52pC into A

Test Mode Disabled

Test Mode Enabled

Integrate B Integrate A

t

2

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TEST and CONV work together to implement this feature.
The test mode is entered when TEST is HIGH prior to a
CONV edge. At that point, a CONV edge triggers the ground­ing of the analog inputs and the switching of 13pC packets
of charge onto the integration capacitors. If TEST is kept
HIGH through at least two conversions (that is, a rise and fall
of CONV), all four integrators will be charged with a 13pC
packet. At the end of each conversion, the voltage at the
output of the integrators is digitized as discussed in the

Continuous and Non-Continuous Operational Modes

section
of this data sheet. The test mode is exited when TEST is
LOW and a CONV edge occurs.

Once the test mode is entered as described above, TEST
can cycle as many times as desired. When this is done,
additional 13pC packets are added on the rising edge of
TEST to the existing charge on the integrator capacitors.
Multiple charge packets can be added in this way as long as
the TEST pin is not LOW when CONV toggles.

DIGITAL ISSUES

The digital interface of the DDC112 provides the digital results
via a synchronous serial interface consisting of a data clock
(DCLK), a transmit enable pin (

DXMIT

), a valid data pin

(DVALID

), a serial data output pin (DOUT), and a serial data
input pin (DIN). The DDC112 contains only one A/D converter,
so the conversion process is interleaved between the two
inputs (see Figure 2). The integration and conversion process
is fundamentally independent of the data retrieval process.
Consequently, the CLK frequency and DCLK frequencies
need not be the same. DIN is used when multiple converters
are cascaded. Cascading or

daisy-chaining

greatly simplifies
the interconnection and routing of the digital outputs in cases
where a large number of converters are needed. Refer to the

Cascading Multiple Converters

section of this data sheet for

more detail.
The conversion rate of the DDC112 is set by a combination of

the integration time (determined by the user) and the speed of
the A/D conversion process. The A/D conversion time is
primarily a function of the system clock (CLK) speed. One
A/D conversion cycle encompasses the conversion of two
signals (one from each input of the DDC112) and reset time
for each of the integrators involved in the two conversions. In
most situations, the A/D conversion time is shorter than the
integration time. If this condition exists, the DDC112 will
operate in the continuous mode. When the DDC112 is in the
continuous mode, the sensor output is continuously integrated
by one of the two sides of each input.

In the event that the A/D conversion takes longer than the
integration time, the DDC112 will switch into a noncontinu­ous mode. In noncontinuous mode, the A/D converter is not
able to keep pace with the speed of the integration process.
Consequently, the integration process is periodically halted
until the digitizing process catches up. These two basic
modes of operation for the DDC112—continuous and non­continuous modes—are described in the

Continuous and

Noncontinuous Operational Modes

section of this data sheet.

Continuous and Non-Continuous
Operational Modes

The state diagram of the DDC1 12 is shown in Figure 9. In all,
there are 8 states. Table IV provides a brief explanation of
each of the states.

Int A/Meas B

Cont

5

CONV • mbsy

CONV • mbsy

CONV • mbsy

CONV • mbsy

CONV • mbsy

CONV • mbsy

CONV

CONV

Int B/Meas A

Cont

4

Ncont

1

Ncont

2

Int A
Cont

3

Ncont

8

Ncont

7

Int B
Cont

6

CONV

CONV

mbsy

mbsy

FIGURE 9. State Diagram.

Four signals are used to control progression around the state
diagram: CONV and mbsy and their complements. The state
machine uses the level as opposed to the edges of CONV to
control the progression. mbsy is an internally-generated
signal not available to the user. It is active whenever a
measurement/reset/auto-zero (m/r/az) cycle is in progress.

STATE MODE DESCRIPTION

1 Ncont Complete m/r/az of side A, then side B (if previous

state is state 4). Initial power-up state when CONV

is initially held HIGH.
2 Ncont Prepare side A for integration.
3 Cont Integrate on side A.
4 Cont Integrate on side B; m/r/az on side A.
5 Cont Integrate on side A; m/r/az on side B.
6 Cont Integrate on side B.
7 Ncont Prepare side B for integration.
8 Ncont Complete m/r/az of side B, then side A (if previous

state is state 5). Initial power-up state when CONV

is initially held LOW.

TABLE IV. State Descriptions.

DDC112

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T ABLE V . Timing Specifications Generalized in CLK Periods.

SYMBOL DESCRIPTION VALUE (CLK periods)

t

6

Cont mode m/r/az cycle. 4794

t

7

Cont mode data ready. 4212 (t

INT

> 4794)

4212 ±3(t

INT

= 4794)

t

8

1st ncont mode data ready. 4212 ±3

t

9

2nd ncont mode data ready. 4548

t

10

Ncont mode m/r/az cycle. 9108

432154

Integrate BIntegrate A Integrate A Integrate B

m/r/az A m/r/az B m/r/az A

CONV

State

mbsy

m/r/az
Status

Integration

Status

DVALID

t

6

t

7

t = 0

Power-Up

Side A

Data

Side B

Data

Side A

Data

FIGURE 10. Continuous Mode Timing (CONV HIGH at power-up).

SYMBOL

DESCRIPTION VALUE (CLK = 10MHz) VALUE (CLK = 15MHz)

t

6

Cont mode m/r/az cycle. 479.4µs 319.6µs

t

7

Cont mode data ready. 421.2µs(T

INT

> 479.4µs) 280.8µs(T

INT

> 319.6µs)

421.2 ±0.3µs(T

INT

= 479.4µs) 280.8 ±0.2µs(T

INT

= 319.6µs)

During the cont mode, mbsy is not active when CONV
toggles. The non-integrating side is always ready to begin
integrating when the other side finishes its integration. Con­sequently, keeping track of the current status of CONV is all
that is needed to know the current state. Cont mode opera­tion corresponds to states 3-6. Two of the states, 3 and 6,
only perform an integration (no m/r/az cycle).

mbsy becomes important when operating in the ncont mode;
states 1, 2, 7, and 8. Whenever CONV is toggled while mbsy
is active, the DDC112 will enter or remain in either ncont
state 1 (or 8). After mbsy goes inactive, state 2 (or 7) is
entered. This state prepares the appropriate side for integra­tion. As mentioned above, in the ncont states, the inputs to
the DDC112 are grounded.

One interesting observation from the state diagram is that the
integrations always alternate between sides A and B. This
relationship holds for any CONV pattern and is independent
of the mode. States 2 and 7 insure this relationship during the
ncont mode.

When power is first applied to the DDC112, the beginning
state is either 1 or 8, depending on the initial level of CONV.
For CONV held HIGH at power-up, the beginning state is 1.
Conversely, for CONV held LOW at power-up, the beginning
state is 8. In general, there is a symmetry in the state
diagram between states 1-8, 2-7, 3-6, and 4-5. Inverting
CONV results in the states progressing through their sym­metrical match.

TIMING EXAMPLES
Cont Mode

A few timing diagrams will now be discussed to help illustrate
the operation of the state machine. These are shown in
Figures 10 through 19. Table V gives generalized timing
specifications in units of CLK periods. Values in µs for

Table V can be easily found for a given CLK. For example,
if CLK = 10MHz, then a CLK period = 0.1µs. t

6

in Table V

would then be 479.4µs.

Figure 10 shows a few integration cycles beginning with
initial power-up for a cont mode example. The top signal is
CONV and is supplied by the user. The next line indicates the
current state in the state diagram. The following two traces
show when integrations and measurement cycles are under­way. The internal signal mbsy is shown next. Finally, DVALID
is given. As described in the data sheet, DVALID goes active
LOW when data is ready to be retrieved from the DDC112.
It stays LOW until

DXMIT

is taken LOW by the user. In Figure
10 and the following timing diagrams, it is assumed that

DXMIT

it taken LOW soon after DVALID goes LOW. The text

below the DVALID

pulse indicates the side of the data and
arrows help match the data to the corresponding integration.
The signals shown in Figures 10 through 19 are drawn at
approximately the same scale.

In Figure 10, the first state is ncont state 1. The DDC112
always powers up in the ncont mode. In this case, the first
state is 1 because CONV is initially HIGH. After the first two
states, cont mode operation is reached and the states begin
toggling between 4 and 5. From now on, the input is being
continuously integrated, either by side A or side B. The time
needed for the m/r/az cycle, t

6

, is the same time that

DDC112

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determines the boundary between the cont and ncont modes
described earlier in the Overview section. DVALID

goes

LOW after CONV toggles in time t

7

, indicating that data is
ready to be retrieved. As shown in Figure 10, there are two
values for t

7

, depending on T

INT

. The reason for this will be

discussed in the Special Considerations section.

Figure 11 shows the result of inverting the logic level of
CONV. The only difference is in the first three states. After­wards, the states toggle between 4 and 5 just as in the
previous example. Figure 12 shows the timing diagram of the
internal operations occurring during continuous mode opera­tion.

FIGURE 11. Continuous Mode Timing (CONV LOW at power-up).

567845

Integrate AIntegrate B Integrate B Integrate A

m/r/az B m/r/az A m/r/az B

CONV

State

Integration

Status

m/r/az
Status

mbsy

DVALID

t

6

t

7

t = 0

Power-Up

Side B

Data

Side A

Data

Side B

Data

FIGURE 12. Timing Diagram of the Internal Operation in Continuous Mode of the DDC112.

t

12

t

12

t

14

t

13

T

INT

T

INT

End Integration Side A
Start Integration Side B

Side A

Side A

Data Ready

Side B

Data Ready

Side B

Side A Side B

Side A

End Integration Side B
Start Integration Side A

End Integration Side A
Start Integration Side B

CONV

DVALID

A/D Conversion

Input 1 (Internal)

A/D Conversion

Input 2 (Internal)

CLK = 10MHz CLK = 15MHz

SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS

T

INT

Integration Period (continuous mode) 500 1,000,000 333 1,000,000 µs

t

12

A/D Conversion Time (internally controlled) 202.2 134.8 µs

t

13

A/D Conversion Reset Time (internally controlled) 13.2 8.8 µs

t

14

Integrator and A/D Conversion Reset Time 61.8 41.2 µs

(internally controlled)

TABLE VI. Timing for the Internal Operation in the Continuous Mode.

DDC112

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FIGURE 13. Non-Continuous Mode Timing.

Ncont Mode

Figure 13 illustrates operation in the ncont mode. The
integrations come in pairs (that is, sides A/B or sides B/A)
followed by a time during which no integrations occur.
During that time, the previous integrations are being mea­sured, reset and auto-zeroed. Before the DDC112 can
advance to states 3 or 6, both sides A and B must be
finished with the m/r/az cycle which takes time t

10

. When the

m/r/az cycles are completed, time t

11

is needed to prepare
the next side for integration. This time is required for the
ncont mode because the m/r/az cycle of the ncont mode is
slightly different from that of the cont mode. After the first
integration ends, DVALID

goes LOW in time t8. This is the

same time as in the cont mode. The second data will be
ready in time t

9

after the first data is ready. One result of the
naming convention used in this application bulletin is that
when the DDC112 is operating in the

ncont mode

, it passes

through both

ncont mode states

and

cont mode states

. For
example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4, 1,
2, 3, 4...where 3 and 4 are cont mode states.

Ncont mode

by definition means that for some portion of the time, neither
side A nor B is integrating. States that perform an integration
are labeled

cont mode states

while those that do not are

called

ncont mode states

. Since integrations are performed
in the ncont mode, just not continuously, some cont mode
states must be used in an ncont mode state pattern.

SYMBOL

DESCRIPTION VALUE (CLK = 10MHz) VALUE (CLK = 15MHz)

t

8

1st ncont mode data ready. 421.2 ±0.3µs 280.8 ±0.2µs

t

9

2nd ncont mode data ready. 454.8µs 303.2µs

t

10

Ncont mode m/r/az cycle. 910.8µs 607.2µs

t

11

Prepare side for integration. ≥ 24.0µs ≥ 24.0µs

23134 4 1 2

Int BInt AInt BInt A

m/r/az Bm/r/az A

m/r/az A m/r/az B

CONV

State

mbsy

m/r/az

Status

Integration

Status

DVALID

t

10

t

9

t

11

t

8

Side A

Data

Side B

Data

Side A

Data

Side B

Data

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CLK = 10MHz CLK = 15MHz

SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS

T

INT

Integration Time (noncontinuous mode) 50 1,000,000 50 1,000,000 µs

t

12

A/D Conversion Time (internally controlled) 202.2 134.8 µs

t

13

A/D Conversion Reset Time (internally controlled) 13.2 8.8 µs

t

15

Integrator and A/D Conversion Reset Time 37.8 25.2 µs

(internally controlled)

t

16

Total A/D Conversion and Rest Time 910.8 607.2 µs

(internally controlled)

t

17

Release Time 24 24 µs

FIGURE 14. Conversion Detail for the Internal Operation of the Non-Continuous Mode with Side A Integrated First.

t

12

T

INT

T

INT

t

16

t

12

t

13

t

15

t

17

Release

State

End Integration Side A
Start Integration Side B

End Integration Side B

Wait State

Side A

Data Ready

Side B

Data Ready

Start Integration Side A

Start Integration Side A

CONV

A/D Conversion

Input 1

A/D Conversion

Input 2

DVALID

t

12

T

INT

T

INT

t

16

t

12

t

13

t

15

t

17

CONV

A/D Conversion

Input 1

A/D Conversion

Input 2

DVALID

Release

State

End Integration Side B
Start Integration Side A

End Integration Side A

Wait State

Side B

Data Ready

Side A

Data Ready

Start Integration Side B

Start Integration Side B

FIGURE 15. Internal Operation Timing Diagram of the Non-Continuous Mode with Side B Integrated First.

TABLE VII. Internal Timing for the DDC112 in the Non-Continuous Mode.

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FIGURE 16. Equivalent CONV Signals in Non-Continuous Mode.

FIGURE 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal.

CONV1

CONV2

23134 4 1 2

State

mbsy

CONV

DVALID

23134 41

State

Integration

Status

mbsy

Int BInt AInt B

Side A

Data

Side B

Data

Side A

Data

Int A

Looking at the state diagram, one can see that the CONV
pattern needed to generate a given state progression is not
unique. Upon entering states 1 or 8, the DDC1 12 remains in
those states until mbsy goes LOW, independent of CONV.
As long as the m/r/az cycle is underway, the state machine
ignores CONV (see Figure 9). The top two signals are
different CONV patterns that produce the same state.
This feature can be a little confusing at first, but it does allow
flexibility in generating ncont mode CONV patterns. For
example, the DDC112 Evaluation Fixture operates in the
ncont mode by generating a square wave with pulse width
< t

6

. Figure 17 illustrates operation in the ncont mode using

a 50% duty cycle CONV signal with T

INT

= 1620 CLK
periods. Care must be exercised when using a square wave
to generate CONV. There are certain integration

times that

must be avoided since they produce very short intervals for
state 2 (or state 7 if CONV is inverted). As seen in the state
diagram, the state progresses from 2 to 3 as soon as CONV
is HIGH. The state machine does not insure that the duration
of state 2 is long enough to properly prepare the next side
for integration (t

11

). This must be done by the user with
proper timing of CONV. For example, if CONV is a square
wave with T

INT

= 3042 CLK periods, state 2 will only be 18

CLK periods long, therefore, t

11

will not be met.

DDC112

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CONV

4214

Non-Continuous Continuous

33

State

mbsy

m/r/az
Status

Integration

Status

m/r/az A m/r/az B m/r/az A

Int BInt A Integrate A Integrate B

FIGURE 18. Changing from Continuous Mode to Non-Continuous Mode.

FIGURE 19. Changing from Non-Continuous Mode to Continuous Mode.

CONV

8745

Continuous Non-Continuous

5 65

State

Integration

Status

m/r/az

Status

mbsy

m/r/az B m/r/az A m/r/az B m/r/az A m/r/az B

Integrate A Integrate B Int AInt A Int B

Changing Between Modes

Changing from the cont to ncont mode occurs whenever
T

INT

< t6. Figure 18 shows an example of this transition.
In this figure, the cont mode is entered when the integration
on side A is completed before the m/r/az cycle on side B is
complete. The DDC112 completes the measurement on
sides B and A during states 8 and 7 with the input signal
shorted to ground. Ncont integration begins with state 6.

Changing from the ncont to cont mode occurs when T

INT

is

increased so that T

INT

is always ≥ t6 (see Figure 14). With a

longer T

INT

, the m/r/az cycle has enough time to finish before
the next integration begins and continuous integration of the
input signal is possible. For the special case of the very first
integration when changing to the cont mode, T

INT

can be

< t

6

. This is allowed because there is no simultaneous

m/r/az cycle on the side B during state 3—

there is no need

to wait for it to finish before ending the integration on side A.

DDC112

20

SBAS085B

www.ti.com

SPECIAL CONSIDERATIONS

NCONT MODE INTEGRATION TIME

The DDC112 uses a relatively fast clock. For CLK = 10MHz,
this allows T

INT

to be adjusted in steps of 100ns since CONV
should be synchronized to CLK. However, for the internal
measurement, reset and auto-zero operations, a slower
clock is more efficient. The DDC112 divides CLK by six and
uses this slower clock with a period of 600ns to run the m/r/
az cycle and data ready logic.

Because of the divider, it is possible for the integration time
to be a non-integer number of slow clock periods.

For

example, if T

INT

= 5000 CLK periods (500µs for CLK = 10MHz),
there will be 833 1/3 slow clocks in an integration period. This
non-integer relationship between T

INT

and the slow clock
period causes the number of rising and falling slow clock
edges within an integration period to change from integration
to integration. The digital coupling of these edges to the
integrators will in turn change from integration to integration
which produces noise. The change in the clock edges is not
random, but will repeat every 3 integrations. The coupling
noise on the integrators appears as a tone with a frequency
equal to the rate at which the coupling repeats.

To avoid this problem in cont mode, the internal slow clock
is shut down after the m/r/az cycle is complete when it is no
longer needed. It starts up again just after the next integra­tion begins. Since the slow clock is always off when CONV
toggles, the same number of slow clock edges fall within an
integration period regardless of its length. Therefore,
T

INT

≥ 4794 CLK periods will not produce the coupling

problem described above.
For the ncont mode however, the slow clock must always be

left running. The m/r/az cycle is not completed before an
integration ends. It is then possible to have digital coupling to
the integrators. The digital coupling noise depends heavily on
the layout of the printed circuit board used for the DDC112.
For solid grounds and power supplies with good bypassing,
it is possible to greatly reduce the coupling. However, for
ensuring the best performance in the ncont mode, the inte­gration time should be chosen to be an integer multiple of
1/(2f

SLOWCLOCK

). For CLK = 10MHz, the integration time

should be an integer multiple of 300ns—T

INT

= 100µs is not.

A better choice would be T

INT

= 99µs.

DATA READY

The DVALID signal which indicates that data is ready is
generated using the internal slow clock. The phase relation­ship between this clock and CLK is set when power is first
applied and is random. Since CONV is synchronized with
CLK, it will have a random phase relationship with respect to
the slow clock. When T

INT

> t6, the slow clock will temporarily
shut down as described above. This shutdown process
synchronizes the internal clock with CONV so that the time
between when CONV toggles to when

DVALID

goes LOW

(t

7

and t8) is fixed.

For T

INT

≤ t6, the internal slow clock, is not allowed to shut
down and the synchronization never occurs. Therefore, the
time between CONV toggling and DVALID

indicating data is
ready has uncertainty due to the random phase relationship
between CONV and the slow clock. This variation is
±1/(2f

SLOWCLOCK

) or ±3/f

CLK

. The timing to the second DVALID
in the ncont mode will not have a variation since it is
triggered off the first data ready (t

9

) and both are derived

from the slow clock.
Polling DVALID

to determine when data is ready eliminates
any concern about the variation in timing since the readback
is automatically adjusted as needed. If the data readback is
triggered off the toggling of CONV directly (instead of poll­ing), then waiting the maximum value of t

7

or t8 insures that

data will always be ready before readback occurs.

Data Retrieval

In the continuous and noncontinuous modes of operation,
the data from the last conversion is available for retrieval with
the falling edge of DVALID

(see Figure 22). The falling edge

of

DXMIT

in combination with the data clock (DCLK) will
initiate the serial transmission of the data from the DDC112.
Typically, data is retrieved from the DDC112 as soon as

DVALID

falls and completed before the next CONV transition
from HIGH to LOW or LOW to HIGH occurs. If this is not the
case, care should be taken to stop activity on DCLK and
consequently DOUT by at least 10µs around a CONV tran­sition. If this caution is ignored it is possible that the integra­tion that is being initiated by CONV will have additional noise
introduced.

The serial output data at DOUT is transmitted in Straight
Binary Code per Table VIII. An output offset has been built
into the DDC112 to allow for the measurement of input
signals near and below zero. Board leakage up to

≈ –0.4%

of the positive full-scale can be tolerated before the digital
output clips to all zeroes.

Cascading Multiple Converters

Multiple DDC112 units can be connected in serial or parallel
configurations, as illustrated in Figures 20 and 21.

DOUT can be used with DIN to

daisy-chain

several DDC112
devices together to minimize wiring. In this mode of opera­tion, the serial data output is shifted through multiple DDC112s,
as illustrated in Figure 20.

R

PULLUP

prevents DIN from floating when

DXMIT

is HIGH.
Care should be taken to keep the capacitive load on DOUT
as low as possible when running CLK=15MHz.

CODE INPUT SIGNAL

1111 1111 1111 1111 1111 FS
1111 1111 1111 1111 1110 FS – 1LSB
0000 0001 0000 0000 0001 +1LSB
0000 0001 0000 0000 0000 Zero
0000 0000 0000 0000 0000 –0.4% FS

TABLE VIII. Straight Binary Code Table.

DDC112

21

SBAS085B

www.ti.com

FIGURE 20. Daisy-Chained DDC112s.

IN1

IN2

DCLK
DXMIT
DIN

DVALID

DOUT

DDC112

“F”“E”

Sensor “F” Sensor “E”

IN1

IN2

DCLK
DXMIT
DIN

DVALID

DOUT

DDC112

“D”“C”

Sensor “D” Sensor “C”

IN1

IN2

DCLK
DXMIT
DIN

DVALID

DOUT

Data Retrieval
Outputs

DDC112

“B”“A”

Sensor “B” Sensor “A”

R

P

R

P

R

P

Data Retrievel

Inputs

40 Bits 40 Bits 40 Bits

FIGURE 21. DDC112 in Parallel Operation.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

18

Propagation Delay from Rising Edge of CLK to DVALID LOW 30 ns

t

19

Propagation Delay from DXMIT LOW to DVALID HIGH 30 ns

t

20

Setup Time from DCLK LOW TO DXMIT LOW 20 ns

t

21

Propagation Delay from DXMIT LOW to Valid DOUT 30 ns

t

22

Hold Time that DOUT is Valid After Falling Edge of DCLK 5 ns

t

23

Propagation Delay from DXMIT HIGH to DOUT Disabled 30 ns

t

22A

(1)

Propagation Delay from Falling Edge of DCLK to Valid DOUT 25 ns

t

22B

(2)

Propagation Delay from Falling Edge of DCLK to Valid DOUT 30 ns

NOTES: (1) Applies to DDC112UK, YK only, with a maximum load of one DDC112UK, YK DIN (4pF typical) with an additional load of (5pF 100kΩ). (2) Applies
to DDC112U, Y only, with a maximum load of one DDC112U,Y DIN (4pF typical) with an additional load of (5pF 100kΩ).

FIGURE 22. Digital Interface Timing Diagram for Data Retrieval From a Single DDC112.

TABLE IX. Timing for the DDC112 Data Retrieval.

DIN

DIN

DIN

DOUT

DXMIT

DDC112

Data Output

DDC112

DDC112

Enable

DOUT

DXMIT

DOUT

DXMIT

t

18

t

19

t

20

t

21

t

22

t

23

Input 2

Bit 1

Input 2
Bit 20

Input 1

Bit 1

Input 1

Bit 20

MSB LSB MSB

Output Disabled

Output Enabled

Output Disabled

LSB

CLK

DVALID

DXMIT

DCLK

(1)

DOUT

NOTE: (1) Disable DCLK (preferably hold LOW) when DXMIT is HIGH.

DDC112

22

SBAS085B

www.ti.com

RETRIEVAL

BEFORE

CONV TOGGLES

(CONTINUOUS MODE)

This is the most straightforward method. Data retrieval be­gins soon after DVALID

goes LOW and finishes before
CONV toggles, see Figure 24. For best performance, data
retrieval must stop t

28

before CONV toggles. This method is
the most appropriate for longer integration times. The maxi­mum time available for readback is T

INT

– t27 – t28.
For DCLK and CLK = 10MHz, the maximum number of
DDC112s that can be daisy-chained together is:

Ts

INT

DCLK

– .431 240µ

τ

Where τ

DCLK

is the period of the data clock. For example, if

T

INT

= 1000µs and DCLK = 10MHz, the maximum number of

DDC112s is:

1000 431 2

40 100

142 2 142 112

µµ

=→

ss

ns

DDC s

– .

()( )

.

RETRIEVAL

AFTER

CONV TOGGLES

(CONTINUOUS MODE)

For shorter integration times, more time is available if data
retrieval begins after CONV toggles and ends before the new
data is ready. Data retrieval must wait t

29

after CONV toggles
before beginning. Figure 25 shows an example of this. The
maximum time available for retrieval is t

27

– t29 – t

26

(421.2µs – 10µs – 2µs for CLK = 10MHz), regardless of T

INT

.
The maximum number of DDC112s that can be daisy­chained together is:

409 240. µs

DCLK

τ

For DCLK = 10MHz, the maximum number of DDC112s is

102.

FIGURE 23. Timing Diagram When Using the DIN Function of the DDC112.

t

18

t

14

t

20

t

21

t

22

t

23

t

24

t

25

Output Disabled

Output Enabled

Output Disabled

CLK

DVALID

DXMIT

DCLK

(1)

DIN

Input A

Bit 1

Input E

Bit 20

Input F

Bit 1

Input F

Bit 20

MSB

Output Disabled

Output Enabled

LSB LSB Output DisabledMSB

DOUT

NOTE: (1) Disable DCLK (preferably LOW) when DXMIT is HIGH.

t

26

t

22A, t22B

TABLE X. Timing for the DDC112 Data Retrieval Using DIN.

CLK = 10MHz CLK = 15MHz

SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS

t

24

Set-Up Time From DIN to Rising Edge of DCLK 10 5 ns

t

25

Hold Time For DIN After Rising Edge of DCLK 10 10 ns

t

26

Hold Time for DXMIT HIGH Before Falling 2 1.33 µs

Edge of DVALID

DDC112

23

SBAS085B

www.ti.com

CLK = 10MHz CLK = 15MHz

SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS

t

27

Cont Mode Data Ready 421.2 280.8 µs

t

28

Data Retrieval Shutdown Before Edge of CONV 10 10 µs

••••••

••••••

Side B

Data

Side A

Data

T

INT

T

INT

t

27

t

28

CONV

DVALID

DXMIT

DCLK

DOUT

FIGURE 24. Readback

Before

CONV Toggles.

T

INT

t

27

t

29

t

26

T

INT

T

INT

••• ••• •••

••• ••• •••

Side A

Data

Side B

Data

Side A

Data

CONV

DVALID

DXMIT

DCLK

DOUT

FIGURE 25. Readback

After

CONV Toggles.

CLK = 10MHz CLK = 15MHz

SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS

t

26

Hold Time for DXMIT HIGH Before Falling Edge 2 1.33 µs

of DVALID

t

27

Cont Mode Data Ready 421.2 280.8 µs

t

29

Data Retrieval Start-Up After Edge of CONV 10 10 µs

DDC112

24

SBAS085B

www.ti.com

RETRIEVAL

BEFORE

AND

AFTER

CONV

TOGGLES (CONTINUOUS MODE)

For the absolute maximum time for data retrieval, data can
be retrieved

before and after

CONV toggles. Nearly all of T

INT

is available for data retrieval. Figure 26 illustrates how this is
done by combining the two previous methods. You must
pause the retrieval during CONV toggling to prevent digital
noise, as discussed previously, and finish before the next
data is ready. The maximum number of DDC112s that can
be daisy-chained together is:

Tss

INT

DCLK

––20 2

40

µµ

τ

For T

INT

= 500µs and DCLK = 10MHz, the maximum number

of DDC112s is 119.

RETRIEVAL: NONCONTINUOUS MODE

Retrieving in noncontinuous mode is slightly different as
compared with the continuous mode. As shown in Figure 27
and described in detail in Application Bulletin SBAA024

(available for download at www.ti.com), DVALID

goes LOW

in time t

30

after the first integration completes. If T

INT

is

shorter than this time, all of t

31

is available to retrieve data

before the other side’s data is ready. For T

INT

> t30, the first
integration’s data is ready before the second integration
completes. Data retrieval must be delayed until the second
integration completes leaving less time available for retrieval.
The time available is t

31

– (T

INT

– t30). The second integration’s
data must be retrieved before the next round of integrations
begin. This time is highly dependent on the pattern used to
generate CONV. As with the continuous mode, data retrieval
must halt before and after CONV toggles (t

28

and t29) and be

completed before new data is ready (t

26

).

POWER-UP SEQUENCING

Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they should
never exceed AV

DD

or DVDD. The level of CONV at power­up is used to determine which side (A or B) will be integrated
first. Before integrations can begin though, CONV must
toggle; see Figure 28.

••• ••• ••• ••• ••• •••

••• ••• •••

••• ••• •••

DCLK

DXMIT

DVALID

CONV

DOUT

Side B

Data

Side A

Data

T

INT

t

29

t

28

t

26

T

INT

T

INT

FIGURE 26. Readback

Before and After

CONV Toggles.

CLK = 10MHz CLK = 15MHz

SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS

t

26

Hold Time for DXMIT HIGH Before Falling 2 1.33 µs

Edge of DVALID

t

28

Data Retrieval Shutdown Before Edge of CONV 10 10 µs

t

29

Data Retrieval Start-Up After dge of CONV 10 10 µs

DDC112

25

SBAS085B

www.ti.com

••• •••

••• •••

T

INT

T

INT

t

30

T

INT

T

INT

t

31

Side A

Data

Side B

Data

CONV

DVALID

DXMIT

DCLK

DOUT

FIGURE 27. Readback in Noncontinuous Mode.

FIGURE 28. Timing Diagram at Power-Up of the DDC112.

t

32

t

33

Integrate Side A

Integrate Side B

Power-Up

Initialization

Release State

Start

Integration

CONV

(HIGH at power-up)

CONV

(LOW at power-up)

Power Supplies

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

32

Power-On Initialization Period 50 µs

t

33

From Release Edge to Integration Start 50 µs

TABLE XI. Timing for the DDC112 Power-Up Sequence.

CLK = 10MHz CLK = 15MHz

SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS

t

30

1st Ncont Mode Data Ready (see SBAA024) 421.1 ±0.3 280.8 µs

t

31

2nd Ncont Mode Data Ready (see SBAA024) 454.8 303.2 µs

LAYOUT

Power Supplies and Grounding

Both AVDD and DVDD should be as quiet as possible. It is
particularly important to eliminate noise from AV

DD

that is
non-synchronous with the DDC112 operation. Figure 29
illustrates two acceptable ways to supply power to the
DDC112. The first case shows two separate +5V supplies for
AV

DD

and DVDD. In this case, each +5V supply of the
DDC112 should be bypassed with 10µF solid tantalum ca­pacitors and 0.1µF ceramic capacitors. The second case

shows the DV

DD

power supply derived from the AVDD supply
with a < 10Ω isolation resistor. In both cases, the 0.1µF
capacitors should be placed as close to the DDC112 pack­age as possible.

Shielding Analog Signal Paths

As with any precision circuit, careful printed circuit layout will
ensure the best performance. It is essential to make short,
direct interconnections and avoid stray wiring capacitance—
particularly at the analog input pins. Digital signals should be
kept as far from the analog input signals as possible on the
PC board.

DDC112

26

SBAS085B

www.ti.com

FIGURE 30. Recommended Shield for DDC112U Layout

Design.

FIGURE 29. Power Supply Connection Options.

DDC112

0.1µF

< 10Ω

10µF

V

S

+

One +5V Supply

AV

DD

DV

DD

AV

DD

DV

DD

DDC112

0.1µF

0.1µF

0.1µF

10µF

V

S

+

Separate +5V Supplies

10µF

V

DD

+

Input shielding practices should be taken into consideration
when designing the circuit layout for the DDC112. The inputs
to the DDC112 are high impedance and extremely sensitive
to extraneous noise. Leakage currents between the PCB
traces can exceed the input bias current of the DDC112 if
shielding is not implemented. Figure 30 illustrates an accept­able approach to this problem. A PC ground plane is placed
around the inputs of the DDC112. This shield helps minimize
coupled noise into the input pins. Additionally, the pins that

DDC112U

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Digital I/O

and

Digital Power

Digital I/O

and

Digital Power

Shield

external

caps when

used

Analog
Ground

Analog

Power

Shield

external

caps when

used

Analog

Ground

Analog

Ground

IN1 IN2

Analog

Ground

are used for the external integration capacitors should be
guarded by a ground plane when the external capacitors are
used.

The approach above reduces leakage affects by surrounding
these sensitive pins with a low impedance analog ground.
Leakage currents from other portions of the circuit will flow
harmlessly to the low impedance analog ground rather than
into the analog input stage of the DDC112.

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

DDC112U ACTIVE SOIC DW 28 20 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

DDC112U/1K ACTIVE SOIC DW 28 1000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

DDC112U/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

DDC112UG4 ACTIVE SOIC DW 28 20 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

DDC112UK ACTIVE SOIC DW 28 20 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

DDC112UK/1K ACTIVE SOIC DW 28 1000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

DDC112UK/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

DDC112Y/250 ACTIVE TQFP PJT 32 250 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

DDC112Y/250G4 ACTIVE TQFP PJT 32 250 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

DDC112Y/2K ACTIVE TQFP PJT 32 2000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

DDC112Y/2KG4 ACTIVE TQFP PJT 32 2000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

DDC112YK/250 ACTIVE TQFP PJT 32 250 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

DDC112YK/250G4 ACTIVE TQFP PJT 32 250 Green(RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

DDC112YK/2K ACTIVE TQFP PJT 32 2000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

DDC112YK/2KG4 ACTIVE TQFP PJT 32 2000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

(1)

The marketing status values are defined asfollows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the devicewill be discontinued, and alifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but isnot in production. Samples mayor may not be available.
OBSOLETE: TI has discontinued the production ofthe device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information andadditional product content details.

TBD: The Pb-Free/Green conversion plan has notbeen defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products aresuitable for use in specifiedlead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed0.1% by weight in homogeneousmaterial)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

PACKAGE OPTION ADDENDUM

www.ti.com

26-Mar-2007

Addendum-Page 1

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

26-Mar-2007

Addendum-Page 2

MECHANICAL DATA

MPQF112 – NOVEMBER 2001

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PJT (S-PQFP–N32) PLASTIC QUAD FLA TPACK

4203540/A 11/01

1

0,45
0,30

32

7,00

SQ

0,95

1,05

Seating Plane

0,45

0,75

0,25

Gage Plane

0,80

0,20

SQ

9,00

1,00

1,20

0,10

0,05

0,15

0,20
0,09

M

0°– 7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to
discontinue any product or service without notice. Customers should obtain the latest relevant information
before placing orders and should verify that such information is current and complete. All products are sold
subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent
TI deems necessary to support this warranty. Except where mandated by government requirements, testing
of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible
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Products

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Amplifiers amplifier.ti.com Audio www.ti.com/audio

Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband

Interface interface.ti.com Digital Control www.ti.com/digitalcontrol

Logic logic.ti.com Military www.ti.com/military

Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork

Microcontrollers microcontroller.ti.com Security www.ti.com/security

Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony

Video & Imaging www.ti.com/video

Wireless www.ti.com/wireless

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