TEXAS INSTRUMENTS DAC8534 Technical data

DAC8534

D

®

A

C

8

5

3

4

SBAS254D – SEPTEMBER 2002 – REVISED MARCH 2004

Quad Channel, Low Power, 16-Bit, Serial Input

DIGITAL-TO-ANALOG CONVERTER

FEATURES

● POWER SUPPLY: +2.7V to +5.5V

●

micro

POWER OPERATION: 950µA at 5V

● 16-BIT MONOTONIC OVER TEMPERATURE

● SETTLING TIME: 10µs to ±0.003% FSR

● ULTRA-LOW AC CROSSTALK: –100dB typ

● POWER-ON RESET TO ZERO-SCALE

● ON-CHIP OUTPUT BUFFER AMPLIFIER WITH

RAIL-TO-RAIL OPERATION

● DOUBLE BUFFERED INPUT ARCHITECTURE

● SIMULTANEOUS OR SEQUENTIAL OUTPUT

UPDATE AND POWER-DOWN

● 16 CHANNEL BROADCAST CAPABILITY

● SCHMITT-TRIGGERED INPUTS

● TSSOP-16 PACKAGE

APPLICATIONS

● PORTABLE INSTRUMENTATION

● CLOSED-LOOP SERVO-CONTROL

● PROCESS CONTROL

● DATA ACQUISITION SYSTEMS

● PROGRAMMABLE ATTENUATION

● PC PERIPHERALS

DESCRIPTION

The DAC8534 is a quad channel, 16-bit Digital-to-Analog
Converter (DAC) offering low-power operation and a flexible
serial host interface. Each on-chip precision output amplifier
allows rail-to-rail output swing to be achieved over the supply
range of 2.7V to 5.5V. The device supports a standard 3-wire
serial interface capable of operating with input data clock
frequencies up to 30MHz for IOV

The DAC8534 requires an external reference voltage to set
the output range of each DAC channel. Also incorporated
into the device is a power-on reset circuit which ensures that
the DAC outputs power up at zero-scale and remain there
until a valid write takes place. The DAC8534 provides a per
channel power-down feature, accessed over the serial inter­face, that reduces the current consumption to 200nA per
channel at 5V.

The low-power consumption of this device in normal opera­tion makes it ideally suited to portable battery-operated
equipment and other low-power applications. The power
consumption is 5mW at 5V, reducing to 4µW in power-down
mode.

The DAC8534 is available in a TSSOP-16 package with a
specified operating temperature range of –40°C to +105°C.

AV

IOV

DD

DD

Data

Buffer A

Data

Buffer D

18

DAC

Register A

DAC

Register D

V

REF

DAC A

DAC D

H

DD

= 5V.

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

SYNC

SCLK

D

24-Bit

Serial-to-

Parallel

Shift

IN

Register

GND

Buffer

Control

8

A0 A1 LDAC

Register

Control

ENABLE

V

L

REF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright © 2002-2004, Texas Instruments Incorporated

www.ti.com

Power-Down
Control Logic

Resistor
Network

ABSOLUTE MAXIMUM RATINGS

AV

to GND ........................................................................ –0.3V to +6V

DD

Digital Input Voltage to GND ............................... –0.3V to +AV

V

A to V

OUT

Operating Temperature Range ......................................–40°C to +105°C

Storage Temperature Range ......................................... –65°C to +150°C

Junction Temperature Range (T

Power Dissipation ..........................................................(T

θ

JA

θ

JC

Lead Temperature, Soldering:

Vapor Phase (60s) ............................................................... +215°C

Infrared (15s)........................................................................ +220 °C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

to GND .................................... –0.3V to + AVDD + 0.3V

OUTD

max) ........................................ +150°C

J

Thermal Impedance.........................................................118°C/W

Thermal Impedance ........................................................... 29°C/W

(1)

+ 0.3V

DD

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru­ments recommends that all integrated circuits be handled with

max – TA)/

J

θ

JA

appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE/ORDERING INFORMATION

PRODUCT PACKAGE-LEAD DESIGNATOR

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

DAC8534 TSSOP-16 PW –40°C to +105°C D8534I DAC8534IPW Tube, 90

(1)

"" " ""DAC8534IPWR Tape and Reel, 2000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

SPECIFICATION

RANGE MARKING NUMBER MEDIA, QUANTITY

ELECTRICAL CHARACTERISTICS

AVDD = +2.7V to +5.5V, –40°C to +105°C, unless otherwise specified.

DAC8534
PARAMETER CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE

Resolution 16 Bits
Relative Accuracy ±0.0987 % of FSR
Differential Nonlinearity 16-Bit Monotonic 0.25 ±1LSB
Zero-Scale Error +5 +20 mV
Zero-Scale Error Drift ±7 µV/°C
Full-Scale Error –0.15 –1.0 % of FSR
Gain Error ±1.0 % of FSR
Gain Temperature Coefficient ±3 ppm of FSR/°C
Channel-to-Channel Matching R
PSRR 0.75 mV/V

OUTPUT CHARACTERISTICS

Output Voltage Range 0V
Output Voltage Settling Time To ±0.003% FSR 8 10 µs

Slew Rate 1V/µs
Capacitive Load Stability R

Code Change Glitch Impulse 1LSB Change Around Major Carry 20 nV-s
Digital Feedthrough 0.5 nV-s
DC Crosstalk 0.25 LSB
AC Crosstalk 1kHz sine Wave –100 –96 dB
DC Output Impedance 1 Ω
Short-Circuit Current AV

Power-Up Time Coming Out of Power-Down Mode

AC PERFORMANCE BW = 20kHz, AV
SNR (

1st 19 Harmonics Removed) F
THD 67 dB
SFDR 69 dB
SINAD 65 dB

NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested.

(1)

= 2kΩ, CL = 200pF 8 mV

L

(2)

HV

REF

0200

to FD00

RL = 2kΩ; 0pF < CL < 200pF

Coming Out of Power-Down Mode

H

R

= 2kΩ; CL = 500pF 12 µs

L

R

L

DD

AV

DD

AV

DD

AV

DD

OUT

H

= ∞ 470 pF

L

= 2kΩ 1000 pF

= +5V 50 mA
= +3V 20 mA

= +5V 2.5 µs

= +3V 5 µs

= 5V

DD

= 1kHz

94 dB

2

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DAC8534

SBAS254D

ELECTRICAL CHARACTERISTICS (Cont.)

AVDD = +2.7V to +5.5V, –40°C to +105°C, unless otherwise specified.

DAC8534
PARAMETER CONDITIONS MIN TYP MAX UNITS
REFERENCE INPUT

Reference Current V

Reference Input Range 0 AV
Reference Input Impedance 37 kΩ

LOGIC INPUTS

(2)

Input Current ±1 µA
V

L, Input LOW Voltage IOVDD = +5V 0.8 V

IN

V

L, Input LOW Voltage IOVDD = +3V 0.6 V

IN

V

H, Input HIGH Voltage IOVDD = +5V 2.4 V

IN

V

H, Input HIGH Voltage IOVDD = +3V 2.1 V

IN

Pin Capacitance 3pF

POWER REQUIREMENTS

AV

DD

IOV

DD

AIDD (normal mode)

IOI

DD

AI

= +3.6V to +5.5V VIH = IOVDD and VIL = GND 0.95 1.6 mA

DD

AI

= +2.7V to +3.6V VIH = IOVDD and VIL = GND 0.9 1.5 mA

DD

AI

(all power-down modes)

DD

AI

= +3.6V to +5.5V VIH = IOVDD and VIL = GND 0.8 1 µA

DD

AI

= +2.7V to +3.6V VIH = IOVDD and VIL = GND 0.05 1 µA

DD

DAC Active and Excluding Load Current

POWER EFFICIENCY

I

OUT/IDD

TEMPERATURE RANGE

Specified Performance –40 +105 °C

NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested.

= AVDD = +5V 135 180 µA

REF

V

= AVDD = +3V 80 120 µA

REF

DD

2.7 5.5 V

2.7 5.5 V

10 20 µA

I

= 2mA, AVDD = +5V 89 %

LOAD

V

PIN CONFIGURATION

Top View TSSOP

V
V
V

V

V
V

OUT

OUT

REF

AV

REF

GND

OUT

OUT

1

A

2

B

3

H

4

DD

L

DAC8534

5
6
7

C

8

D

16
15
14
13
12
11
10

9

LDAC
ENABLE
A1
A0
IOV

DD

D

IN

SCLK
SYNC

PIN DESCRIPTIONS

PIN NAME DESCRIPTION

1V
2V
2V
4AV
5V
6 GND Ground reference point for all circuitry on the part.
7V
8V
9 SYNC Level-triggered control input (active LOW). This is

10 SCLK Serial Clock Input. Data can be transferred at rates

11 D

12 IOV
13 A0 Address 0 — sets device address, see Table II.
14 A1 Address 1 — sets device address, see Table II.
15 ENABLE Active LOW, ENABLE LOW connects the SPI inter-

16 LDAC Load DACs, rising edge triggered loads all DAC

A Analog output voltage from DAC A.

OUT

B Analog output voltage from DAC B.

OUT

H Positive reference voltage input.

REF

REF

OUT
OUT

Power supply input, +2.7V to +5.5V.

DD

L Negative reference voltage input.

C Analog output voltage from DAC C.
D Analog output voltage from DAC D.

the frame synchronization signal for the input data.
When SYNC goes LOW, it enables the input shift
register and data is transferred in on the falling
edges of the following clocks. The DAC is updated
following the 24th clock (unless SYNC is taken
HIGH before this edge in which case the rising edge
of SYNC acts as an interrupt and the write sequence
is ignored by the DAC8534).

up to 30MHz.
Serial Data Input. Data is clocked into the 24-bit

IN

input shift register on each falling edge of the serial
clock input.

Digital Input-Output Power Supply

DD

face to the serial port.

registers.

DAC8534

SBAS254D

3

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TIMING CHARACTERISTICS

(1, 2)

AVDD = +2.7V to +5.5V; all specifications –40°C to +105°C unless otherwise noted.

DAC8534

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNITS

(3)

t

1

t

2

t

3

t

4

SCLK Cycle Time IOVDD = AVDD = 2.7V to 3.6V 50 ns

IOV

= AVDD = 3.6V to 5.5V 33 ns

DD

SCLK HIGH Time IOVDD = AVDD = 2.7V to 3.6V 26 ns

IOV

= AVDD = 3.6V to 5.5V 15 ns

DD

SCLK LOW Time IOVDD = AVDD = 2.7V to 3.6V 22.5 ns

IOV

= AVDD = 3.6V to 5.5V 13 ns

DD

SYNC Falling Edge to SCLK IOVDD = AVDD = 2.7V to 3.6V 0 ns

Rising Edge Setup Time IOV

= AVDD = 3.6V to 5.5V 0 ns

DD

t

5

t

6

t

7

t

8

t

9

NOTES: (1) All input signals are specified with t
timing diagram, below. (3) Maximum SCLK frequency is 30MHz at IOV

Data Setup Time IOVDD = AVDD = 2.7V to 3.6V 5 ns

IOV

= AVDD = 3.6V to 5.5V 5 ns

DD

Data Hold Time IOVDD = AVDD = 2.7V to 3.6V 4.5 ns

IOV

= AVDD = 3.6V to 5.5V 4.5 ns

DD

24th SCLK Falling Edge to IOVDD = AVDD = 2.7V to 3.6V 0 ns

SYNC Rising Edge IOV

= AVDD = 3.6V to 5.5V 0 ns

DD

Minimum SYNC HIGH Time IOVDD = AVDD = 2.7V to 3.6V 50 ns

IOV

= AVDD = 3.6V to 5.5V 33 ns

DD

24th SCLK Falling Edge to IOVDD = AVDD = 2.7V to 5.5V 130 ns

SYNC Falling Edge

= tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation

R

SERIAL WRITE OPERATION

t

SCLK 1 24

t

SYNC

D

8

IN

t

4

t

5

DB23 DB0 DB23

t

3

t

6

= AV

DD

1

t

2

= +3.6V to +5.5V and 20MHz at IOVDD = AV

DD

t

9

t

7

= +2.7V to +3.6V.

DD

4

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DAC8534

SBAS254D

TYPICAL CHARACTERISTICS

64
48
32
16

0

–16
–32
–48
–64

LE (LSB)

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

0000

H

2000H4000H6000H8000

H

Digital Input Code

A000

H

C000HE000HFFFF

H

1.0

0.5

0.0

–0.5
–1.0

DLE (LSB)

CHANNEL B AVDD = 2.7V

At TA = +25°C, unless otherwise noted.

LINEARITY ERROR AND DIFFERENTIAL

64
48
32
16

0

–16

LE (LSB)

–32
–48
–64

LINEARITY ERROR vs DIGITAL INPUT CODE

CHANNEL A AVDD = 5V

1.0

0.5

0.0

–0.5

DLE (LSB)

–1.0

2000H4000H6000H8000

0000

H

H

A000

Digital Input Code

LINEARITY ERROR AND DIFFERENTIAL

64
48
32
16

0

–16

LE (LSB)

–32
–48
–64

LINEARITY ERROR vs DIGITAL INPUT CODE

CHANNEL C AVDD = 5V

1.0

0.5

0.0

–0.5

DLE (LSB)

–1.0

0000

2000H4000H6000H8000

H

H

A000

Digital Input Code

C000HE000HFFFF

H

C000HE000HFFFF

H

LINEARITY ERROR AND DIFFERENTIAL

64
48
32
16

0

–16

LE (LSB)

–32
–48
–64

LINEARITY ERROR vs DIGITAL INPUT CODE

CHANNEL B AVDD = 5V

1.0

0.5

0.0

–0.5

DLE (LSB)

–1.0

2000H4000H6000H8000

H

0000

H

A000

H

C000HE000HFFFF

H

H

Digital Input Code

LINEARITY ERROR AND DIFFERENTIAL

64
48
32
16

0

–16

LE (LSB)

–32
–48
–64

LINEARITY ERROR vs DIGITAL INPUT CODE

CHANNEL D AVDD = 5V

1.0

0.5

0.0

–0.5

DLE (LSB)

–1.0

0000

H

2000H4000H6000H8000

H

A000

H

C000HE000HFFFF

H

H

Digital Input Code

LINEARITY ERROR AND DIFFERENTIAL

64
48
32
16

0

–16

LE (LSB)

–32
–48
–64

LINEARITY ERROR vs DIGITAL INPUT CODE

CHANNEL A AVDD = 2.7V

1.0

0.5

0.0

–0.5

DLE (LSB)

–1.0

0000

2000H4000H6000H8000

H

DAC8534

SBAS254D

Digital Input Code

H

A000

C000HE000HFFFF

H

H

5

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TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, unless otherwise noted.

LINEARITY ERROR AND DIFFERENTIAL

64
48
32
16

–16

LE (LSB)

–32
–48
–64

LINEARITY ERROR vs DIGITAL INPUT CODE

CHANNEL C AVDD = 2.7V

0

1.0

0.5

0.0

–0.5

DLE (LSB)

–1.0

0000

2000H4000H6000H8000

H

H

A000

Digital Input Code

ZERO-SCALE ERROR vs TEMPERATURE

10

CH D CH C

8

6

4

Error (mV)

C000HE000HFFFF

H

AVDD = V

REF

= 5V

LINEARITY ERROR AND DIFFERENTIAL

64
48
32
16

0

–16

LE (LSB)

–32
–48
–64

LINEARITY ERROR vs DIGITAL INPUT CODE

CHANNEL D AVDD = 2.7V

1.0

0.5

0.0

–0.5

DLE (LSB)

–1.0

2000H4000H6000H8000

H

0000

H

H

A000

C000HE000HFFFF

H

H

Digital Input Code

ZERO-SCALE ERROR vs TEMPERATURE

10

8

AVDD = V

REF

= 2.7V

6

CH A CH C CH B CH D

4

Error (mV)

2

2

CH B CH A

0

–40 –10 20 50 80 110

Temperature (°C)

FULL-SCALE ERROR vs TEMPERATURE

20

15

10

5

Error (mV)

0

To avoid clipping of the output signal
during the test, V

AV

DD

= 5V, V

REF

= AV

REF

– 10mV,

DD

= 4.99V

–5

–10

–40 –10 20 50 80 110

Temperature (°C)

CH C

CH D

CH B

CH A

0

–2

–40 –10 20 50 80 110

Temperature (°C)

FULL-SCALE ERROR vs TEMPERATURE

20

To avoid clipping of the output signal

15

10

CH C CH D

during the test, V

AV

= 2.7V, V

DD

REF

= AV

REF

– 10mV,

DD

= 2.69V

5

Error (mV)

0

CH A

–5

CH B

–10

–40 –10 20 50 80 110

Temperature (°C)

6

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DAC8534

SBAS254D

TYPICAL CHARACTERISTICS (Cont.)

AVDD = V

REF

= 5V

SUPPLY CURRENT vs DIGITAL INPUT CODE

1200

1000

800

600

400

200

0

AI

DD

(µA)

0000H2000H4000H6000H8000

H

Digital Input Code

A000

H

C000HE000HFFFF

H

AVDD = V

REF

= 2.7V

1000

950
900
850
800
750
700
650
600

AI

DD

(µA)

2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
AV

DD

(V)

SUPPLY CURRENT vs SUPPLY VOLTAGE

At TA = +25°C, unless otherwise noted.

0.150
V

= AVDD – 10mV

REF

DAC loaded with 0000

0.125

H

0.100

SINK CURRENT CAPABILITY (ALL CHANNELS)

(V)

0.075

OUT

V

AVDD = 5V

0.050

0.025

AVDD = 2.7V

0.000

012345

I

(mA)

SINK

SOURCE CURRENT CAPABILITY (ALL CHANNELS)

(V)

OUT

V

2.70

2.65

2.60

V

= AV

REF

DAC Loaded with FFFF

AV

DD

DD

– 10mV

= 2.7V

SOURCE CURRENT CAPABILITY (ALL CHANNELS)

(V)

OUT

V

5.00

4.95

4.90

V

= AV

DD

AV

– 10mV

= 5V

DD

REF

DAC Loaded with FFFF

H

4.85

4.80
012345

I

(mA)

SOURCE

H

2.55

2.50
012345

SUPPLY CURRENT vs TEMPERATURE

1200

AVDD = V

REF

= 5V

1000

800

(µA)

600

DD

Reference Current Included
All Channels Powered, No Load.

400

200

0

–40 –10 20 50 80 110

AI

DAC8534

SBAS254D

I

(mA)

SOURCE

AVDD = V

REF

Temperature (°C)

= 2.7V

7

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TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, unless otherwise noted.

1750

TA = 25°C, SYNC Input (All others inputs = GND)

1650

Reference Current Included

1550

SUPPLY CURRENT vs LOGIC INPUT VOLTAGE

1450

(µA)

DD

1350
1250

+ IOI

DD

1150

AI

1050

950

AVDD = V

REF

AVDD = V

= 2.7V

850
750

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

(V)

V

LOGIC

HISTOGRAM OF CURRENT CONSUMPTION

1500

AVDD = V
Reference Current Included

REF

= 2.7V

1000

Frequency

500

0

730

850

880

910

940

820

790

760

AIDD (µA)

REF

970

= 5V

1000

1030

1060

1500

1000

Frequency

500

0

5.5

5.0

4.5

4.0

3.5

(V)

3.0

OUT

2.5

V

2.0

1.5

1.0

0.5

0.0

–0.5

HISTOGRAM OF CURRENT CONSUMPTION

AVDD = V
Reference Current Included

790

820

REF

850

= 5V

880

910

940

970

1000

AIDD (µA)

EXITING POWER-DOWN MODE

AVDD = V
Power-Up Code = FFFF

REF

= 5V

H

Time (3µs/div)

1030

1060

1090

1120

1150

2.53

2.52

2.51

2.50

2.49

2.48

(V, 10mV/div)

2.47

OUT

V

2.46

2.45

2.44

2.43

8

OUTPUT GLITCH

(Mid-Scale)

AVDD = V
Code 7FFF
(Glitch Occurs Every N • 4096

= 5V

REF

to 8000H to 7FFF

H

Code Boundary)

Time (1µs/div)

OUTPUT GLITCH

4.72
AVDD = V

H

4.70

4.68

REF

Code EFFF
(Glitch Occurs Every N • 4096

H

Code Boundary)

(Worst Case)

= 5V

to F000H to EFFF

H

4.66

4.64

4.62

(V, 20mV/div)

OUT

4.60

V

4.58

4.56

4.54

Time (1µs/div)

DAC8534

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SBAS254D

TYPICAL CHARACTERISTICS (Cont.)

Channel B Output

Channel A Output

Channel C Output

Channel D Output

ABSOLUTE ERROR

10

8
6
4
2
0

–2
–4
–6
–8

–10

Output Error (mV)

0000H2000H4000H6000H8000

H

Digital Input Code

A000

H

C000HE000HFFFF

H

AVDD = V

REF

= 2.7V

T

A

= 25°C

HALF-SCALE SETTLING TIME

(Large Signal)

3.0

2.5

2.0

1.5

1.0

0.5

0

V

OUT

(V)

Time (12µs/div)

AVDD = V

REF

= 5V
Output Loaded with
2kΩ and 200pF
to GND

HALF-SCALE SETTLING TIME

1.5

1.0

0.5

0

V

OUT

(V)

Time (12µs/div)

AVDD = V

REF

= 2.7V

Output Loaded with

2kΩ and 200pF

to GND

At TA = +25°C, unless otherwise noted.

20
18
16
14
12

AVDD = V
T

= 25°C

A

ABSOLUTE ERROR

= 5V

REF

Channel B Output

10

8
6

Output Error (mV)

4

Channel A Output

2
0

0000H2000H4000H6000H8000

Digital Input Code

FULL-SCALE SETTLING TIME

6

(Large Signal)

5

4

(V)

3

OUT

V

2

Channel D Output

Channel C Output

A000

H

C000HE000HFFFF

H

AVDD = V
Output Loaded with
2kΩ and 200pF
to GND

REF

H

= 5.5V

3.5

3.0

2.5

2.0

(V)

OUT

1.5

V

1.0

0.5

DAC8534

SBAS254D

1

0

0

Time (12µs/div)

FULL-SCALE SETTLING TIME

(Large Signal)

Time (12µs/div)

AVDD = V
Output Loaded with

REF

= 2.7V

2kΩ and 200pF
to GND

9

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TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, unless otherwise noted.

SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY

98

96

94

92

90

SNR (dB)

88

AVDD = V
–1dB FSR Digital Input, FS = 52ksps

86

Measurement Bandwidth = 20kHz

84

0 500 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k 4.5k

AVDD = 5V

AVDD = 2.7V

REF

Output Frequency (Hz)

TOTAL HARMONIC DISTORTION vs

0

AVDD = V

–10

F

= 52ksps, –1dB FSR Digital Input

S

–20

Measurement Bandwidth = 20kHz

–30
–40
–50

THD (dB)

–60
–70
–80
–90

–100

0 500 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k

OUTPUT FREQUENCY

= 5V

REF

THD

2nd-Harmonic

Output Frequency (Hz)

3rd-Harmonic

TOTAL HARMONIC DISTORTION vs

0

AVDD = V

–10

F

= 52ksps, –1dB FSR Digital Input

S

–20

Measurement Bandwidth = 20kHz

–30
–40
–50

THD (dB)

–60
–70
–80
–90

–100

0 500 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k

OUTPUT FREQUENCY

= 2.7V

REF

THD

2nd-Harmonic

Output Frequency (Hz)

3rd-Harmonic

FULL-SCALE SETTLING TIME

(Small-Signal-Positive Going Step)

Small-Signal Settling Time
5mV/div

Output Voltage

Trigger Pulse

Time (2µs/div)

FULL-SCALE SETTLING TIME

(Small-Signal-Negative Going Step)

Small-Signal Settling Time
5mV/div

10

Output Voltage

Trigger Pulse

Time (2µs/div)

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DAC8534

SBAS254D

THEORY OF OPERATION

To Output

Amplifier
(2x Gain)

R

R

R

R

V

REF

2

V

REF

H

R

DIVIDER

V

REF

L

DAC SECTION

The architecture of each channel of the DAC8534 consists of
a resistor-string DAC followed by an output buffer amplifier.
Figure 1 shows a simplified block diagram of the DAC
architecture.

H

V

REF

70kΩ

DAC Register

REF (+)

Resistor String

REF(–)

V

REF

FIGURE 1. DAC8534 Architecture.

The input coding for each device is unipolar straight binary,
so the ideal output voltage is given by:

VX VLVHVL

=+−

••

2

OUT

REF REF REF

where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 65535.
V

X refers to channel A or through D.

OUT

RESISTOR STRING

The resistor string section is shown in Figure 2. It is simply
a divide-by-2 resistor followed by a string of resistors. The
code loaded into the DAC register determines at which node
on the string the voltage is tapped off. This voltage is then
applied to the output amplifier by closing one of the switches
connecting the string to the amplifier.

OUTPUT AMPLIFIER

Each output buffer amplifier is capable of generating rail-to­rail voltages on its output which approaches an output range
of 0V to AV
account). Each buffer is capable of driving a load of 2kΩ in
parallel with 1000pF to GND. The source and sink capabili­ties of the output amplifier can be seen in the typical charac­teristics.

(gain and offset errors must be taken into

DD

SERIAL INTERFACE

The DAC8534 uses a 3-wire serial interface (
and D
Microwire™ interface standards, as well as most DSPs. See

), which is compatible with SPI™, QSPI™, and

IN

the Serial Write Operation timing diagram for an example of
a typical write sequence.

50kΩ 50kΩ

V

OUT

L

D

()

IN

65536

SYNC

, SCLK,

FIGURE 2. Resistor String.

The write sequence begins by bringing the
Data from the D

line is clocked into the 24-bit shift register on

IN

SYNC

line LOW.

each falling edge of SCLK. The serial clock frequency can be
as high as 30MHz, making the DAC8534 compatible with high­speed DSPs. On the 24th falling edge of the serial clock, the
last data bit is clocked into the shift register and the shift
register gets locked. Further clocking does not change the shift
register data. Once 24 bits are locked into the shift register, the
8MSBs are used as control bits and the 16LSBs are used as
data. After receiving the 24th falling clock edge, DAC8534
decodes the 8 control bits and 16 data bits to perform the
required function, without waiting for a
new SPI sequence starts at the next falling edge of
rising edge of

SYNC

before the 24-bit sequence is complete

SYNC

rising edge. A

SYNC

. A

resets the SPI interface; no data transfer occurs.
At this point, the

SYNC

line may be kept LOW or brought HIGH.
In either case, the minimum delay time from the 24th falling
SCLK edge to the next falling

SYNC

edge must be met in order
to properly begin the next cycle. To assure the lowest power
consumption of the device, care should be taken that the digital
input levels are as close to each rail as possible. (Please refer
to the “Typical Characteristics” section for the “Supply Current
vs Logic Input Voltage” transfer characteristic curve.)

IOVDD AND VOLTAGE TRANSLATORS

The IOVDD pin powers the digital input structures of the
DAC8534. For single-supply operation, it could be tied to AV
For dual-supply operation, the IOV

pin provides interface

DD

flexibility with various CMOS logic families and it should be
connected to the logic supply of the system. Analog circuits and
internal logic of the DAC8534 use AV
The external logic high inputs get translated to AV
shifters. These level shifters use the IOV

as the supply voltage.

DD

DD

voltage as a

DD

DD

by level

.

DAC8534

SBAS254D

11

www.ti.com

reference to shift the incoming logic HIGH levels to AVDD.
IOV

is ensured to operate from 2.7V to 5.5V regardless of

DD

the AV
logic families. Although specified down to 2.7V, IOV

voltage, which ensures compatibility with various

DD

DD

will
operate at as low as 1.8V with degraded timing and tempera­ture performance. For lowest power consumption, logic V

IH

levels should be as close as possible to IOVDD, and logic V
levels should be as close as possible to GND voltages.

INPUT SHIFT REGISTER

The input shift register (SR) of the DAC8534 is 24 bits wide, as
shown in Figure 3, and is made up of 8 control bits (DB16-DB23)
and 16 data bits (DB0-DB15). The first two control bits (DB22
and DB23) are the address match bits. The DAC8534 offers
additional hardware-enabled addressing capability allowing a
single host to talk to up to four DAC8534s through a single SPI
bus without any glue logic, enabling up to 16-channel operation.
The state of DB23 should match the state of pin A1; similarly, the
state of DB22 should match the state of pin A0. If there is no
match, the control command and the data (DB21...DB0) are
ignored by the DAC8534. That is, if there is no match, the
DAC8534 is not addressed. Address matching can be overrid­den by the broadcast update, as will be explained.

LD 1 (DB20) and LD 0 (DB21) control the updating of each
analog output with the specified 16-bit data value or power­down command. Bit DB19 is a “Don’t Care” bit which does not
affect the operation of the DAC8534 and can be 1 or 0. The
DAC Channel Select Bits (DB17, DB18) control the destination
of the data (or power-down command) from DAC A through
DAC D. The final control bit, PD0 (DB16), selects the power­down mode of the DAC8534 channels.

The DAC8534 also supports a number of different load com­mands. The load commands include broadcast commands to
address all the DAC8534s on an SPI bus. The load commands
can be summarized as follows:

DB21 = 0 and DB20 = 0: Single-channel store. The temporary
register (data buffer) corresponding to a DAC selected by
DB18 and DB17 is updated with the contents of SR data (or
power-down).

DB21 = 0 and DB20 = 1: Single-channel update. The tempo­rary register and DAC register corresponding to a DAC se­lected by DB18 and DB17 are updated with the contents of SR
data (or power-down).

DB21 = 1 and DB20 = 0: Simultaneous update. A channel
selected by DB18 and DB17 gets updated with the SR data,
and simultaneously, all the other channels get updated with
previous stored data (or power-down).

DB21 = 1 and DB20 = 1: Broadcast update. All the DAC8534s
on the SPI bus respond, regardless of address matching. If
DB18 = 0, then SR data gets ignored, all channels from all

DAC8534s get updated with previously stored data (or power­down). If DB18 = 1, then SR data (or power-down) updates all
channels of all DAC8534s in the system. This broadcast update
feature allows the simultaneous update of up to 16 channels.

Power-down/data selection is as follows:
DB16 is a power-down flag. If this flag is set, then DB15 and

IL

DB14 select one of the four power-down modes of the device
as described in Table I. If DB16 = 1, DB15 and DB14 no longer
represent the two MSBs of data, they represent a power-down
condition described in Table I. Similar to data, power-down
conditions can be stored at the temporary registers of each
DAC. It is possible to update DACs simultaneously either with
data, power-down, or a combination of both.

Please refer to Table II for more information.

PD0 (DB16) PD1 (DB15) PD2 (DB14) OPERATING MODE

1 0 0 Output High Impedance
1 0 1 Output Typically 1kΩ to GND
1 1 0 Output Typically 100kΩ to GND
1 1 1 Output High Impedance

TABLE I. DAC8534 Power-Down Modes.

SYNC

INTERRUPT

In a normal write sequence, the

SYNC

line is kept LOW for
at least 24 falling edges of SCLK and the addressed DAC
register is updated on the 24th falling edge. However, if

SYNC

is brought HIGH before the 24th falling edge, it acts
as an interrupt to the write sequence; the shift register is
reset and the write sequence is discarded. Neither an update
of the data buffer contents, DAC register contents, nor a
change in the operating mode occurs (see Figure 4).

POWER-ON RESET

The DAC8534 contains a power-on reset circuit that con­trols the output voltage during power-up. On power-up, the
DAC registers are filled with zeros and the output voltages
are set to zero-scale; they remain there until a valid write
sequence and load command is made to the respective
DAC channel. This is useful in applications where it is
important to know the state of the output of each DAC
output while the device is in the process of powering up. No
device pin should be brought high before power is applied
to the device.

POWER-DOWN MODES

The DAC8534 utilizes four modes of operation. These modes
are accessed by setting three bits (PD2, PD1, and PD0) in
the shift register and performing a “Load” action to the DACs.
The DAC8534 offers a very flexible power-down interface
based on channel register operation. A channel consists of a

DB23 DB12

A1 A0 LD1 LD0 X

DB11 DB0

D11D10D9D8D7D6D5D4D3D2D1D0

DAC Select 1 DAC Select 0

PD0 D15 D14 D13 D12

FIGURE 3. DAC8534 Data Input Register Format.

12

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DAC8534

SBAS254D

D23 D22 D21 D20 D19 D18 D17 D16

A1 A0 Load 1 Load 0 Don’t Care DAC Sel 1 DAC Sel 0 PD0

(Address Select)

0/1 0/1

0 0 X 0 0 0 Write To Buffer A w/Data
0 0 X 0 1 0 Write To Buffer B w/Data
0 0 X 1 0 0 Write To Buffer C w/Data
0 0 X 1 1 0 Write To Buffer D w/Data

00 X

(A0 and A1 should

correspond to the

package address set

via pins 13 and 14.)

X X 1 1 X 0 X X Load All DACs, All Device, and All Buffers with Stored Data
X X 1 1 X 1 X 0 Write To All Devices and Load All Dacs, with SR Data

XX11X1X1

01 X 0

01 X

10 X Write To Buffer w / D a t a ( s e l e c t e d by DB17 and D B18) and Load All

10 X

Broadcast Modes

See Below

(00, 01, 10, or 11)

(00, 01, 10, or 11)

(00, 01, 10, or 11)

(00, 01, 10, or 11)

(00, 01, 10, or 11)

D15 D14 D13-D0

MSB MSB-1 MSB-2...LSB

Data
Data
Data
Data

1

(see Table I)

Data

1

(see Table I)

0

1

(see Table I)

(see Table I)

Data

X

Data

DESCRIPTION

This address selects 1 of 4 possible devices on a single SPI
data bus based on each device’s address pin(s) state.

Write To Buffer (sel e c t e d b y D B 1 7 and DB18) w/Power-Down

0

Command
Write To Buffer w/Data and Load DAC (selected by DB17 and

DB18)
Write To Buffer w/Power-Down Command and Load DAC

0

(selected by DB17 and DB18)

DACs
Write To Buffer w/Power-Down Command (selected by DB17 and

0

DB18) and Load All DACs

0

Write To All Devices w/Power-Down Command in SR

TABLE II. Control Matrix.

SCLK

SYNC

D

IN

FIGURE 4. Interrupt and Valid

SYNC HIGH Before 24th Falling Edge

SYNC

12 12

Invalid Write-Sync Interrupt:

DB23 DB22

DB0 DB23 DB22 DB1 DB0

Timing.

single 16-bit DAC with power-down circuitry, a temporary
storage register (TR), and a DAC register (DR). TR and DR
are both 18-bit wide. Two MSBs represent power-down
condition and 16LSBs represent data for TR and DR. By
adding bits 17 and 18 to TR and DR, a power-down condition
can be temporarily stored and used just like data. Internal
circuits ensure that DB15 and DB14 get transfered to TR17
and TR16 (DR17 and DR16), when DB16 = 1.

The DAC8534 treats the power-down condition like data and
all the operational modes are still valid for power-down. It is
possible to broadcast a power-down condition to all the
DAC8534s in a system, or it is possible to simultaneously
power-down a channel while updating data on other channels.

DB16, DB15, and DB14 = 100 represent a power-down
condition with Hi-Z output impedance for a selected channel.
Same is true for 111. 101 represents a power-down condition
with 1k output impedance and 110 represents a power-down
condition with 100k output impedance.

24th Falling

Edge

Valid Write-Buffer/DAC Update:

SYNC HIGH After 24th Falling Edge

24th Falling

Edge

When both bits are set to 0 or 1, the device enters a high­impedance state with a typical power consumption of 3pA at
5V. For the two low impedance output modes, however, the
supply current falls to 100nA at 5V (50nA at 3V). Not only does
the supply current fall, but the output stage is also internally
switched from the output of the amplifier to a resistor network
of known values. This has the advantage that the output
impedance of the device is known while it is in power-down
mode. There are three different options for power-down: the
output is connected internally to GND through a 1kΩ resistor,
a 100kΩ resistor, or it is left open-circuited (High-Impedance).
The output stage is illustrated in Figure 5.

All analog circuitry is shut down when the power-down mode
is activated. Each DAC will exit power-down when PD0 is set
to 0, new data is written to the Data Buffer, and the DAC
channel receives a “Load” command. The time to exit power­down is typically 2.5µs for AV

= 5V and 5µs for AVDD = 3V

DD

(see the Typical Characteristics).

DAC8534

SBAS254D

13

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Resistor

String DAC

Amplifier

X

V

OUT

Power-down

Circuitry

Resistor
Network

FIGURE 5. Output Stage During Power-Down (High-Impedance).

OPERATION EXAMPLES

Example 1: Write to Data Buffer A; Through Buffer D; Load DAC A Through DAC D Simultaneously

• 1st—Write to Data Buffer A:

A1 A0 LD1 LD0 DC

0000X000D15..... D1 D0

• 2nd—Write to Data Buffer B:

A1 A0 LD1 LD0 DC

0000X010D15..... D1 D0

• 3rd—Write to Data Buffer C:

A1 A0 LD1 LD0 DC

0000X100D15..... D1 D0

• 4th—Write to Data Buffer D and simultaneously update all DACs:

A1 A0 LD1 LD0 DC

0010X110D15..... D1 D0

DAC Sel 1 DAC Sel

DAC Sel 1 DAC Sel

DAC Sel 1 DAC Sel

DAC Sel 1 DAC Sel

0 PD0 DB15 ...... DB1 DB0

0 PD0 DB15 ...... DB1 DB0

0 PD0 DB15 ...... DB1 DB0

0 PD0 DB15 ...... DB1 DB0

The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon completion of the
4th write sequence. (The “Load” command moves the digital data from the data buffer to the DAC register at which time the
conversion takes place and the analog output is updated. “Completion” occurs on the 24th falling SCLK edge after

SYNC

LOW.)

Example 2: Load New Data to DAC A Through DAC D Sequentially

• 1st—Write to Data Buffer A and Load DAC A: DAC A output settles to specified value upon completion:

A1 A0 LD1 LD0 DC

0001X000D15..... D1 D0

DAC Sel 1 DAC Sel

0 PD0 DB15 ...... DB1 DB0

• 2nd—Write to Data Buffer B and Load DAC B: DAC B output settles to specified value upon completion:

A1 A0 LD1 LD0 DC

0001X010D15..... D1 D0

DAC Sel 1 DAC Sel

0 PD0 DB15 ...... DB1 DB0

• 3rd—Write to Data Buffer C and Load DAC C: DAC C output settles to specified value upon completion:

A1 A0 LD1 LD0 DC

0001X100D15..... D1 D0

DAC Sel 1 DAC Sel

0 PD0 DB15 ...... DB1 DB0

• 4th—Write to Data Buffer D and Load DAC D: DAC D output settles to specified value upon completion:

A1 A0 LD1 LD0 DC

0001X110D15..... D1 D0

DAC Sel 1 DAC Sel

0 PD0 DB15 ...... DB1 DB0

After completion of each write cycle, DAC analog output settles to the voltage specified .

Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ Simultaneously

• Write power-down command to Data Buffer A: DAC A to 1kΩ.

A1 A0 LD1 LD0 DC

0000X00101X........

DAC Sel 1 DAC Sel

0 PD0 DB15 DB14 DB13 ........

14

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DAC8534

SBAS254D

• Write power-down command to Data Buffer B: DAC B to 1kΩ.

A1 A0 LD1 LD0 DC

0000X01101X........

DAC Sel 1 DAC Sel

0 PD0 DB15 DB14 DB13 ........

• Write power-down command to Data Buffer C: DAC C to 100kΩ.

A1 A0 LD1 LD0 DC

0000X10110X........

DAC Sel 1 DAC Sel

0 PD0 DB15 DB14 DB13 ........

• Write power-down command to Data Buffer D: DAC D to 100kΩ and Simultaneously Update all DACs.

A1 A0 LD1 LD0 DC

0010X11110X........

DAC Sel 1 DAC Sel

0 PD0 DB15 DB14 DB13 ........

The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified mode upon
completion of the 4th write sequence.

Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially:

• Write power-down command to Data Buffer A and Load DAC A: DAC A output = High-Z:

A1 A0 LD1 LD0 DC

0001X00111X........

DAC Sel 1 DAC Sel

0 PD0 DB15 DB14 DB13 ........

• Write power-down command to Data Buffer B and Load DAC B: DAC B output = High-Z:

A1 A0 LD1 LD0 DC

0001X01111X........

DAC Sel 1 DAC Sel

0 PD0 DB15 DB14 DB13 ........

• Write power-down command to Data Buffer C and Load DAC C: DAC C output = High-Z:

A1 A0 LD1 LD0 DC

0001X10111X........

DAC Sel 1 DAC Sel

0 PD0 DB15 DB14 DB13 ........

• Write power-down command to Data Buffer D and Load DAC D: DAC D output = High-Z:

A1 A0 LD1 LD0 DC

0001X11111X........

DAC Sel 1 DAC Sel

0 PD0 DB15 DB14 DB13 ........

The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon completion of the
1st, 2nd, 3rd, and 4th write sequences, respectively.

LDAC FUNCTIONALITY

The DAC8534 offers both a software and hardware simulta­neous update function. The DAC8534 double-buffered architec­ture has been designed so that new data can be entered for
each DAC without disturbing the analog outputs. The software
simultaneous update capability is controlled by the Load 1 (LD1)
and Load 0 (LD0) control bits. By setting Load 1 equal to “1” all
of the DAC registers will be updated on the falling edge of the
24th clock signal. When the new data has been entered into the
device, all of the DAC outputs can be updated simultaneously
and synchronously with the clock.

The internal DAC register is edge triggered and not level
triggered, therefore, when the LDAC pin signal is transitioned
from LOW to HIGH, the digital word currently in the DAC input
register is latched. Additionally, it allows the DAC input registers
to be written to at any point; then, the DAC output voltages can
be asynchronously changed via the LDAC pin. The LDAC trigger
should only be used after the buffers are properly updated
through software. If DAC outputs are desired to be updated
through software only, the LDAC pin must be tied low perma­nently.

MICROPROCESSOR
INTERFACING

DAC8534 to 8051 INTERFACE

See Figure 6 for a serial interface between the DAC8534 and
a typical 8051-type microcontroller. The setup for the inter­face is as follows: TXD of the 8051 drives SCLK of the
DAC8534, while RXD drives the serial data line of the device.
The

SYNC

signal is derived from a bit-programmable pin on
the port of the 8051. In this case, port line P3.3 is used. When
data is to be transmitted to the DAC8534, P3.3 is taken LOW.
The 8051 transmits data in 8-bit bytes; thus only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left LOW after the first eight bits are transmitted,
then a second and third write cycle is initiated to transmit the
remaining data. P3.3 is taken HIGH following the completion
of the third write cycle. The 8051 outputs the serial data in a
format which presents the LSB first, while the DAC8534
requires its data with the MSB as the first bit received. The
8051 transmit routine must therefore take this into account,
and “mirror” the data as needed.

DAC8534

SBAS254D

15

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80C51/80L51

P3.3

TXD

RXD

(1)

DAC8534

SYNC
SCLK

D

IN

(1)

DAC8534 to TMS320 DSP INTERFACE

Figure 9 shows the connections between the DAC8534 and
a TMS320 Digital Signal Processor (DSP). A Single DSP can
control up to four DAC8534s without any interface logic.

NOTE: (1) Additional pins omitted for clarity.

FIGURE 6. DAC8534 to 80C51/80L51 Interface.

DAC8534 to Microwire INTERFACE

Figure 7 shows an interface between the DAC8534 and any
Microwire compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the
DAC8534 on the rising edge of the CK signal.

Microwire

NOTE: (1) Additional pins omitted for clarity.
Microwire is a registered trademark of National Semiconductor.

TM

CS
SK

SO

DAC8534

SYNC
SCLK
D

IN

(1)

FIGURE 7. DAC8534 to Microwire Interface.

DAC8534 to 68HC11 INTERFACE

Figure 8 shows a serial interface between the DAC8534 and
the 68HC11 microcontroller. SCK of the 68HC11 drives the
SCLK of the DAC8534, while the MOSI output drives the
serial data line of the DAC. The
a port line (PC7), similar to the 8051 diagram.

(1)

68HC11

PC7
SCK

MOSI

NOTE: (1) Additional pins omitted for clarity.

FIGURE 8. DAC8534 to 68HC11 Interface.

The 68HC11 should be configured so that its CPOL bit is 0
and its CPHA bit is 1. This configuration causes data appear­ing on the MOSI output to be valid on the falling edge of
SCLK. When data is being transmitted to the DAC, the

SYNC

line is held LOW (PC7). Serial data from the 68HC11
is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted MSB
first.) In order to load data to the DAC8534, PC7 is left LOW
after the first eight bits are transferred, then a second and
third serial write operation is performed to the DAC. PC7 is
taken HIGH at the end of this procedure.

SYNC

signal is derived from

DAC8534

SYNC
SCLK
D

IN

(1)

TMS320 DSP

FSX

DX

CLKX

DAC8534

SYNC

D

IN

SCLK

V

V

V

AV

OUT

OUT

V

GND

REF

REF

DD

A

D

H

L

Positive Supply

0.1µF10µF

Output A

Output D

Reference
Input

0.1µF1µF to 10µF

FIGURE 9. DAC8534 to TMS320 DSP.

APPLICATIONS

CURRENT CONSUMPTION

The DAC8534 typically consumes 250µA at AV
225µA at AV

= 3V for each active channel, including

DD

reference current consumption. Additional current consump­tion can occur at the digital inputs if V

<< IOVDD. For most

IH

efficient power operation, CMOS logic levels are recom­mended at the digital inputs to the DAC.
In power-down mode, typical current consumption is 200nA
per channel. A delay time of 10ms to 20ms after a power­down command is issued to the DAC is typically sufficient for
the power-down current to drop below 10µA.

DRIVING RESISTIVE AND CAPACITIVE LOADS

The DAC8534 output stage is capable of driving loads of up
to 1000pF while remaining stable. Within the offset and gain
error margins, the DAC8534 can operate rail-to-rail when
driving a capacitive load. Resistive loads of 2kΩ can be
driven by the DAC8534 while achieving a typical load regu­lation of 1%. As the load resistance drops below 2kΩ, the
load regulation error increases. When the outputs of the DAC
are driven to the positive rail under resistive loading, the
PMOS transistor of each Class-AB output stage can enter
into the linear region. When this occurs, the added IR voltage
drop deteriorates the linearity performance of the DAC. This
only occurs within approximately the top 20mV of the DAC’s
output voltage characteristic. The reference voltage applied
to the DAC8534 may be reduced below the supply voltage
applied to AV

in order to eliminate this condition if good

DD

linearity is a requirement at full-scale (under resistive loading
conditions).

CROSSTALK AND AC PERFORMANCE

The DAC8534 architecture uses separate resistor strings for
each DAC channel in order to achieve ultra-low crosstalk
performance. DC crosstalk seen at one channel during a full-

= 5V and

DD

16

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DAC8534

SBAS254D

REF02

DAC8534

3-Wire

Serial

Interface

+5V

AV

DD

, V

REF

V

OUT

= 0V to 5V

SYNC

SCLK

D

IN

+15

AIDD + I

REF

scale change on the neighboring channel is typically less than

0.5LSBs. The AC crosstalk measured (for a full-scale, 1kHz
sine wave output generated at one channel, and measured at
the remaining output channel) is typically under –100dB.
In addition, the DAC8534 can achieve typical AC perfor­mance of 96dB SNR (Signal-to-Noise Ratio) and 65dB THD
(Total Harmonic Distortion), making the DAC8534 a solid
choice for applications requiring high SNR at output frequen­cies at or below 4kHz.

OUTPUT VOLTAGE STABILITY

The DAC8534 exhibits excellent temperature stability of
5ppm/°C typical output voltage drift over the specified tem­perature range of the device. This enables the output voltage
of each channel to stay within a ±25µV window for a ±1°C
ambient temperature change.
Good Power-Supply Rejection Ratio (PSRR) performance
reduces supply noise present on AV

from appearing at the

DD

outputs to well below 10µV-s. Combined with good DC noise
performance and true 16-bit differential linearity, the DAC8534
becomes a perfect choice for closed-loop control applica­tions.

SETTLING TIME AND OUTPUT
GLITCH PERFORMANCE

Settling time to within the 16-bit accurate range of the
DAC8534 is achievable within 10µs for a full-scale code
change at the input. Worst-case settling times between
consecutive code changes is typically less than 2µs, en­abling update rates up to 500ksps for digital input signals
changing code-to-code. The high-speed serial interface of
the DAC8534 is designed in order to support these high
update rates.
For full-scale output swings, the output stage of each
DAC8534 channel typically exhibits less than 100mV of
overshoot and undershoot when driving a 200pF capacitive
load. Code-to-code change glitches are extremely low given
that the code-to-code transition does not cross an Nx4096
code boundary. Due to internal segmentation of the
DAC8534, code-to-code glitches occur at each crossing of
an Nx4096 code boundary. These glitches can approach
100nVs for N = 15, but settle out within ~2µs.

USING THE REF02 AS A POWER SUPPLY FOR
THE DAC8534

Due to the extremely low supply current required by the
DAC8534, a possible configuration is to use a REF02 +5V
precision voltage reference to supply the required voltage to
the DAC8534's supply input as well as the reference input, as
shown in Figure 10. This is especially useful if the power
supply is quite noisy or if the system supply voltages are at
some value other than 5V. The REF02 will output a steady
supply voltage for the DAC8534. If the REF02 is used, the
current it needs to supply to the DAC8534 is 1.085mA typical
and 1.78mA max for AV

= 5V. When a DAC output is

DD

loaded, the REF02 also needs to supply the current to the
load. The total typical current required (with a 5kΩ load on a

given DAC output) is:

1.085mA + (5V/ 5kΩ) = 2.085mA

FIGURE 10. REF02 as a Power Supply to the DAC8534.

BIPOLAR OPERATION USING THE DAC8534

The DAC8534 has been designed for single-supply opera­tion, but a bipolar output range is also possible using the
circuit in Figure 11. The circuit shown will give an output
voltage range of ±V
output is achievable using an amplifier such as the OPA703,
as shown in Figure 11.

. Rail-to-rail operation at the amplifier

REF

+5V

10µF 0.1µF

FIGURE 11. Bipolar Operation with the DAC8534.

DAC8534

SBAS254D

R

1

10kΩ

DAC8534

, V

AV

DD

REF

(Other pins omitted for clarity.)

www.ti.com

V

OUT

R

2

10kΩ

+5V

X

OPA703

-5V

±5V

17

The output voltage for any input code can be calculated as
follows:

VXV

OUT



=•



REF REF










65536





•









RR

D



+

12



R



1

–

V







R

2

•







R







1



where D represents the input code in decimal (0–65535).
With V

= 5V, R1 = R2 = 10kΩ:

REF

VX

OUT

=

10






65536

D

•



5–

V





This is an output voltage range of ±5V with 0000H corre­sponding to a –5V output and FFFF
output. Similarly, using V

= 2.5V, a ±2.5V output voltage

REF

corresponding to a +5V

H

range can be achieved.

LAYOUT

A precision analog component requires careful layout, ad­equate bypassing, and clean, well-regulated power supplies.

The DAC8534 offers single-supply operation, and it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switch­ing speed, the more difficult it will be to keep digital noise
from appearing at the output.

Due to the single ground pin of the DAC8534, all return
currents, including digital and analog return currents for the
DAC, must flow through a single point. Ideally, GND would
be connected directly to an analog ground plane. This plane
would be separate from the ground connection for the digital
components until they were connected at the power-entry
point of the system.

The power applied to AV

should be well regulated and low

DD

noise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high-frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between the power connec­tions and analog output.

As with the GND connection, AV

should be connected to

DD

a positive power-supply plane or trace that is separate from
the connection for digital logic until they are connected at the
power-entry point. In addition, a 1µF to 10µF capacitor in
parallel with a 0.1µF bypass capacitor is strongly recom­mended. In some situations, additional bypassing may be
required, such as a 100µF electrolytic capacitor or even a
“Pi” filter made up of inductors and capacitors—all designed
to essentially low-pass filter the supply, removing the high­frequency noise.

Up to four DAC8534 devices can be used on a single SPI bus
without any glue logic to create a high channel count solu­tion. Special attention is required to avoid digital signal
integrity problems when using multiple DAC8534s on the
same SPI bus. Signal integrity of

SYNC

, SCLK, and DIN lines
will not be an issue as long as the rise times of these digital
signals are longer than six times the propagation delay
between any two DAC8534 devices. Propagation speed is
approximately six inches/ns on standard PCBs. Therefore, if
the digital signal risetime is 1ns, the distance between any
two DAC8534 devices is recommended not to exceed 1 inch.
If the DAC8534s have to be further apart on the PCB, the
signal rise times should be reduced by placing series resis­tors at the drivers for

SYNC

, SCLK, and DIN lines. If the
largest distance between any two DAC8534s has to be six
inches, the risetime should be reduced to 6ns with an RC
network formed by the series resistor at the digital driver and
the total trace and input capacitance on the PCB.

18

www.ti.com

DAC8534

SBAS254D

PACKAGE OPTION ADDENDUM

www.ti.com

30-Mar-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

DAC8534IPW ACTIVE TSSOP PW 16 90 TBD CU NIPDAU Level-1-220C-UNLIM

DAC8534IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &

no Sb/Br)

DAC8534IPWR ACTIVE TSSOP PW 16 2000 TBD CU NIPDAU Level-1-220C-UNLIM

DAC8534IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DAT A

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15
0,05

8

1

A

DIM

14

0,10

6,60
6,20

M

0,10

0,15 NOM

2016

0°–8°

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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