TEXAS INSTRUMENTS DAC8218 Technical data

DAC8218

ControlLogic

An ogal Monit ro

ToDAC-0,DAC-1,

DAC-2,DAC-3

ToDAC-0,DAC-1,

DAC-2,DAC-3

ToDAC-4,DAC-5,DAC-6,DAC-7

DAC8218

OFFSET-B

AGND-B

V -7

OUT

MON

OFFSET-A

AGND-A

REF-B

Reference

BufferB

InternalTrimming

Zero/Gain;INL

Reference

BufferA

OFFSET

DACA

OFFSET

DACB

DAC-0

Latch-0

Power-Up/

Power-Down

Control

(SameFunctionBlocks

forAllChannels)

REF-A

LDAC

RST

RSTSEL

LDAC

CLR

USB/BTC

AIN-0

AIN-1

GPIO-0 GPIO-1 GPIO-2

SDO

SDI

SCLK

WAKEUP

SPIShiftRegister

IOVDDDGND DVDDAVDDAV

DGND DVDDAVDDAV

V -0

OUT

V -7

OUT

AIN-0

AIN-1 RefBufferA RefBufferB

OFFSET-B

Mux

Command

Registers

InputData Register0

Correction

Engine

(WhenCorrectionEngineDisabled)

DAC-0

Data

UserCalibration:

ZeroRegister0 GainRegsiter0

V -0

OUT

DAC8218

www.ti.com

SBAS460A –MAY 2009–REVISED DECEMBER 2009

Octal, 14-Bit, Low-Power, High-Voltage Output, Serial Input

DIGITAL-TO-ANALOG CONVERTER

Check for Samples: DAC8218

FEATURES

2345

• Bipolar Output: ±2V to ±16.5V

• Unipolar Output: 0V to +33V

• 14-Bit Resolution

• Low Power: 14.4mW/Ch (Bipolar Supply)

• Relative Accuracy: 1 LSB Max when operating from a +30.5V (or higher) power

• Low Zero/Full-Scale Error – Before User Calibration: ±2.5 LSB Max – After User Calibration: ±1 LSB

• Flexible System Calibration

• Low Glitch: 4nV-s

• Settling Time: 15μs

• Channel Monitor Output

• Programmable Gain: x4/x6

• Programmable Offset

• SPI™: Up to 50MHz, 1.8V/3V/5V Logic

• Schmitt Trigger Inputs

• Daisy-Chain with Sleep Mode Enhancement

• Packages: QFN-48 (7x7mm), TQFP-64 (10x10mm)

APPLICATIONS

• Automatic Test Equipment

• PLC and Industrial Process Control

• Communications

DESCRIPTION

The DAC8218 is a low-power, octal, 14-bit digital-to-analog converter (DAC). With a 5V reference, the output can either be a bipolar ±15V voltage when operating from dual ±15.5V (or higher) power supplies, or a unipolar 0V to +30V voltage

supply. With a 5.5V reference, the output can either be a bipolar ±16.5V voltage when operating from dual ±17V (or higher) power supplies, or a unipolar 0V to +33V voltage when operating from a +33.5V (or higher) power supply. This DAC provides low-power operation, good linearity, and low glitch over the specified temperature range of –40°C to +105°C. This device is trimmed in manufacturing and has very low zero-code and gain error. In addition, system level calibration can be performed to achieve ±1 LSB bipolar zero/full-scale error with bipolar supplies, or ±1 LSB zero code/full-scale error with a unipolar supply, over the entire signal chain. The output range can be offset by using the DAC offset register.

The DAC8218 features a standard, high-speed serial peripheral interface (SPI) that operates at up to 50MHz and is 1.8V, 3V, and 5V logic compatible, to communicate with a DSP or microprocessor. The input data of the device are double-buffered. An asynchronous load input (LDAC) transfers data from the DAC data register to the DAC latch. The asynchronous CLR input sets the output of all eight DACs to AGND. The V that connects to the individual analog outputs, the offset DAC, the reference buffer outputs, and two external inputs through a multiplexer (mux).

The DAC8218 is pin-to-pin and function-compatible with the DAC8718 (16-bit) and the DAC7718 (12-bit).

pin is a monitor output

MON

2DSP is a trademark of Texas Instruments. 3SPI, QSPI are trademarks of Motorola Inc. 4Microwire is a trademark of National Semiconductor. 5All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of allparameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DAC8218

SBAS460A –MAY 2009–REVISED DECEMBER 2009

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

(1)

RELATIVE DIFFERENTIAL SPECIFIED

ACCURACY LINEARITY PACKAGE- PACKAGE TEMPERATURE PACKAGE

PRODUCT (LSB) (LSB) LEAD DESIGNATOR RANGE MARKING

DAC8218

±1 ±1 QFN-48 RGZ –40°C to +105°C DAC8218 ±1 ±1 TQFP-64 PAG –40°C to +105°C DAC8218

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range (unless otherwise noted).

DAC8218 UNIT

AVDDto AV

AVDDto AGND –0.3 to 38 V AVSSto AGND, DGND –19 to 0.3 V DVDDto DGND –0.3 to 6 V IOVDDto DGND –0.3 to min of (6 or DVDD+ 0.3) V AGND-x to DGND –0.3 to 0.3 V Digital input voltage to DGND –0.3 to IOVDD+ 0.3 V SDO to DGND –0.3 to IOVDD+ 0.3 V V

OUT

-x, V

, AIN-x to AV

MON

REF-A, REF-B to AGND –0.3 to DV GPIO-n to DGND –0.3 to IOVDD+ 0.3 V GPIO-n input current 5 mA Maximum current from V

MON

Operating temperature range –40 to +105 °C Storage temperature range –65 to +150 °C Maximum junction temperature (TJmax) +150 °C

Human body model (HBM) 2.5 kV

ESD ratings Charged device model (CDM) 1000 V

Machine model (MM) 200 V

TQFP 55 °C/W QFN 27.5 °C/W TQFP 21 °C/W QFN 10.8 °C/W

Thermal impedance

Junction-to-ambient, θ

Junction-to-case, θ

Power dissipation (TJmax – TA) / θ

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

–0.3 to 38 V

–0.3 to AVDD+ 0.3 V

3 mA

Product Folder Link(s): DAC8218

DAC8218

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SBAS460A –MAY 2009–REVISED DECEMBER 2009

ELECTRICAL CHARACTERISTICS: Dual-Supply

All specifications at TA= T gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

STATIC PERFORMANCE

Resolution 14 Bits Linearity error Measured by line passing through codes 0000h and 3FFFh ±1 LSB Differential linearity error Measured by line passing through codes 0000h and 3FFFh ±1 LSB

Bipolar zero error TA= +25°C, before user calibration, gain = 4, code = 2000h ±4 LSB

Bipolar zero error TC Gain = 4 or 6, code = 2000h ±0.5 ±2 ppm FSR/°C

Zero-code error

Zero-code error TC Gain = 4 or 6, code = 0000h ±0.5 ±3 ppm FSR/°C

Gain error

Gain error TC Gain = 4 or 6 ±1 ±3 ppm FSR/°C

Full-scale error TA= +25°C, before user calibration, gain = 4, code = 3FFFh ±4 LSB

Full-scale error TC Gain = 4 or 6, code = 3FFFh ±0.5 ±3 ppm FSR/°C DC crosstalk

(3)

(1) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary

no more than ±3 LSB from the nominal number listed in Table 7. The Offset DAC pins are not intended to drive an external load, and

must not be connected during dual-supply operation. (2) Gain = 4 and TC specified by design and characterization. (3) The DAC outputs are buffered by op amps that share common AVDDand AVSSpower supplies. DC crosstalk indicates how much dc

change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With

high-impedance loads, the effect is virtually immeasurable. Multiple AVDDand AVSSterminals are provided to minimize dc crosstalk.

(2)

to T

MIN

TA= +25°C, before user calibration, gain = 6, code = 2000h ±2.5 LSB

TA= +25°C, after user calib., gain = 4 or 6, code = 2000h ±1 LSB

TA= +25°C, gain = 6, code = 0000h ±2.5 LSB TA= +25°C, gain = 4, code = 0000h ±4 LSB

TA= +25°C, gain = 6 ±2.5 LSB TA= +25°C, gain = 4 ±4 LSB

TA= +25°C, before user calibration, gain = 6, code = 3FFFh ±2.5 LSB

TA= +25°C, after user calib., gain = 4 or 6, code = 3FFFh ±1 LSB

Measured channel at code = 2000h, full-scale change on any other channel

, AVDD= +16.5V, AVSS= –16.5V, IOVDD= DVDD= +5V, REF-A and REF-B = +5V,

MAX

DAC8218

0.05 LSB

(1)

Product Folder Link(s): DAC8218

DAC8218

SBAS460A –MAY 2009–REVISED DECEMBER 2009

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ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)

All specifications at TA= T gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

ANALOG OUTPUT (V

Voltage output

Output impedance Code = 2000h 0.5 Ω Short-circuit current Load current See Figure 37 ±3 mA

Output drift vs time

Capacitive load stability 500 pF

Settling time 15 μs

Slew rate Power-on delay Power-down recovery time 60 μs Digital-to-analog glitch Glitch impulse peak amplitude Code from 1FFFh to 2000h and 2000h to 1FFFh 5 mV Channel-to-channel isolation

DAC-to-DAC crosstalk

Digital crosstalk Digital feedthrough

Output noise TA= +25°C at 10kHz, gain = 4 130 nV/√Hz

Power-supply rejection

(5)

(7)

(8)

(12)

(4) Specified by design. (5) The analog output range of V

the analog output must not be greater than (AVDD– 0.5V), and the minimum value must not be less than (AVSS+ 0.5V). All

specifications are for a ±16.5V power supply and a ±15V output, unless otherwise noted. (6) When the output current is greater than the specification, the current is clamped at the specified maximum value. (7) Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale. (8) Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid

digital communication. (9) Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as

the area of the glitch in nV-s. It is measured by toggling the DAC register data between 1FFFh and 2000h in straight binary format. (10) Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the

sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale. (11) DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and

subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s. (12) Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input

register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s. (13) Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of

the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s. (14) The output must not be greater than (AVDD– 0.5V) and not less than (AVSS+ 0.5V).

(13)

-0 to V

OUT

(6)

(9)

(11)

(14)

to T

MIN

-7)

OUT

V V

TA= +25°C, device operating for 500 hours, full-scale output 3.4 ppm of FSR TA= +25°C, device operating for 1000 hours, full-scale output 4.3 ppm of FSR

To 0.03% of FSR, CL= 200pF, RL= 10kΩ, code from 0000h to 3FFFh and 3FFFh to 0000h

To 1 LSB, CL= 200pF, RL= 10kΩ, code from 0000h to 3FFFh and 3FFFh to 0000h

To 1 LSB, CL= 200pF, RL= 10kΩ, code from 1FC0h to 2040h and 2040h to 1FC0h

From IOVDD≥ +1.8V and DVDD≥ +2.7V to CS low 200 μs

Code from 1FFFh to 2000h and 2000h to 1FFFh 4 nV-s

(10)

V DACs in the same group 7.5 nV-s DACs among different groups 1 nV-s

TA= +25°C at 10kHz, gain = 6 200 nV/√Hz

0.1Hz to 10Hz, gain = 6 20 μV AVDD= ±15.5V to ±16.5V 0.05 LSB

, AVDD= +16.5V, AVSS= –16.5V, IOVDD= DVDD= +5V, REF-A and REF-B = +5V,

MAX

DAC8218

(4)

= +5V –15 +15 V

REF

= +1.5V –4.5 +4.5 V

REF

±8 mA

10 μs

6 μs 6 V/μs

= 4VPP, f = 1kHz 88 dB

REF

1 nV-s 1 nV-s

OUT

-0 to V

-7 is equal to (6 × V

OUT

– 5 × OUTPUT_OFFSET_DAC) for gain = 6. The maximum value of

REF

(1)

Product Folder Link(s): DAC8218

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SBAS460A –MAY 2009–REVISED DECEMBER 2009

ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)

All specifications at TA= T gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

OFFSET DAC OUTPUT

Voltage output V Full-scale error TA= +25°C ±1 LSB Zero-code error TA= +25°C ±0.5 LSB Linearity error ±1.5 LSB Differential linearity error ±1 LSB

ANALOG MONITOR PIN (V

Output impedance Three-state leakage current 100 nA

AUXILIARY ANALOG INPUT

Input range AV Input impedance

(AIN-x to V

MON

) Input capacitance Input leakage current 30 nA

REFERENCE INPUT

Reference input voltage range Reference input dc impedance 10 MΩ Reference input capacitance

DIGITAL INPUT

High-level input voltage, V

Low-level input voltage, V

Input current

Input capacitance USB/BTC and RSTSEL 12 pF

DIGITAL OUTPUT

High-level output voltage, V (SDO)

Low-level output voltage, V (SDO)

GPIO-n output voltage low, V GPIO-n output voltage high, VOH10kΩ pull-up resistor to IOV High-impedance leakage current SDO and GPIO-n ±5 μA

High-impedance output capacitance

(15) Specified by design. (16) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary

no more than ±3 LSB from the nominal number listed in Table 7. The Offset DAC pins are not intended to drive an external load, and

must not be connected during dual-supply operation. (17) 8kΩ when V (18) Reference input voltage ≤ DVDD.

(15) (16)

(17)

(15)

is connected to Reference Buffer A or B, and 4kΩ when V

MON

to T

MIN

, AVDD= +16.5V, AVSS= –16.5V, IOVDD= DVDD= +5V, REF-A and REF-B = +5V,

MAX

DAC8218

= +5V 0 5 V

REF

)

MON

TA= +25°C 2 kΩ

TA= +25°C 2 kΩ

4 pF

(18)

(15)

1.0 5.5 V

10 pF

IOVDD= +4.5V to +5.5V 3.8 0.3 + IOV IOVDD= +2.7V to +3.3V 2.3 0.3 + IOV IOVDD= +1.7V to 2.0V 1.5 0.3 + IOV IOVDD= +4.5V to +5.5V –0.3 0.8 V IOVDD= +2.7V to +3.3V –0.3 0.6 V IOVDD= +1.7V to 2.0V –0.3 0.3 V CLR, LDAC, RST, CS, and SDI ±1 μA USB/BTC, RSTSEL, and GPIO-n ±5 μA CLR, LDAC, RST, CS, and SDI 5 pF

GPIO-n 14 pF

IOVDD= +2.7V to +5.5V, sourcing 1mA IOVDD– 0.4 IOV IOVDD= +1.8V, sourcing 200μA 1.6 IOV IOVDD= +2.7V to +5.5V, sinking 1mA 0 0.4 V IOVDD= +1.8V, sinking 200μA 0 0.2 V 1mA sink from IOV

0.99 × IOV

0.15 V

SDO 5 pF GPIO-n 14 pF

is connected to Offset DAC-A or -B.

MON

(1)

DD DD DD

DD DD

V V V

V V

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DAC8218

SBAS460A –MAY 2009–REVISED DECEMBER 2009

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ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)

All specifications at TA= T gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

POWER SUPPLY

(19)

IOV

IOI

Power dissipation Normal operation, ±16.5V supplies, midscale code 115 165 mW

TEMPERATURE RANGE

Specified performance –40 +105 °C

(19) IOVDD≤ DVDD.

to T

MIN

Normal operation, midscale code, output unloaded 4.3 6 mA Power down, output unloaded 35 μA Normal operation, midscale code, output unloaded –4 –2.7 mA Power down, output unloaded 35 μA Normal operation 78 μA Power down 36 μA Normal operation, VIH= IOVDD, VIL= DGND 5 μA Power down, VIH= IOVDD, VIL= DGND 5 μA

, AVDD= +16.5V, AVSS= –16.5V, IOVDD= DVDD= +5V, REF-A and REF-B = +5V,

MAX

DAC8218

+4.5 +18 V

–18 –4.5 V +2.7 +5.5 V +1.8 +5.5 V

(1)

Product Folder Link(s): DAC8218

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SBAS460A –MAY 2009–REVISED DECEMBER 2009

ELECTRICAL CHARACTERISTICS: Single-Supply

All specifications at TA= T AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

STATIC PERFORMANCE

Resolution 14 Bits Linearity error Measured by line passing through codes 0040h and 3FFFh ±1 LSB Differential linearity error Measured by line passing through codes 0040h and 3FFFh ±1 LSB

Unipolar zero error TA= +25°C, before user calibration, gain = 4, code = 0040h ±4 LSB

Unipolar zero error TC Gain = 4 or 6, code = 0040h ±0.5 ±3 ppm FSR/°C

Gain error

Gain error TC Gain = 4 or 6 ±1 ±3 ppm FSR/°C

Full-scale error TA= +25°C, before user calibration, gain = 4, code = 3FFFh ±4 LSB

Full-scale error TC Gain = 4 or 6, code = 3FFFh ±0.5 ±3 ppm FSR/°C DC crosstalk

ANALOG OUTPUT (V

Voltage output

Output impedance Code = 2000h 0.5 Ω Short-circuit current Load current SeeFigure 84 and Figure 85 ±3 mA

Output drift vs time

Capacitive load stability 500 pF

Settling time 15 μs

Slew rate Power-on delay Power-down recovery time 90 μs Digital-to-analog glitch Glitch impulse peak amplitude Code from 1FFFh to 2000h and 2000h to 1FFFh 5 mV Channel-to-channel isolation

(2)

(4)

(6)

(7)

(1) Gain = 4 and TC specified by design and characterization. (2) The DAC outputs are buffered by op amps that share common AVDDand AVSSpower supplies. DC crosstalk indicates how much dc

change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With

high-impedance loads, the effect is virtually immeasurable. Multiple AVDDand AVSSterminals are provided to minimize dc crosstalk. (3) Specified by design. (4) The analog output range of V

greater than (AVDD– 0.5V). All specifications are for a +32V power supply and a 0V to +30V output, unless otherwise noted. (5) When the output current is greater than the specification, the current is clamped at the specified maximum value. (6) Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale. (7) Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid

digital communication. (8) Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as

the area of the glitch in nV-s. It is measured by toggling the DAC register data between 1FFFh and 2000h in straight binary format. (9) Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the

sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale.

(1)

-0 to V

OUT

(5)

(8)

to T

MIN

TA= +25°C, before user calibration, gain = 6, code = 0040h ±2.5 LSB

TA= +25°C, after user calib., gain = 4 or 6, code = 0040h ±1 LSB

TA= +25°C, gain = 6 ±2.5 LSB TA= +25°C, gain = 4 ±4 LSB

TA= +25°C, before user calibration, gain = 6, code = 3FFFh ±2.5 LSB

TA= +25°C, after user calib., gain = 4 or 6, code = 3FFFh ±1 LSB

Measured channel at code = 2000h, full-scale change on any other channel

-7)

OUT

REF

TA= +25°C, device operating for 500 hours, full-scale output 3.4 ppm of FSR TA= +25°C, device operating for 1000 hours, full-scale output 4.3 ppm of FSR

To 0.03% of FSR, CL= 200pF, RL= 10kΩ, code from 0040h to 3FFFh and 3FFFh to 0040h

To 1 LSB, CL= 200pF, RL= 10kΩ, code from 0040h to 3FFFh and 3FFFh to 0040h

To 1 LSB, CL= 200pF, RL= 10kΩ, code from 1FC0h to 2040h and 2040h to 1FC0h

From IOVDD≥ +1.8V and DVDD≥ +2.7V to CS low 200 μs

Code from 1FFFh to 2000h and 2000h to 1FFFh 4 nV-s

(9)

REF

, AVDD= +32V, AVSS= 0V, IOVDD= DVDD= +5V, REF-A and REF-B = +5V, gain = 6,

MAX

DAC8218

0.05 LSB

(3)

= +5V 0 +30 V = +1.5V 0 +9 V

±8 mA

10 μs

6 μs 6 V/μs

= 4VPP, f = 1kHz 88 dB

OUT

-0 to V

-7 is equal to (6 × V

OUT

) for gain = 6. The maximum value of the analog output must not be

REF

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SBAS460A –MAY 2009–REVISED DECEMBER 2009

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ELECTRICAL CHARACTERISTICS: Single-Supply (continued)

All specifications at TA= T AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

DAC-to-DAC crosstalk

Digital crosstalk Digital feedthrough

Output noise TA= +25°C at 10kHz, gain = 4 130 nV/√Hz

Power-supply rejection

ANALOG MONITOR PIN (V

Output impedance Three-state leakage current 100 nA

AUXILIARY ANALOG INPUT

Input range AV Input impedance

(AIN-x to V

MON

Input capacitance Input leakage current 30 nA

REFERENCE INPUT

Reference input voltage

(16)

range Reference input dc impedance 10 MΩ Reference input capacitance

DIGITAL INPUT

High-level input voltage, V

Low-level input voltage, V

Input current

Input capacitance USB/BTC and RSTSEL 12 pF

(10) DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and

subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s. (11) Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input

register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s. (12) Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of

the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s. (13) The analog output must not be greater than (AVDD– 0.5V). (14) 8kΩ when V (15) Specified by design. (16) Reference input voltage ≤ DVDD.

(10)

(11)

(12)

(13)

(14)

)

(15)

is connected to Reference Buffer A or B, and 4kΩ when V

MON

to T

MIN

, AVDD= +32V, AVSS= 0V, IOVDD= DVDD= +5V, REF-A and REF-B = +5V, gain = 6,

MAX

DAC8218

DACs in the same group 10 nV-s DACs among different groups 1 nV-s

1 nV-s 1 nV-s

TA= +25°C at 10kHz, gain = 6 200 nV/√Hz

0.1Hz to 10Hz, gain = 6 20 μV AVDD= +33V to +36V 0.05 LSB

)

MON

TA= +25°C 2 kΩ

TA= +25°C 2 kΩ

4 pF

1.0 5.5 V

(15)

IOVDD= +4.5V to +5.5V 3.8 0.3 + IOV IOVDD= +2.7V to +3.3V 2.3 0.3 + IOV IOVDD= +1.7V to 2.0V 1.5 0.3 + IOV

10 pF

DD DD DD

IOVDD= +4.5V to +5.5V –0.3 0.8 V IOVDD= +2.7V to +3.3V –0.3 0.6 V IOVDD= +1.7V to 2.0V –0.3 0.3 V CLR, LDAC, RST, CS, and SDI ±1 μA USB/BTC, RSTSEL, and GPIO-n ±5 μA CLR, LDAC, RST, CS, and SDI 5 pF

GPIO-n 14 pF

is connected to Offset DAC-A or -B.

MON

V V V

Product Folder Link(s): DAC8218

DAC8218

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SBAS460A –MAY 2009–REVISED DECEMBER 2009

ELECTRICAL CHARACTERISTICS: Single-Supply (continued)

All specifications at TA= T AGND-x = DGND = 0V, data format = straight binary, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNIT

DIGITAL OUTPUT

High-level output voltage, V (SDO)

Low-level output voltage, V (SDO)

GPIO-n output voltage low, VOL1mA sink from IOV GPIO-n output voltage high, VOH10kΩ pull-up resistor to IOV High-impedance leakage current SDO and GPIO-n ±5 μA

High-impedance output capacitance

POWER SUPPLY

(18)

IOV

IOI

Power dissipation Normal operation 140 225 mW

TEMPERATURE RANGE

Specified performance –40 +105 °C

(17) Specified by design. (18) IOVDD≤ DVDD.

(17)

to T

MIN

, AVDD= +32V, AVSS= 0V, IOVDD= DVDD= +5V, REF-A and REF-B = +5V, gain = 6,

MAX

DAC8218

IOVDD= +2.7V to +5.5V, sourcing 1mA IOVDD– 0.4 IOV IOVDD= +1.8V, sourcing 200μA 1.6 IOV

DD DD

IOVDD= +2.7V to +5.5V, sinking 1mA 0 0.4 V IOVDD= +1.8V, sinking 200μA 0 0.2 V

0.99 × IOV

0.15 V

SDO 5 pF GPIO-n 14 pF

+9 +36 V +2.7 +5.5 V +1.8 +5.5 V

Normal operation, midscale code, output unloaded 4.5 7 mA Power down, output unloaded 35 µA Normal operation 70 μA Power down 36 μA Normal operation, VIH= IOVDD, VIL= DGND 5 μA Power down, VIH= IOVDD, VIL= DGND 5 μA

V V

Product Folder Link(s): DAC8218

ControlLogic

An ogal Monit ro

ToDAC-0,DAC-1,

DAC-2,DAC-3

ToDAC-0,DAC-1,

DAC-2,DAC-3

ToDAC-4,DAC-5,DAC-6,DAC-7

DAC8218

OFFSET-B

AGND-B

V -7

OUT

MON

OFFSET-A

AGND-A

REF-B

Reference

BufferB

InternalTrimming

Zero/Gain;INL

Reference

BufferA

OFFSET

DACA

OFFSET

DACB

DAC-0

Latch-0

Power-Up/

Power-Down

Control

(SameFunctionBlocks

forAllChannels)

REF-A

LDAC

RST

RSTSEL

LDAC

CLR

USB/BTC

AIN-0

AIN-1

GPIO-0 GPIO-1 GPIO-2

SDO

SDI

SCLK

WAKEUP

SPIShiftRegister

IOVDDDGND DV

DGND DV

V -0

OUT

V -7

OUT

AIN-0

AIN-1 RefBufferA RefBufferB

OFFSET-B

Mux

Command

Registers

InputData Register0

Correction

Engine

(WhenCorrectionEngineDisabled)

DAC-0

Data

UserCalibration:

ZeroRegister0 GainRegsiter0

V -0

OUT

DAC8218

SBAS460A –MAY 2009–REVISED DECEMBER 2009

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Block Diagram

Product Folder Link(s): DAC8218

AIN-1

V -4

OUT

REF-B

V -5

OUT

V -6

OUT

AGND-B

OFFSET-B

V -7

OUT

AIN-0

V -3

OUT

REF-A

V -2

OUT

V -1

OUT

AGND-A

OFFSET-A

V -0

OUT

MON

WAKEUP

LDAC

SDONCSDICSSCLK

IOV

DGNDNCNC

RSTSEL

USB/BTC

GPIO-2

CLR

RST

DGND

GPIO-1

GPIO-0

64 63 62 61 60 59 58 57 56 55 54

18 19 20

21 222324

25 26

53 52 51 50 49

28 29 30 31 32

DAC8218

AIN-0

V -3

OUT

REF-A

V -2

OUT

V -1

OUT

AGND-A

OFFSET-A

V -0

OUT

MON

AIN-1

V -4

OUT

REF-B

V -5

OUT

V -6

OUT

AGND-B

OFFSET-B

V -7

OUT

DAC8218

WAKEUP

LDAC

SDO

SDICSSCLK

IOV

DGNDNCRSTSEL

USB/BTC

4847464544434241403938

GPIO-2

CLR

RST

DGND

GPIO-1

GPIO-0

1314151617181920212223

DAC8218

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PAG PACKAGE

TQFP-64

(TOP VIEW)

SBAS460A –MAY 2009–REVISED DECEMBER 2009

PIN CONFIGURATIONS

RGZ PACKAGE

QFN-48

(TOP VIEW)

NAME

AIN-0 2 3 I Auxiliary analog input 0, directly routed to the analog mux

-3 3 4 O DAC-3 output

OUT

REF-A 4 5 I Group A V

-2 5 6 O DAC-2 output

OUT

-1 6 7 O DAC-1 output

OUT

AGND-A 7 8 I Group A analog ground and the ground of REF-A. This pin must be tied to AGND-B and DGND. AGND-A 8 9 I Group A analog ground and the ground of REF-A. This pin must be tied to AGND-B and DGND.

OFFSET-A 9 10 O

(1) Group A consists of DAC-0, DAC-1, DAC-2, and DAC-3. Group B consists of DAC-4, DAC-5, DAC-6, and DAC-7.

-0 10 11 O DAC-0 output

OUT

MON

GPIO-2 13 19 I/O

CLR 14 20 I through switches and internal low-impedance. When the CLR pin is logic '1', all V

RST 15 21 I

(1) The thermal pad is internally connected to

the substrate. This pad can be connected to AVSSor left floating. Keep the thermal pad separate from the digital ground, if possible.

PIN DESCRIPTIONS

PIN NO.

QFN-48 TQFP-64 I/O DESCRIPTION

1 1 I Positive analog power supply

(1)

reference input

11 12 I Negative analog power supply

12 14 O reference buffer outputs, offset DAC outputs, or one of the auxiliary analog inputs, depending on

OFFSET DAC-A analog output. Must be connected to AGND-A during single power-supply operation (AVSS= 0V). This pin is not intended to drive an external load.

Analog monitor output. This pin is either in Hi-Z status, connected to one of the eight DAC outputs, the content of the Monitor Register. See the Monitor Register, Table 12, for details.

General-purpose digital input/output 2. This pin is a bidirectional digital input/output, open-drain and requires an external pull-up resistor. See the GPIO Pins section for details.

Clear input, level triggered. When the CLR pin is logic '0', all V connect to the amplifier outputs.

Reset input (active low). Logic low on this pin resets the DAC registers and DACs to the values defined by the RSTSEL pin. CS must be logic high when RST is active.

Product Folder Link(s): DAC8218

-X pins connect to AGND-x

OUT

-X pins

DAC8218

SBAS460A –MAY 2009–REVISED DECEMBER 2009

PIN DESCRIPTIONS (continued)

NAME

DGND 20 25 I Digital ground DGND 22 28 I Digital ground

GPIO-1 23 29 I/O

GPIO-0 24 30 I/O

-7 27 38 O DAC-7 output

OUT

OFFSET-B 28 39 O

AGND-B 29 40 I Group B AGND-B 30 41 I Group B analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND.

-6 31 42 O DAC-6 output

OUT

-5 32 43 O DAC-5 output

OUT

REF-B 33 44 I Group B reference input V

-4 34 45 O DAC-4 output

OUT

AIN-1 35 46 I Auxiliary analog input 1, directly routed to the analog mux

USB/BTC 37 50 I when connected to DGND or in twos complement format when connected to IOVDD. The command

RSTSEL 38 51 I

DGND 40 54 I Digital ground

IOV

SCLK 43 57 I SPI bus serial clock input

CS 44 58 I

SDI 45 59 I SPI bus serial data input

SDO 46 61 O

LDAC 47 62 I

WAKEUP 48 63 I

NC — Not connected

PIN NO.

QFN-48 TQFP-64 I/O DESCRIPTION

17 24 I Digital power supply

General-purpose digital input/output 1. This pin is a bidirectional digital input/output, open-drain and requires an external resistor. See the GPIO Pins section for details.

General-purpose digital input/output 0. This pin is a bidirectional digital input/output, open-drain and requires an external resistor. See the GPIO Pins section for details.

26 37 I Negative analog power supply

OFFSET DAC-B analog output. Must be connected to AGND-B during single-supply operation (AVSS= 0V).

(1)

analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND.

36 48 I Positive analog power supply

Data format selection of Input DAC data and Offset DAC data. Data are in straight binary format data are always in straight binary format. Refer to Input Data Format section for details.

Output reset selection. Selects the output voltage on the V Refer to the Power-On Reset section for details.

41 55 I Interface power 42 56 I Digital power supply

SPI bus chip select input (active low). Data are not clocked into SDI unless CS is low. When CS is high, SDO is in a high-impedance state and the SCLK and SDI signals are blocked from the device.

SPI bus serial data output. When the DSDO bit = '0', the SDO pin works as an output in normal operation. When the DSDO bit = '1', SDO is always in a Hi-Z state, regardless of the CS pin status. Refer to the Timing Diagrams section for details.

Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the contents of the DAC Data Register are transferred to it. The DAC output changes to the corresponding level simultaneously when the DAC latch is updated. See the Updating the DAC

Outputs section for details. If asynchronous mode is desired, LDAC must be permanently tied low

before power is applied to the device. If synchronous mode is desired, LDAC must be logic high during power-on.

Wake-up input (active low). Restores the SPI from sleep to normal operation. See the Daisy-Chain

Operation section for details.

2, 13,

15-18, 22,

16, 18, 19, 23, 26, 27,

21, 25, 39 31-36, 47,

49, 52, 53,

60, 64

pin after power-on or hardware reset.

OUT

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Product Folder Link(s): DAC8218

SCLK

InputDataRegisterand

DACLatchUpdated

WhenCorrectionCompletes

(1)

DACLatchUpdated

(2)

SDI

BIT23(MSB)

BIT22 BIT1

Low

BIT0

LDAC

Ifthecorrectionengineisoff,theDAClatchisreloadedimmediatelyaftertheDACDataRegisterisupdated.NOTE:(1)

TheDAClatchisupdatedwhen goeslow,aslongasthetimingrequirementoft issatisfied.

LDAC

NOTE:(2)

Case1:Standalonemode:Updatewithout pin; tiedtologiclowLDAC LDAC pin .

SCLK

InputDataRegisterUpdated,

butDACLatchisNot Updated

SDI

BIT22 BIT1

High

BIT0

LDAC

Case2:Standalonemode:Updatewith pin.LDAC

=Don’tCare

Bit23=MSB Bit0=LSB

DAC8218

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TIMING DIAGRAMS

SBAS460A –MAY 2009–REVISED DECEMBER 2009

Figure 2. SPI Timing for Standalone Mode

Product Folder Link(s): DAC8218

SCLK

SDI

BIT23(N)

BIT22(N) BIT0(N) BIT23(N+1)

BIT23(N) BIT0(N)

Low

BIT0(N+1)

SDO

LDAC

Ifthecorrectionengineisoff,theDAClatchisreloadedimmediatelyaftertheDACDataRegisterisupdated.NOTE:(1)

TheDAClatchisupdatedwhen goeslow.Theproperdataareloadedifthet timingrequirementissatisfied. Otherwise,invaliddataareloaded.

LDAC

NOTE:(2)

Case3:Daisy-ChainMode:Updatewithout pin; pintiedtologiclow.LDAC LDAC

High

LDAC

=Don’tCare

Bit23=MSB Bit0=LSB

SCLK

InputDataRegisterUpdated,

butDACLatchisNotUpdated

SDI

BIT23(N)

BIT22(N) BIT0(N) BIT23(N+1)

BIT23(N) BIT0(N)

BIT0(N+1)

SDO

Case4:Daisy-ChainMode:Updatewith pin.LDAC

DACLatchUpdated

(2)

InputDataRegisterand

DACLatchUpdated

WhenCorrectionCompletes

(1)

DB23 DB0

Case5:Daisy-ChainMode:Sleeping.

SCLK

SDI

FirstWord LastWord

DB23 DB0

SDO

DB23 DB0

Hi-Z

Hi-Z Hi-Z Hi-Z

Hi-Z Hi-Z

Hi-Z

DAC8218

SBAS460A –MAY 2009–REVISED DECEMBER 2009

TIMING DIAGRAMS (continued)

www.ti.com

Figure 3. SPI Timing for Daisy-Chain Mode

Product Folder Link(s): DAC8218

Case6:ReadbackforStandalonemode.

BIT23(=1) BIT22

InputWordSpecifiesRegistertobeRead

NOPCommand(write ‘1’ toNOPbit)

DatafromtheSelectedRegister

BIT0

BIT23

BIT23(=1)

BIT22

BIT1

BIT0

InternalRegisterUpdated

SCLK

SDI

SDO

LDAC

Low

=Don’tCare

Bit23=MSB Bit0=LSB

Hi-Z Hi-Z Hi-Z

DAC8218

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TIMING DIAGRAMS (continued)

Figure 4. SPI Timing for Readback Operation in Standalone Mode

SBAS460A –MAY 2009–REVISED DECEMBER 2009

Product Folder Link(s): DAC8218

DAC8218

SBAS460A –MAY 2009–REVISED DECEMBER 2009

TIMING CHARACTERISTICS: IOVDD= +5V

(1)(2)(3)(4)

At –40°C to +105°C, DVDD= +5V, and IOVDD= +5V, unless otherwise noted.

PARAMETER MIN MAX UNIT

SCLK

Clock frequency 50 MHz SCLK cycle time 20 ns SCLK high time 10 ns SCLK low time 7 ns CS falling edge to SCLK falling edge setup time 8 ns SDI setup time before falling edge of SCLK 5 ns SDI hold time after falling edge of SCLK 5 ns SCLK falling edge to CS rising edge 5 ns CS high time 10 ns CS rising edge to LDAC falling edge 5 ns LDAC pulse duration 10 ns Delay from SCLK rising edge to SDO valid 3 8 ns Delay from CS rising edge to SDO Hi-Z 5 ns Delay from CS falling edge to SDO valid 6 ns SDI to SDO delay during sleep mode 2 5 ns

(1) Specified by design. Not production tested. (2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters. (3) All input signals are specified with tR= tF= 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2. (4) SDO loaded with 10Ω series resistance and 10pF load capacitance for SDO timing specifications.

BLANKSPACE

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TIMING CHARACTERISTICS: IOVDD= +3V

(1)(2)(3)(4)

At –40°C to +105°C, DVDD= +3V/+5V, and IOVDD= +3V, unless otherwise noted.

PARAMETER MIN MAX UNIT

SCLK

(1) Specified by design. Not production tested. (2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters. (3) All input signals are specified with tR= tF= 3ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2. (4) SDO loaded with 10Ω series resistance and 10pF load capacitance for SDO timing specifications.

Clock frequency 25 MHz SCLK cycle time 40 ns SCLK high time 19 ns SCLK low time 7 ns CS falling edge to SCLK falling edge setup time 15 ns SDI setup time before falling edge of SCLK 5 ns SDI hold time after falling edge of SCLK 5 ns SCLK falling edge to CS rising edge 10 ns CS high time 19 ns CS rising edge to LDAC falling edge 5 ns LDAC pulse duration 10 ns Delay from SCLK rising edge to SDO valid 3 15 ns Delay from CS rising edge to SDO Hi-Z 7 ns Delay from CS falling edge to SDO valid 10 ns SDI to SDO delay during sleep mode 2 10 ns

Product Folder Link(s): DAC8218

DAC8218

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TIMING CHARACTERISTICS: IOVDD= +1.8V

(1)(2)(3)(4)

SBAS460A –MAY 2009–REVISED DECEMBER 2009

At –40°C to +105°C, DVDD= +3V/+5V, and IOVDD= +1.8V, unless otherwise noted.

PARAMETER MIN MAX UNIT

SCLK

(1) Specified by design. Not production tested. (2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters. (3) All input signals are specified with tR= tF= 6ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2. (4) SDO loaded with 10Ω series resistance and 10pF load capacitance for SDO timing specifications.

Clock frequency 16.6 MHz SCLK cycle time 60 ns SCLK high time 28 ns SCLK low time 7 ns CS falling edge to SCLK falling edge setup time 28 ns SDI setup time before falling edge of SCLK 10 ns SDI hold time after falling edge of SCLK 5 ns SCLK falling edge to CS rising edge 10 ns CS high time 28 ns CS rising edge to LDAC falling edge 5 ns LDAC pulse duration 10 ns Delay from SCLK rising edge to SDO valid 3 25 ns Delay from CS rising edge to SDO Hi-Z 15 ns Delay from CS falling edge to SDO valid 23 ns SDI to SDO delay during sleep mode 2 25 ns

Product Folder Link(s): DAC8218

1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

INLError(LSB)

AllEightChannelsShown

2048

16384143361228810240819261444096

DigitalInputCode

1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

DNLError(LSB)

AllEightChannelsShown

2048

16384143361228810240819261444096

DigitalInputCode

1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

INLError(LSB)

2048

16384143361228810240819261444096

DigitalInputCode

TypicalChannelShown

Gain=4

1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

DNLError(LSB)

2048

16384143361228810240819261444096

DigitalInputCode

TypicalChannelShown

Gain=4

DAC8218

SBAS460A –MAY 2009–REVISED DECEMBER 2009

TYPICAL CHARACTERISTICS: Bipolar

At TA= 25°C, AVDD= 16.5V, AVSS= –16.5V, V

LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (All 8 Channels) vs DIGITAL INPUT CODE (All 8 Channels)

Figure 5. Figure 6.

LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C) vs DIGITAL INPUT CODE (+25°C)

www.ti.com

= IOVDD= DVDD= 5V, gain = 6, data format=USB, unless otherwise noted.

REF

Figure 7. Figure 8.

Product Folder Link(s): DAC8218

1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

INLError(LSB)

TypicalChannelShown

2048

16384143361228810240819261444096

DigitalInputCode

1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

DNLError(LSB)

TypicalChannelShown

2048

16384143361228810240819261444096

DigitalInputCode

1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

INLError(LSB)

TypicalChannelShown

2048

16384143361228810240819261444096

DigitalInputCode

1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

DNLError(LSB)

TypicalChannelShown

2048

16384143361228810240819261444096

DigitalInputCode

1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

INLError(LSB)

TypicalChannelShown

2048

16384143361228810240819261444096

DigitalInputCode

1.0

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

-0.8

-1.0

DNLError(LSB)

TypicalChannelShown

2048

16384143361228810240819261444096

DigitalInputCode

DAC8218

www.ti.com

TYPICAL CHARACTERISTICS: Bipolar (continued)

At TA= 25°C, AVDD= 16.5V, AVSS= –16.5V, V

LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C) vs DIGITAL INPUT CODE (–40°C)

Figure 9. Figure 10.

LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+25°C) vs DIGITAL INPUT CODE (+25°C)

SBAS460A –MAY 2009–REVISED DECEMBER 2009

= IOVDD= DVDD= 5V, gain = 6, data format=USB, unless otherwise noted.

REF

Figure 11. Figure 12.

LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (+105°C) vs DIGITAL INPUT CODE (+105°C)

Figure 13. Figure 14.

Product Folder Link(s): DAC8218

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