Texas Instruments DAC7802LU-1K, DAC7802LP, DAC7802KU-1K, DAC7802KP, DAC7800KP Datasheet

DESCRIPTION

The DAC7800, DAC7801 and DAC7802 are members of a
new family of monolithic dual 12-bit CMOS multiplying Digi­tal-to-Analog Converters (DACs). The digital interface speed
and the AC multiplying performance are achieved by using
an advanced CMOS process optimized for data conversion
circuits. High stability on-chip resistors provide true 12-bit
integral and differential linearity over the wide industrial
temperature range of –40°C to +85°C.

DAC7800 features a serial interface capable of clocking-in
data at a rate of at least 10MHz. Serial data is clocked (edge
triggered) MSB first into a 24-bit shift register and then
latched into each DAC separately or simultaneously as
required by the application. An asynchronous CLEAR control
is provided for power-on reset or system calibration func­tions. It is packaged in a 16-pin 0.3" wide plastic DIP.

DAC7801 has a 2-byte (8 + 4) double-buffered interface.
Data is first loaded (level transferred) into the input registers
in two steps for each DAC. Then both DACs are updated
simultaneously. DAC7801 features an asynchronous CLEAR
control. DAC7801 is packaged in a 24-pin 0.3" wide plastic
DIP.

DAC7802 has a single-buffered 12-bit data word interface.
Parallel data is loaded (edge triggered) into the single DAC
register for each DAC. DAC7802 is packaged in a 24-pin 0.3"
wide plastic DIP.

FEATURES

● TWO DACs IN A 0.3" WIDE PACKAGE

● SINGLE +5V SUPPLY

● HIGH SPEED DIGITAL INTERFACE:

Serial—DAC7800
8 + 4-Bit Parallel—DAC7801
12-Bit Parallel—DAC7802

● MONOTONIC OVER TEMPERATURE

● LOW CROSSTALK: –94dB min

● FULLY SPECIFIED OVER –40OC TO +85OC

APPLICATIONS

● PROCESS CONTROL OUTPUTS

● ATE PIN ELECTRONICS LEVEL SETTING

● PROGRAMMABLE FILTERS

● PROGRAMMABLE GAIN CIRCUITS

● AUTO-CALIBRATION CIRCUITS

Dual Monolithic CMOS 12-Bit Multiplying

DIGITAL-TO-ANALOG CONVERTERS

Serial Interface

8-Bit Interface
8 Bits + 4 Bits

Serial

DAC7801

DAC7800

12-Bit MDAC

DAC A

FB B

I

OUT B

CLR

WR

A0CSA1

UPD

UPD A

UPD B

CS

CLK

CLR

12-Bit MDAC

DAC B

R

12-Bit Interface

DAC7802

CSA

WR

12

8

CSB

12

12

AGND B

REF B

V

FB A

I

OUT A

R

AGND A

REF A

V

DAC7800
DAC7801
DAC7802

SBAS005A – DECEMBER 2001

www.ti.com

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright © 1990, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DAC7800, 7801, 7802

2

SBAS005A

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SPECIFIED

RELATIVE GAIN PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT ACCURACY ERROR PACKAGE-LEAD DESIGNATOR

(1)

RANGE MARKING NUMBER MEDIA, QUANTITY

DAC7800KP ±1LSB ±3LSB DIP-16 N –40°C to +85°C DAC7800KP DAC7800KP Rails, 25
DAC7800LP ±1/2 LSB ±1LSB DIP-16 N DAC7800LP DAC7800LP Rails, 25
DAC7800KU ——SO-16 DW –40°C to +85°C DAC7800KU DAC7800KU/1K Tape and Reel, 1000
DAC7800LU ——SO-16 DW DAC7800LU DAC7800LU/1K Tape and Reel, 1000

DAC7801KP ±1LSB ±3LSB DIP-24 NT –40°C to +85°C DAC7801KP DAC7801KP Rails, 15
DAC7801LP ±1/2 LSB ±1LSB DIP-24 NT DAC7801LP DAC7801LP Rails, 15
DAC7801KU ——SO-24 DW –40°C to +85°C DAC7801KU DAC7801KU/1K Tape and Reel, 1000
DAC7801LU ——SO-24 DW DAC7801LU DAC7801LU/1K Tape and Reel, 1000

DAC7802KP ±1LSB ±3LSB DIP-24 NTG –40°C to +85°C DAC7802KP DAC7802KP Rails, 15
DAC7802LP ±1/2 LSB ±1LSB DIP-24 NTG DAC7802LP DAC7802LP Rails, 15
DAC7802KU ——SO-24 DW –40°C to +85°C DAC7802KU DAC7802KU/1K Tape and Reel, 1000
DAC7802LU ——SO-24 DW DAC7802LU DAC7802LU/1K Tape and Reel, 1000

NOTE: (1 ) For the most current specifications and package information, refer to our web site at www.ti.com.

ELECTRICAL CHARACTERISTICS

At VDD = +5VDC, V

REF A

= V

REF B

= +10V, TA = –40°C to +85°C, unless otherwise noted.

DAC7800, 7801, 7802K DAC7800, 7801, 7802L
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY

Resolution 12 ✻ Bits
Relative Accuracy ±1 ±1/2 LSB
Differential Nonlinearity ±1 ✻ LSB
Gain Error Measured Using R

FB A

and R

FB B

. ±3 ±1LSB

All Registers Loaded with All 1s.

Gain Temperature Coefficient

(1)

25 ✻✻ppm/°C

Output Leakage Current T

A

= +25°C 0.005 10 ✻✻ nA

T

A

= –40°C to +85°C 3 150 ✻✻ nA

REFERENCE INPUT

Input Resistance 6 10 14 ✻✻✻ kΩ
Input Resistance Match 0.5 3 ✻ 2%

DIGITAL INPUTS

V

IH

(Input HIGH Voltage) 2 ✻ V

V

IL

(Input LOW Voltage) 0.8 ✻ V

I

IN

(Input Current) TA = +25°C ±1 ✻ µA

T

A

= –40°C to +85°C ±10 ✻ µA

C

IN

(Input Capacitance) 0.8 10 ✻✻ pF

POWER SUPPLY

V

DD

4.5 5.5 ✻✻V

I

DD

0.2 2 ✻✻ mA

Power-Supply Rejection V

DD

from 4.5V to 5.5V 0.002 ✻ %/%

✻ Same specification as for DAC7800, 7801, 7802K.

VDD to AGND .................................................................................. 0V, +7V

V

DD

to DGND.................................................................................. 0V, +7V

AGND to DGND .......................................................................... –0.3, V

DD

Digital Input to DGND ........................................................ –0.3, VDD + 0.3

V

REF A

, V

REF B

to AGND ..................................................................... ±16V

V

REF A

, V

REF B

to DGND ..................................................................... ±16V

I

OUT A

, I

OUT B

to AGND ................................................................. –0.3, V

DD

Storage Temperature Range ........................................... –55°C to +125°C

Operating Temperature Range ......................................... –40°C to +85°C

Lead Temperature (soldering, 10s) ................................................. +300°C

Junction Temperature...................................................................... +175 °C

ABSOLUTE MAXIMUM RATINGS

At TA = +25°C, unless otherwise noted.

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru­ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE/ORDERING INFORMATION

DAC7800, 7801, 7802

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AC PERFORMANCE

OUTPUT OP AMP IS OPA602.

At V

DD

= +5VDC, V

REF A

= V

REF B

= +10V, TA = +25°C, unless otherwise noted. These specifications are fully characterized but not subject to test.

NOTE: (1) Ensured but not tested.

DAC7800, 7801, 7802K DAC7800, 7801, 7802L

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
OUTPUT CURRENT SETTLING TIME To 0.01% of Full-Scale 0.4 0.8 ✻✻ µs

R

L

= 100Ω, CL = 13pF

DIGITAL-TO-ANALOG GLITCH IMPULSE V

REF A

= V

REF B

= 0V 0.9 ✻ nV-s

R

L

= 100Ω, CL = 13pF

AC FEEDTHROUGH f

VREF

= 10kHz –75 –72 ✻✻ dB

OUTPUT CAPACITANCE DAC Loaded with All 0s 30 50 ✻✻ pF

DAC Loaded with All 1s 70 100 ✻✻ pF

CHANNEL-TO-CHANNEL ISOLATION

V

REF A

to I

OUT B

f

VREF A

= 10kHz –90 –94 ✻✻ dB

V

REF B

= 0V,

Both DACs Loaded with 1s

V

REF B

to I

OUT A

f

VREF B

= 10kHz –90 –101 ✻✻ dB

V

REF A

= 0V,

Both DACs Loaded with 1s

DIGITAL CROSSTALK Full-Scale Transition 0.9 ✻ nV-s

R

L

= 100Ω, CL = 13pF

✻ Same specification as for DAC7800, 7801, and 7802K.

DAC7800

BLOCK DIAGRAM

DAC A

DAC B

DAC A Register

12

12

12

UPD B
I
AGND B
R
V
V
R
I
AGND A
UPD A

OUT B

FB B

REF B

REF A

FB A

OUT A

12

V

DD

9

DGND

10
15
16
14
13

4
3
2
1
6

DAC B Register

Bit 0

Bit 11
Bit 12

Bit 23

Control Logic and Shift Register

7 11

CLR

12

DAC7800

Data

In

5

CLK8CS

PIN CONFIGURATION

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

AGND A

CLK

UPD A

Data In

CS

AGND B
I
R
V
V
CLR
UPD B
DGND

OUT A

FB A

REF A

OUT B

DAC7800

I

R

V

FB B

REF B

DD

CLK UPD A UPD B CS CLR FUNCTION

XXXX0All register contents set to 0’s (asynchronous).
X X X 1 X No data transfer.

X X 0 1 Input data is clocked into input register (location Bit 23) and previous data shifts.
X0101Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A.
X1001Input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B.
X0001Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A, and input register bits 11 (LSB) - 0 (MSB)

are loaded into DAC B.

X = Don’t care.

means falling edge triggered.

LOGIC TRUTH TABLE

Top View DIP

DAC7800, 7801, 7802

4

SBAS005A

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DATA

CS

CLK

t

1

t

5

UPD A
UPD B

t

3

t

7

CLR

t

6

t

8

t

4

0V

5V

5V

5V

5V
0V

NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t = t = 5ns.
(2) Timing measurement reference level is

V + V

2

FR

IH IL

.

t

2

PARAMETER

MINIMUM

t1 — Data Setup Time 15ns
t

2

— Data Hold Time 15ns

t

3

— Chip Select to CLK, 15ns

Update, Data Setup Time

t4 — Chip Select to CLK, 40ns

Update, Data Hold Time

t

5

— CLK Pulse Width 40ns

t

6

— Clear Pulse Width 40ns

t

7

— Update Pulse Width 40ns

t

8

— CLK Edge to UPD A 15ns

or UPD B

TIMING CHARACTERISTICS

V

DD

= +5V, V

REF A

= V

REF B

= +10V, TA = –40°C to +85°C.

Data In

Bit 0 Bit 23Bit 22Bit 21Bit 20Bit 19Bit 18Bit 17Bit 16Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1

LSB

DAC A

MSB
DAC A

LSB

DAC B

MSB

DAC B

DAC7800 Data Input Sequence

DAC7800 Digital Interface Block Diagram

24-Bit

Shift Register

DAC A Register

UPD A

Data In

CLK

UPD B

LSB MSB

DAC B Register

LSB MSB

Bit
23

Bit
12

Bit
11

Bit

0

CLK

DATA INPUT FORMAT

DAC7800 (Cont.)

DAC7800, 7801, 7802

5

SBAS005A

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LOGIC TRUTH TABLE

BLOCK DIAGRAM PIN CONFIGURATION

1
2
3
4
5
6
7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

AGND A

CS
DB0
DB1
DB2
DB3
DB4
DB5

DGND

AGND B
I
R
V
V
UPD
WR
CLR
A1
A0
DB7
DB6

OUT A

FB A

REF A

FB B

REF B

DD

OUT B

DAC7801

I

R

V

DAC7801

CLR UPD CS WR A1 A0 FUNCTION

1 1 1 X X X No Data Transfer
1 1 X 1 X X No Data Transfer
0 X X X X X All Registers Cleared
1 1 0 0 0 0 DAC A LS Input Register Loaded with DB7 - DB0 (LSB)
1 1 0 0 0 1 DAC A MS Input Register Loaded with DB3 (MSB) - DB0
1 1 0 0 1 0 DAC B LS Input Register Loaded with DB7 - DB0 (LSB)
1 1 0 0 1 1 DAC B MS Input Register Loaded with DB3 (MSB) - DB0
1 0 1 0 X X DAC A, DAC B Registers Updated Simultaneously from Input Registers
1 0 0 0 X X DAC A, DAC B Registers are Transparent

X = Don’t care.

TIMING CHARACTERISTICS

V

DD

= +5V, V

REF A

= V

REF B

= +10V, TA = –40°C to +85°C.

PARAMETER MINIMUM

t

1

— Address Valid to Write Setup Time 10ns

t

2

— Address Valid to Write Hold Time 10ns

t

3

— Data Setup Time 30ns

t

4

— Data Hold Time 10ns

t

5

— Chip Select or Update to Write Setup Time 0ns

t

6

— Chip Select or Update to Write Hold Time 0ns

t

7

— Write Pulse Width 40ns

t

8

— Clear Pulse Width 40ns

A0–A1

CLR

t

2

t

1

t

8

WR

t

7

CS, UPD

t

6

t

4

t

3

DATA

t

5

5V
0V

5V
0V

5V
0V

5V
0V

5V
0V

NOTES: (1) All input signal rise and fall times are measured from 10% to 90%
of +5V. t

R

= t F = 5ns. (2) Timing measurement reference level is .

V

IH

+ V

IL

2

DAC A

I
AGND A
R
V
V
R
I
AGND B

OUT A

FB A

REF A

REF B

FB B

OUT B

20

V

DD

2
1
3

4
21
22
23
24

DAC A Register

4

8

DAC A

LS

Input

Reg

DAC A

MS

Input

Reg

Control Logic

DAC B

DAC B Register

4

8

12

DGND

DAC B

LS

Input

Reg

DAC B

MS

Input

Reg

19
16
15

5
18
17

UPD

A1
A0

CS

WR

CLR

DAC7801

14 6
DB7–DB0

12

12

Top View DIP

DAC7800, 7801, 7802

6

SBAS005A

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BLOCK DIAGRAM

1
2
3
4
5
6
7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

AGND

I

R

V

CS A

(LSB) DB0

DB1
DB2
DB3
DB4
DB5

DGND

I
R
V
V
CS B
WR
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6

OUT A

FB A

REF A

FB B

REF B

DD

OUT B

DAC7802

TIMING CHARACTERISTICS

At V

DD

= +5V, and TA = –40oC to +85oC.

PARAMETER MINIMUM

t

1

- Data Setup Time 20ns

t

2

- Data Hold Time 15ns

t

3

- Chip Select to Write Setup Time 30ns

t

4

- Chip Select to Write Hold Time 0ns

t

5

- Write Pulse Width 30ns

LOGIC TRUTH TABLE

CSA CSB WR FUNCTION

X X 1 No Data Transfer
1 1 X No Data Transfer

0 A Rising Edge on CSA or CSB Loads

Data to the Respective DAC
01 DAC A Register Loaded from Data Bus
10

DAC B Register Loaded from Data Bus
00

DAC A and DAC B Registers Loaded

from Data Bus

X = Don’t care.

means rising edge triggered.

PIN CONFIGURATION

DAC7802

DATA

5V
0V

5V

5V

CSA, CSB

WR

t

2

t

1

t

3

t

4

t

5

NOTES: (1) All input signal rise and fall times are measured from 10%
to 90% of +5V. t

R

= tR = 5ns. (2) Timing measurement reference level

is

V

IH

+ V

IL

2

.

CK

DAC B

DAC A

12

12

12

12

12

DGND

18

CS A

5

CS B 20

WR 19

21

V

DD

DAC7802

6

2 I
3 R

OUT A

FB A

23 R
24 I
1 AGND

FB B

OUT B

DAC A Register

CK

DAC B Register

DB11–DB0

422V

V

REF A

REF B

Top View DIP