TEXAS INSTRUMENTS DAC7632 Technical data

D

A

C763

2

SBAS234 – FEBRUARY 2002

16-Bit, Dual Voltage Output

DIGITAL-TO-ANALOG CONVERTER

DAC7632

FEATURES

● LOW POWER: 4mW

● UNIPOLAR OR BIPOLAR OPERATION

● SETTLING TIME: 10µs to ±0.003% FSR

● 15-BIT LINEARITY AND MONOTONICITY:

–40°C to +85°C

● PROGRAMMABLE RESET TO MID-SCALE

OR ZERO-SCALE

● DOUBLE-BUFFERED DATA INPUTS

APPLICATIONS

● PROCESS CONTROL

● CLOSED-LOOP SERVO-CONTROL

● MOTOR CONTROL

● DATA ACQUISITION SYSTEMS

● DAC-PER-PIN PROGRAMMERS

V

V

DAC7632

V

DD

CC

SS

DESCRIPTION

The DAC7632 is a 16-bit, dual channel, voltage output,
Digital-to-Analog Converter (DAC) which provides 15-bit
monotonic performance over the specified temperature range.
The device accepts 24-bit serial input data, has double­buffered DAC input logic (allowing simultaneous update of
both DACs), and provides a serial data output for daisy­chaining multiple devices. A programmable asynchronous
reset clears all registers to a mid-scale code of 8000
a zero-scale code of 0000

. The DAC7632 can operate from

H

a single +5V supply or from +5V and –5V supplies, providing
an output range of 0V to +2.5V or –2.5V to +2.5V, respec­tively.

Low power and small size per DAC make the DAC7632
ideal for industrial process control, data acquisition sys­tems, and closed-loop servo-control. The DAC7632 is avail­able in an LQFP-32 package and specified over a –40°C to
+85°C temperature range.

V

V

REF

Sense

L

V

REF

L V

REF

H

REF

Sense

H

or to

H

SDI

SDO

CS
CLK
RST

RSTSEL

LDAC
LOAD

Shift

Register

Control

Logic

Input

Register A

Input

Register B

AGND DGND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

DAC

Register A

DAC

Register B

www.ti.com

DAC A

DAC B

Copyright © 2002, Texas Instruments Incorporated

V

V

V

V

OUT

OUTA

OUT

OUTB

A

Sense

B

Sense

ABSOLUTE MAXIMUM RATINGS

V

and V

CC

V

CC

V

REFL

V

CC

V

REFH

Digital Input Voltage to GND ................................... –0.3V to V

Digital Output Voltage to GND................................. –0.3V to V

Maximum Junction Temperature................................................... +150°C

Operating Temperature Range ........................................ –40°C to +85°C

Storage Temperature Range ......................................... –65°C to +125°C

Lead Temperature (soldering, 10s) ............................................... +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

to VSS.............................................................. –0.3V to 11V

DD

and V

to GND ........................................................... –0.3V to 5.5V

DD

to VSS.............................................................–0.3V to (V

to V

H ............................................................ –0.3V to (V

REF

to V

L ......................................................... –0.3V to (V

REF

(1)

ELECTROSTATIC
DISCHARGE SENSITIVITY

– VSS)

CC
CC
CC

+ 0.3V

DD

+ 0.3V

DD

– VSS)
– VSS)

This integrated circuit can be damaged by ESD. Texas Instru­ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE/ORDERING INFORMATION

PRODUCT MONOTONICITY PACKAGE-LEAD DESIGNATOR

DAC7632VF 14 Bits LQFP-32 VF –40°C to +85°C DAC7632 DAC7632VFT Tape and Reel, 250

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

" """""DAC7632VFR Tape and Reel, 1000

DAC7632VFB

15 Bits LQFP-32

VF –40°C to +85°C DAC7632B DAC7632VFB T Tape and Reel, 250

" """""DAC7632VFB R Tape and Reel, 1000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

SPECIFIED

(1)

RANGE MARKING NUMBER MEDIA, QUANTITY

2

www.ti.com

DAC7632

SBAS234

ELECTRICAL CHARACTERISTICS (Dual Supply)

At TA = T

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY

Linearity Error ±3 ±4 ±2 ±3 LSB
Linearity Match ±4 ±2 LSB
Differential Linearity Error ±2 ±3 ±1 ±2 LSB
Monotonicity, T
Bipolar Zero Error ±1 ±3 ✻✻ mV
Bipolar Zero Error Drift 5 10 ✻✻ppm/°C
Full-Scale Error ±1 ±3 ✻✻ mV
Full-Scale Error Drift 5 10 ✻✻ppm/°C
Bipolar Zero Matching Channel-to-Channel Matching ±1 ±3 ✻✻ mV
Full-Scale Matching Channel-to-Channel Matching ±1 ±3 ✻✻ mV
Power-Supply Rejection Ratio (PSRR)

ANALOG OUTPUT

Voltage Output
Output Current –1.25 +1.25 ✻✻mA
Maximum Load Capacitance No Oscillation 500 ✻ pF
Short-Circuit Current –10, +30 ✻ mA
Short-Circuit Duration GND or V

REFERENCE INPUT

Ref High Input Voltage Range
Ref Low Input Voltage Range –2.5
Ref High Input Current 500 ✻ µA
Ref Low Input Current –500 ✻ µA

DYNAMIC PERFORMANCE

Settling Time To ±0.003%, 5V Output Step 8 10 ✻✻ µs
Channel-to-Channel Crosstalk 0.5 ✻ LSB
Digital Feedthrough 2 ✻ nV-s
Output Noise Voltage f = 10kHz 60 ✻ nV/√Hz
DAC Glitch

DIGITAL INPUT

V
V
I
I

DIGITAL OUTPUT

V
V

POWER SUPPLY

V
V
V
I
I
I
Power 7.5 11.5 ✻✻ mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

✻ Specifications same as DAC7632VF.

to T

MIN

MAX

, VDD = V

= +5V, VSS = –5V, V

CC

H = +2.5V, and V

REF

L = –2.5V, unless otherwise noted.

REF

DAC7632VF DAC7632VFB

MIN

to T

MAX

14 15 Bits

At Full Scale 10 100 ✻✻ppm/V

RL = 10kΩ

or V

CC

SS

7FFFH to 8000H or 8000H to 7FFF

IH

IL
IH
IL

OH

OL

DD

CC

SS
CC
DD
SS

IOH = –0.8mA 3.6 4.5 ✻✻ V

IOL = 1.6mA 0.3 0.4 ✻✻ V

V

LV

REF

H ✻✻V

REF

Indefinite ✻

V

H

L + 1.25

REF

0.7 • V

40 ✻ nV-s

DD

+2.5 ✻✻V

V

H – 1.25

REF

✻✻V

✻ V

0.3 • V

DD

±10 ✻ µA

✻ V

±10 ✻ µA

+4.75 +5.0 +5.25 ✻✻✻ V
+4.75 +5.0 +5.25 ✻✻✻ V
–5.25 –5.0 –4.75 ✻✻✻ V

0.7 1.1 ✻✻ mA
50 ✻ µA

–1.2 –0.8 ✻✻ mA

DAC7632

SBAS234

www.ti.com

3

SPECIFICATIONS (Dual Supply)

At TA = T

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY

Linearity Error
Linearity Match ±4 ±2LSB
Differential Linearity Error ±2 ±3 ±1 ±2LSB
Monotonicity, T
Zero Scale Error ±1 ±3 ✻✻ mV
Zero Scale Error Drift 5 10 ✻✻ppm/°C
Full-Scale Error ±1 ±3 ✻✻ mV
Full-Scale Error Drift 5 10 ✻✻ppm/°C
Zero Scale Matching Channel-to-Channel Matching ±1 ±3 ✻✻ mV
Full-Scale Matching Channel-to-Channel Matching ±1 ±3 ✻✻ mV
Power Supply Rejection Ratio (PSRR)

ANALOG OUTPUT

Voltage Output R
Output Current –1.25 +1.25 ✻✻mA
Maximum Load Capacitance No Oscillation 500 ✻ pF
Short-Circuit Current –10, +30 ✻ mA
Short-Circuit Duration GND or V

REFERENCE INPUT

Ref High Input Voltage Range
Ref Low Input Voltage Range –2.5
Ref High Input Current 250 ✻ µA
Ref Low Input Current –250 ✻ µA

DYNAMIC PERFORMANCE

Settling Time To ±0.003%, 5V Output Step 8 10 ✻✻ µs
Channel-to-Channel Crosstalk 0.5 ✻ LSB
Digital Feedthrough 2 ✻ nV-s
Output Noise Voltage, f = 10kHz 60 ✻ nV/√Hz
DAC Glitch

DIGITAL INPUT

V
V
I

IH

I

IL

DIGITAL OUTPUT

V
V

POWER SUPPLY

V
V
V
I

CC

I

DD

Power 2.5 4.5 ✻✻ mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

✻ Specifications same as DAC7632VF.

NOTE: (1) If V

to T

MIN

, VDD = V

MAX

= +5V, VSS = 0V, V

CC

H = +2.5V, and V

REF

L = 0V, unless otherwise noted.

REF

DAC7632VF DAC7632VFB

(1)

MIN

to T

MAX

14 15 Bits

±3 ±4 ±2 ±3LSB

At Full Scale 10 100 ✻✻ppm/V

= 10kΩ 0V

L

CC

V

REF

7FFFH to 8000H or 8000H to 7FFF

IH
IL

H

0.7 • V

Indefinite ✻

L + 1.25

40 ✻ nV-s

DD

H ✻✻V

REF

+2.5 ✻✻V

V

H – 1.25

REF

✻✻V

✻ V

0.3 • V

DD

±10 ✻ µA

✻ V

±10 ✻ µA

OH
OL

DD
CC
SS

IOH = –0.8mA 3.6 4.5 ✻✻ V

IOL = 1.6mA 0.3 0.4 ✻✻ V

+4.75 +5.0 +5.25 ✻✻✻ V
+4.75 +5.0 +5.25 ✻✻✻ V

000✻✻✻ V

0.5 0.9 ✻✻ mA
50 ✻ µA

= 0V, the specification applies to Code 0040H and above due to possible negative zero-scale error.

SS

4

www.ti.com

DAC7632

SBAS234

PIN CONFIGURATION

Top View SSOP

A
V

OUT

32

A Sense

L Sense

OUT

V

V

31

30

REF

L
V

REF

29

H
V

28

REF

B Sense

H Sense

REF

OUT

V

V

27

26

B
V

OUT

25

1

V

CC

NC

V

SDO

2
3
4
5
6
7

DD

8

9

10

NC

NC

AGND
AGND

DGND
DGND

NC = No Connection

PIN DESCRIPTIONS

PIN NAME DESCRIPTION

1VCCAnalog +5V Power Supply

2, 3 AGND Analog Ground

4 NC No Connection

5, 6 DGND Digital Ground

7VDDDigital +5V Power Supply
8 SDO Serial Data Output

9-16 NC No Connection

17 CLK Data Clock Input
18 SDI Serial Data Input
19 CS Chip Select, Active LOW
20 RSTSEL Reset Select. Determines the action of RST. If

21 RST Reset, Rising Edge Triggered. Depending on the

HIGH, a RST common will set the DAC registers
to mid-scale code (8000
command will set the DAC registers to zero-scale
code (0000

).

H

). If LOW, a RST

H

state of RSTSEL, the DAC registers are set to
either mid-scale code or zero-scale code.

DAC7632

11

NC

24

V

SS

23

LOAD

22

LDAC

21

RST

20

RSTSEL

19

CS

18

SDI

17

CLK

12

13

14

15

16

NC

NC

NC

NC

NC

PIN NAME DESCRIPTION

22 LDAC DAC Register Load Control, Rising Edge

Triggered
23 LOAD DAC Input Register Load Control, Active LOW
24 V
25 V
26 V

27 V

OUT

REF

28 V
29 V
30 V
31 V

REF

REF

32 V

SS

OUT

B Sense DAC B Output Amplifier Inverting Input. Used to

H Sense DAC A and B Reference High Sense Input

REF

REF

L Sense DAC A and B Reference Low Sense Input

A Sense DAC A Output Amplifier Inverting Input. Used to

OUT

Analog –5V Power Supply (or 0V for Single Supply)

B DAC B Output Voltage

close the feedback loop at the load.

H DAC A and B Reference High Input
L DAC A and B Reference Low Input

close the feedback loop at the load.

A DAC A Output Voltage

DAC7632

SBAS234

www.ti.com

5

TYPICAL CHARACTERISTICS: VSS = 0V

At TA = +25°C, VDD = VCC = +5V, VSS = 0V, V

REFH

= +2.5V, V

= 0V, representative unit, unless otherwise specified.

REFL

+25°C

DIFFERENTIAL LINEARITY ERROR vs CODE

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

0000H2000H4000H6000H8000

+85°C

DIFFERENTIAL LINEARITY ERROR vs CODE

2.0

1.5

1.0

0.5

0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5

0

–0.5
–1.0
–1.5
–2.0

0000H2000H4000H6000H8000

LINEARITY ERROR AND

(DAC A, +25°C)

A000

H

H

Digital Input Code

LINEARITY ERROR AND

(DAC A, +85°C)

A000

H

H

Digital Input Code

C000HE000HFFFF

C000HE000HFFFF

DIFFERENTIAL LINEARITY ERROR vs CODE

LINEARITY ERROR AND

(DAC B, +25°C)

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

H

0000H2000H4000H6000H8000

A000

H

C000HE000HFFFF

H

H

Digital Input Code

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B, +85°C)

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

H

0000H2000H4000H6000H8000

A000

H

C000HE000HFFFF

H

H

Digital Input Code

–40°C

DIFFERENTIAL LINEARITY ERROR vs CODE

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

0000H2000H4000H6000H8000

6

LINEARITY ERROR AND

(DAC A, –40°C)

A000

H

H

Digital Input Code

C000HE000HFFFF

H

www.ti.com

DIFFERENTIAL LINEARITY ERROR vs CODE

LINEARITY ERROR AND

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

0000H2000H4000H6000H8000

(DAC B, –40°C)

A000

H

Digital Input Code

C000HE000HFFFF

H

DAC7632

SBAS234

H

TYPICAL CHARACTERISTICS: VSS = 0V (Cont.)

1.0

0.8

0.6

0.4

0.2

0.0

Digital Input Code

0000H2000H4000H6000H8000HA000HC000HE000HFFFF

H

ANALOG SUPPLY CURRENT vs DIGITAL INPUT CODE

I

CC

(mA)

All DACs

No Load

FULL-SCALE ERROR vs TEMPERATURE

Full-Scale Error (mV)

DAC B

DAC A

3

2

1

0

–1

–2

–3

Temperature (°C)

–40 –15 8510 35 60

Code (FFFFH)

At TA = +25°C, VDD = VCC = +5V, VSS = 0V, V

REFH

= +2.5V, V

= 0V, representative unit, unless otherwise specified.

REFL

3

Code (0040H)

2

1

0

–1

Zero-Scale Error (mV)

–2

–3

–40 –15 8510 35 60

Temperature (°C)

ZERO-SCALE ERROR vs TEMPERATURE

V

H CURRENT vs CODE

REF

(all DACs sent to indicated code)

0.30

0.25

0.20

0.15

Current (mA)

0.10

REF

V

0.05

DAC B

DAC A

0.00

–0.05

–0.10

–0.15

Current (mA)

–0.20

REF

V

–0.25

V

L CURRENT vs CODE

REF

(all DACs sent to indicated code)

0.00
0000H2000H4000H6000H8000

Digital Input Code

ANALOG SUPPLY CURRENT vs TEMPERATURE

1

Data = FFFFH (all DACs)

No Load

0.8

0.6

(mA)

CC

I

0.4

0.2

0

–40 –15 10 35 60 85

Temperature (°C)

DAC7632

SBAS234

A000HC000HE000HFFFF

H

H

www.ti.com

–0.30

0000H2000H4000H6000H8000

A000HC000HE000HFFFF

H

Digital Input Code

H

7

TYPICAL CHARACTERISTICS: VSS = 0V (Cont.)

At TA = +25°C, VDD = VCC = +5V, VSS = 0V, V

REFH

= +2.5V, V

= 0V, representative unit, unless otherwise specified.

REFL

OUTPUT VOLTAGE vs SETTLING TIME

Output Voltage

vs MID-SCALE GLITCH PERFORMANCE

(0V to +2.5V)

Large-Signal Settling Time: 1V/div

Small-Signal Settling Time: 500µV/div

Time (2µs/div)

OUTPUT VOLTAGE

+5V
LDAC
0

+5V
LDAC
0

OUTPUT VOLTAGE vs SETTLING TIME

Output Voltage

vs MID-SCALE GLITCH PERFORMANCE

(+2.5V to 2mV)

Small-Signal Settling

Time: 500µV/div

Large-Signal Settling Time: 1V/div

Time (2µs/div)

OUTPUT VOLTAGE

+5V
LDAC
0

+5V
LDAC
0

Output Voltage (20mV/div)

BROADBAND NOISE

Noise Voltage (50µV/div)

Time (1µs/div)

Time (10µs/div)

7FFFH to 8000

BW = 10kHz

Code = 8000

H

Output Voltage (20mV/div)

1000

100

Noise (nV/√Hz)

H

10

OUTPUT NOISE VOLTAGE vs FREQUENCY

10

100

8000H to 7FFF

Time (1µs/div)

1000 10000

Frequency (Hz)

H

100000

1000000

8

www.ti.com

DAC7632

SBAS234

TYPICAL CHARACTERISTICS: VSS = 0V (Cont.)

5

4

3

2

1

0

R

LOAD

(kΩ)

0.01

0.1

1 10 100

V

OUT

vs R

LOAD

V

OUT

(V)

Source

Sink

At TA = +25°C, VDD = VCC = +5V, VSS = 0V, V

REFH

= +2.5V, V

= 0V, representative unit, unless otherwise specified.

REFL

vs LOGIC INPUT LEVEL FOR DIGITAL INPUTS

LOGIC SUPPLY CURRENT

0.50

Typical of One

Digital Input

0.40

0.30

0.20

0.10

Logic Supply Current (mA)

0.00

0

1

23

Logic Input Level for Digital Inputs (V)

VSS = –5V

At TA = +25°C, VDD = VCC = +5V, VSS = –5V, V

+25°C

DIFFERENTIAL LINEARITY ERROR vs CODE

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

0000H2000H4000H6000H8000

LINEARITY ERROR AND

(DAC A, +25°C)

H

Digital Input Code

= +2.5V, V

REFH

A000

C000HE000HFFFF

H

4

5

= –2.5V, representative unit, unless otherwise specified.

REFL

DIFFERENTIAL LINEARITY ERROR vs CODE

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

H

0000H2000H4000H6000H8000

LINEARITY ERROR AND

(DAC B, +25°C)

A000

H

H

Digital Input Code

C000HE000HFFFF

H

+85°C

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

0000H2000H4000H6000H8000

DAC7632

SBAS234

DIFFERENTIAL LINEARITY ERROR vs CODE

LINEARITY ERROR AND

(DAC A, +85°C)

A000

H

Digital Input Code

C000HE000HFFFF

H

H

www.ti.com

DIFFERENTIAL LINEARITY ERROR vs CODE

LINEARITY ERROR AND

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

0000H2000H4000H6000H8000

(DAC B, +85°C)

A000

H

Digital Input Code

C000HE000HFFFF

H

H

9

TYPICAL CHARACTERISTICS: VSS = –5V (Cont.)

At TA = +25°C, VDD = VCC = +5V, VSS = –5V, V

REFH

= +2.5V, V

= –2.5V, representative unit, unless otherwise specified.

REFL

–40°C

DIFFERENTIAL LINEARITY ERROR vs CODE

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

0000H2000H4000H6000H8000

+0.6

+0.5

+0.4

LINEARITY ERROR AND

(DAC A, –40°C)

A000

H

C000HE000HFFFF

H

Digital Input Code

V

H CURRENT vs CODE

REF

(all DACs sent to indicated code)

DIFFERENTIAL LINEARITY ERROR vs CODE

LINEARITY ERROR AND

(DAC B, –40°C)

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

H

0000H2000H4000H6000H8000

A000

H

C000HE000HFFFF

H

H

Digital Input Code

V

L CURRENT vs CODE

REF

(all DACs sent to indicated code)

0.0

–0.1

–0.2

+0.3

Current (mA)

+0.2

REF

V

+0.1

0.0
0000H2000H4000H6000H8000

H

Digital Input Code

BIPOLAR ZERO ERROR vs TEMPERATURE

3

Code (8000H)

2

1

0

–1

Bipolar Zero Error (mV)

–2

–3

–40 –15 8510 35 60

Temperature (°C)

A000HC000HE000HFFFF

DAC B

DAC A

–0.3

Current (mA)

–0.4

REF

V

–0.5

–0.6

H

0000H2000H4000H6000H8000

A000HC000HE000HFFFF

H

H

Digital Input Code

POSITIVE FULL-SCALE ERROR vs TEMPERATURE

3

Code (FFFFH)

2

1

DAC B

0

–1

–2

Positive Full-Scale Error (mV)

DAC A

–3

–40 –15 8510 35 60

Temperature (°C)

10

www.ti.com

DAC7632

SBAS234

TYPICAL CHARACTERISTICS: VSS = –5V (Cont.)

Time (2µs/div)

OUTPUT VOLTAGE vs SETTLING TIME

(+2.5V to –2.5V)

Output Voltage

+5V
LDAC
0

Large-Signal Settling Time: 2V/div

Small-Signal Settling Time:

500µV/div

1.00

0.75

0.50

0.25

0.00

–0.25
–0.50
–0.75
–1.00

ANALOG SUPPLY CURRENT vs DIGITAL INPUT CODE

Analog Supply Current (mA)

0000H2000H4000

H

I

CC

I

SS

6000H8000

H

Digital Input Code

A000HC000HE000HFFFF

H

No Load

At TA = +25°C, VDD = VCC = +5V, VSS = –5V, V

NEGATIVE FULL-SCALE ERROR vs TEMPERATURE

3

Code (0000H)

2

REFH

= +2.5V, V

= –2.5V, representative unit, unless otherwise specified.

REFL

1

0

–1

–2

Negative Full-Scale Error (mV)

–3

–40 –15 8510 35 60

Temperature (°C)

vs R

V

OUT

5

LOAD

4
3

Source
2
1

(V)

0

OUT

V

–1
–2
–3
–4
–5

0.01

0.1

1 10 100

R

(kΩ)

LOAD

Sink

DAC B

DAC A

ANALOG SUPPLY CURRENT vs TEMPERATURE

1

I

CC

0.5

0

–0.5

I

SS

–1

Analog Supply Current (mA)

Data = FFFFH (all DACs)

–1.5

No Load

–40 –15 10 35 60 85

Temperature (°C)

DAC7632

SBAS234

OUTPUT VOLTAGE vs SETTLING TIME

(–2.5V to +2.5V)

Large-Signal Settling Time: 2V/div

Small-Signal Settling Time: 500µV/div

Output Voltage

Time (2µs/div)

+5V
LDAC
0

www.ti.com

11

TYPICAL CHARACTERISTICS: VSS = –5V (Cont.)

At TA = +25°C, VDD = VCC = +5V, VSS = –5V, V

REFH

= +2.5V, V

= –2.5V, representative unit, unless otherwise specified.

REFL

vs MID-SCALE GLITCH PERFORMANCE

Output Voltage (50mV/div)

OUTPUT VOLTAGE

Time (1µs/div)

7FFFH to 8000

H

+5V
LDAC
0

THEORY OF OPERATION

The DAC7632 is a dual channel, voltage output, 16-bit DAC.
The architecture is an R-2R ladder configuration with the
three MSB’s segmented, followed by an operational amplifier
that serves as a buffer. Each DAC has its own R-2R ladder
network, segmented MSBs, and output op amp, as shown in
Figure 1. The minimum voltage output (zero-scale) and
maximum voltage output (full-scale) are set by the external
voltage references V

L and V

REF

H, respectively.

REF

vs MID-SCALE GLITCH PERFORMANCE

Output Voltage (50mV/div)

OUTPUT VOLTAGE

Time (1µs/div)

8000H to 7FFF

H

+5V
LDAC
0

The digital input is a 24-bit serial word that contains an
address bit for selecting one of two DACs, a quick load bit,
six unused bits, and the 16-bit DAC code (MSB first). The
converters can be powered from either a single +5V supply
or a dual ±5V supply. The device offers a reset function
which immediately sets all DAC output voltages, DAC regis­ters and input registers to mid-scale (code 8000
scale (code 0000

), depending on the state of RSTSEL. See

H

) or to zero-

H

Figures 2 and 3 for the basic configurations of the DAC7632.

R

2R2R 2R 2R 2R 2R 2R 2R

FIGURE 1. DAC7632 Architecture.

2R

V

V

V

V

REF

REF

REF

REF

R

F

H

H Sense

L

L Sense

V

Sense

OUT

V

OUT

12

www.ti.com

DAC7632

SBAS234

0V to +2.5V

+2.5V

0V to +2.5V

V

REFL

Sense

29 28

V

REFH

V

REFL

DAC7632

+5V

1µF

1µF

+5V

NC = No Connection

0.1µF

0.1µF

1
2
3
4
5
6
7
8

32

31 30

V

OUTA

V

OUTA

Sense

V

CC

AGND
AGND
NC
DGND
DGND
V

DD

SDO

NC

NC NC NC NC NC NC NC

9 10 11 12 13 14 15 16

FIGURE 2. Basic Single-Supply Operation of the DAC7632.

27 26 25

V

OUTB

Sense

V

REFH

Sense

V

OUTB

V
LOAD
LDAC

RST

RSTSEL

CS

SDI

CLK

24

SS

23

LOAD INPUT REGISTER(S)

22

LOAD DAC REGISTERS

21

RESET INPUT AND DAC REGISTERS

20
19

CHIP SELECT

18

SERIAL DATA IN

17

CLOCK

+5V

1µF

1µF

+5V

NC = No Connection.

0.1µF

0.1µF

1
2
3
4
5
6
7
8

–2.5V to

REFL

V

REFL

+2.5V

V

REFH

28

V
Sense

V

+2.5V

CC

V

OUTA

32

V

Sense

OUTA

–2.5V

31 30 29

V

Sense

AGND
AGND
NC

DAC7632

DGND
DGND
V

DD

SDO

NC

NC NC NC NC NC NC NC

9 10 11 12 13 14 15 16

–2.5V to

27 26 25

V

OUTB

Sense

REFH

+2.5V

V

OUTB

V

LOAD

LDAC

RST

RSTSEL

SDI

CLK

CS

24

SS

23

LOAD INPUT REGISTER(S)

22

LOAD DAC REGISTERS

21

RESET INPUT AND DAC REGISTERS

20

+5V

19

CHIP SELECT

18

SERIAL DATA IN

17

CLOCK

–5V

0.1µF1µF

FIGURE 3. Basic Dual-Supply Operation of the DAC7632.

DAC7632

SBAS234

www.ti.com

13

ANALOG OUTPUTS

When VSS = –5V (dual-supply operation), the output amplifier
can swing to within 2.25V of the supply rails over the –40°C
to +85°C temperature range. When V
operation), and with R

also connected to ground, the

LOAD

= 0V (single-supply

SS

output can swing to ground. Care must also be taken when
measuring the zero-scale error when V

= 0V. Since the

SS

output cannot swing below ground, the output voltage may
not change for the first few digital input codes (0000
0002

, etc.) if the output amplifier has a negative offset. At

H

, 0001H,

H

the negative limit of –2mV, the first specified output starts at
code 0040

.

H

Due to the high accuracy of these DACs, system design
problems such as grounding and contact resistance become
very important. A 16-bit converter with a 2.5V full-scale range
has a 1LSB value of 38µV. With a load current of 1mA, series
wiring and connector resistance of only 40mΩ (R

W2

) will
cause a voltage drop of 40µV, as shown in Figure 4. To
understand what this means in terms of a system layout, the
resistivity of a typical 1 ounce copper-clad printed circuit
board is 1/2mΩ per square. For a 1mA load, a 10 milli-inch
wide printed circuit conductor 600 milli-inches long will result
in a voltage drop of 30µV.

The DAC7632 offers a force and sense output configuration
for the high open-loop gain output amplifier. This feature
allows the loop around the output amplifier to be closed at the
load, as shown in Figure 4, thus ensuring an accurate output
voltage.

REFERENCE INPUTS

The reference inputs, V
between V

+ 2.5V and V

SS

at least 1.25V greater than V
each DAC is equal to V
(essentially, the offset of the output op amp). The maximum
output is equal to V

L and V

REF

– 2.5V, provided that V

CC

REF

REFL

H plus a similar offset voltage. Note

REF

H, can be any voltage

REF

L. The minimum output of

plus a small offset voltage

REF

H is

R

W2

32

V

A

DAC7632

V

V

V

V

OUT

REF

REF

OUT

OUT

A Sense

L Sense

V

REF

V

REF

H Sense
B Sense

V

OUT

31
30
29

L

28

H

27
26
25

B

R

W1

R

W1

R

W2

V

OUT

+V

+2.5V

V

OUT

FIGURE 4. Analog Output Closed-Loop Configuration

R

represents wiring resistances.

W

that V

(the negative power supply) must either be

SS

connected to ground or must be in the range of –4.75V to
–5.25V. The voltage on V
the converter. If V

is not in one of these two configurations,

SS

sets several bias points within

SS

the bias values may be in error and proper operation of the
device may be affected.

The current into the V

H input and out of V

REF

L depends

REF

on the DAC output voltages, and can vary from a few
microamps to approximately 0.5mA. The reference input
appears as a varying load to the reference supply. If the
reference applied can sink or source the required current, a
reference buffer is not required. The DAC7632 features
reference drive and sense connections such that the internal
errors caused by the changing reference current and the
circuit impedances can be minimized. Figures 5 through 13
show different reference configurations and the effect on the
integral linearity and differential linearity, for each case.

+V

OPA2234

–V

DAC7632

V

V

V
V

OUT

REF

REF

OUT

V

OUT

A Sense

L Sense

V

REF

V

REF

H Sense
B Sense

V

OUT

32

A

31
30
29

L

28

H

27
26
25

B

V

OUT

1000pF

1000pF

V

OUT

100Ω

2200pF

100Ω

2200pF

FIGURE 5. Dual Supply Configuration-Buffered References, used for Dual-Supply Performance.

14

www.ti.com

–2.5V

–V

+V

+2.5V

DAC7632

SBAS234

+V

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

LE (LSB)DLE (LSB)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A, +25°C)

0000H2000H4000H6000H8000

H

Digital Input Code

A000

H

C000HE000HFFFF

H

V

OUT

1000pF

1000pF

V

OUT

100Ω

2200pF

100Ω

2200pF

DAC7632

V

OUT

V

V

REF

V

OUT

A Sense

REF

H Sense

B Sense

V

OUT

L Sense

V

REF

V

REF

V

OUT

32

A

31
30
29

L

28

H

27
26
25

B

FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV.

DIFFERENTIAL LINEARITY ERROR vs CODE

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

0000H2000H4000H6000H8000

LINEARITY ERROR AND

(DAC A, +25°C)

A000

H

H

Digital Input Code

C000HE000HFFFF

H

OPA2350

2kΩ

+0.050V
98kΩ

+V

+2.5V

FIGURE 7. Integral Linearity and Differential Linearity Error

FIGURE 9. Single-Supply Buffered Reference with V

DAC7632

SBAS234

Characteristic Curves for Figure 6.

V

A Sense

OUT

V

L Sense

REF

DAC7632

V
V

REF

OUT

H Sense
B Sense

FIGURE 8. Integral Linearity and Differential Linearity Error

Characteristic Curves for Figure 9.

+V

+V

OUT

32

A

V

31
30
29

V

L

REF

REF

28

H

V

27
26

OUT

25

B

V

V

OUT

100Ω

1000pF

1000pF

V

OUT

L = +1.25V and V

REF

www.ti.com

2200pF

100Ω

2200pF

REF

OPA2350

+1.25V

+V

+2.5V

H = +2.5V.

15

DAC7632

LOAD

V

V

V
V

OUT

REF

REF

OUT

V

OUT

A Sense

L Sense

V

REF

V

REF

H Sense
B Sense

V

OUT

1000pF

V

OUT

+V

OPA2350

100Ω

2200pF

V

OUT

+V

+2.5V

32

A

31
30
29

L

28

H

27
26
25

B

FIGURE 10. Single-Supply Buffered V

DIFFERENTIAL LINEARITY ERROR vs CODE

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

0000H2000H4000H6000H8000

LINEARITY ERROR AND

(DAC A, +25°C)

H

Digital Input Code

H.

REF

A000

C000HE000HFFFF

H

H

FIGURE 11. Linearity and Differential Linearity Error Charac-

teristic Curves for Figure 10.

V

OUT

+V

+2.5V

V

OUT

DAC7632

V

V

V
V

OUT

REF

REF

OUT

V

OUT

A Sense

L Sense

V

REF

V

REF

H Sense
B Sense

V

OUT

32

A

31
30
29

L

28

H

27
26
25

B

FIGURE 12. Low-Cost Single-Supply Configuration.

DIFFERENTIAL LINEARITY ERROR vs CODE

2.0

1.5

1.0

0.5
0

–0.5

LE (LSB)DLE (LSB)

–1.0
–1.5
–2.0

2.0

1.5

1.0

0.5
0

–0.5
–1.0
–1.5
–2.0

0000H2000H4000H6000H8000

LINEARITY ERROR AND

(DAC A, +25°C)

A000

H

H

Digital Input Code

C000HE000HFFFF

H

FIGURE 13. Linearity and Differential Linearity Error Charac-

teristic Curves for Figure 12.

DIGITAL INTERFACE

See Table I for the basic control logic for the DAC7632. The
interface consists of a Serial Data Clock (CLK) input, Serial
Data Input (SDI), Input Register Load Control Signal (
and DAC Register Load Control Signal (LDAC). In addition, a
Chip Select (

CS

) input is available to enable serial communi­cation when there are multiple serial devices attached to a
single serial bus. An asynchronous Reset (RST) input (rising
edge triggered) is provided to simplify start-up conditions,
periodic resets, or emergency resets to a known state, de­pending on the status of the Reset Select (RSTSEL) signal.

The DAC code, quick load control, and address are provided
via a 24-bit serial interface (see Figure 15). The first bit
(DACSEL) selects the input register that will be updated
when

goes LOW. The third bit is a “Quick Load” bit
such that if HIGH, the code in the shift register is loaded into
both input registers when the
“Quick Load” bit is LOW when an active

LOAD

signal goes LOW. If the

LOAD
issued, the content of the shift register is loaded only to the
input register that is addressed by DACSEL. The “Quick
Load” bit is followed by five unused bits. The last 16 bits
(MSB first) make up the DAC code.

LOAD

signal is

),

16

www.ti.com

DAC7632

SBAS234

SERIAL DATA INPUT

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

DACSEL X X X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

QUICK

LOAD

DACSEL CS RST RSTSEL

0 L H X X L Write Hold Write Input A

1 L H X X L Write Hold Write Input B
XHHX↑ H Hold Write Update All
X H H X H H Hold Hold Hold All
XX↑ L X X Reset to 0000
XX↑ H X X Reset to 8000

LDAC

LOAD REGISTER REGISTER MODE DAC

INPUT DAC

Reset to 0000HReset to Zero-Scale All

H

Reset to 8000

H

Reset to Mid-scale All

H

TABLE I. DAC7632 Logic Truth Table.

Data presented to SDI is clocked into the shift register on
each rising CLK edge. This data is latched into the input
register(s) via a logic-low level on

LOAD

. The data is directed
from the shift register to the desired input register(s) specified
by data bits 21 and 23. The internal DAC registers are edge
triggered and not level triggered. When the LDAC signal is
transitioned from LOW to HIGH, the digital word currently in
the input registers are latched. This double-buffered architec­ture has been designed so that new data can be entered for
each DAC without disturbing the analog outputs. When the
new data has been entered into the device, both DAC
outputs can be updated simultaneously by the rising edge of
LDAC. Additionally, it allows the input registers to be written
to at any point, then the DAC output voltages can be
synchronously changed via a trigger signal (LDAC).

Note that

CS

and CLK are combined with an OR gate, which
controls the serial-to-parallel shift register. These two inputs
are completely interchangeable. In addition, care must be
taken with the state of CLK when
serial transfer. If CLK is LOW when

CS

rises at the end of a

CS

rises, the OR gate
will provide a rising edge to the shift register, shifting the
internal data one additional bit. The result will be incorrect
data and possible selection of the wrong input register(s). If
both

CS

and CLK are used, CS should rise only when CLK

is HIGH. If not, then either

CS

or CLK can be used to operate

(1)

CS

(2)

H

(4)

L

L ↑
↑ L H H Advanced One Bit

(6)

H

(6)

H

NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH.
(3) X = Don’t Care. (4) L = Logic LOW. (5) = Positive Logic Transition.
(6) A HIGH value is suggested in order to avoid a “false clock” from
advancing the shift register and changing the shift register. (7) If data is
clocked into the serial register while LOAD is LOW, the input registers will
change as data flows through the shift register. This will corrupt the data
in each DAC register that has been erroneously selected. (8) Rising edge
of RST causes no change in the contents of the serial shift register.

TABLE II. Serial Shift Register Truth Table.

SERIAL-DATA OUTPUT

The Serial-Data Output pin (SDO) is the internal shift register’s
output. For the DAC7632, SDO is a driven output and does
not require an external pull-up. Any number of DAC7632s
can be daisy-chained by connecting the SDO pin of one
device to the SDI pin of the following device in the chain, as
shown in Figure 14.

(1)

CLK

X

LOAD

(3)

L H H No Change

(5)

XL
XH↑

H H No Change

H H Advanced One Bit

(7)

RST SERIAL SHIFT REGISTER

H No Change

(8)

No Change

the shift register (the remaining pin should be tied to DGND).
Please refer to Table II for more information.

DAC7632

SCK

DIN

CS

CLK
SDI
CS

SDO

FIGURE 14. Daisy-Chaining Multiple DAC7632s.

DAC7632

SBAS234

DAC7632

CLK

SDO

SDI
CS

www.ti.com

DAC7632

CLK
SDI
CS

SDO

To
Other
Serial
Devices

17

DIGITAL TIMING

Figure 15 and Table III provide detailed timing for the digital
interface of the DAC7632.

DIGITAL INPUT CODING

The DAC7632 input data is in Straight Binary format. The
output voltage is given by Equation 1.

–•

VHVLN

(

VVL

=+

OUT

REF

REF REF

where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.

)

,65 536

DIGITALLY-PROGRAMMABLE CURRENT SOURCE

The DAC7632 offers a unique set of features that allows a
wide range of flexibility in designing application circuits such
as programmable current sources. The DAC7632 offers both
a differential reference input, as well as an open-loop con­figuration around the output amplifier. The open-loop con­figuration around the output amplifier allows a transistor to be
placed within the loop to implement a digitally-program­mable, unidirectional current source. The availability of a
differential reference allows programmability for both the full­scale and zero-scale currents. The output current is calcu­lated as:

I

OUT





=









–

VHVL

REF REF

R

SENSE

VLR

+

(

REF

/






SENSE



•





)

65 536



N








,



SDI

CLK

CS

LOAD

LDAC

SDI

CLK

SDO

LDAC

V

OUT

RST

RSTSEL

t

SDO

(MSB)

DACSEL

t

LDDL

QUICK

X D15 D1 D0

LOAD

t

css

t

LD1

t

DS

t

CL

t

LDDH

t

S

X

t

DH

t

CH

X

XXX

±0.003% FSR
ERROR BAND

t

RSSS

t

RSTL

t

RSTH

t

RSSH

t

CSH

t

LD2

t

LDRW

t

S

(LSB)

t

LDDD

±0.003% FSR
ERROR BAND

FIGURE 15. Digital Input and Output Timing.

18

www.ti.com

DAC7632

SBAS234

SYMBOL DESCRIPTION MIN MAX UNITS

t
t
t

t

t

t
t

t

LDRW

t

LDDL

t

LDDH

t

LDDD

t

RSSS

t

RSSH

t

RSTL

t

RSTH

t

SDO

DS
DH
CH

t

CL
CSS
CSH

LD1
LD2

t

S

Data Valid to CLK Rising 10 ns

Data Held Valid after CLK Rises 20 ns

CLK HIGH 25 ns
CLK LOW 25 ns

CS LOW to CLK Rising 15 ns

CLK HIGH to CS Rising 0 ns

LOAD HIGH to CLK Rising 10 ns

CLK Rising to LOAD LOW 30 ns

LOAD LOW Time 30 ns
LDAC LOW Time 100 ns

LDAC HIGH Time 100 ns

LOAD LOW to LDAC Rising 40 ns

RESETSEL Valid to RESET HIGH 0 ns

RESET HIGH to RESETSEL Not Valid 100 ns

RESET LOW Time 10 ns

RESET HIGH Time 10 ns

SDO Propogation Delay 10 30 ns

Settling Time 10 µs

TABLE III. Timing Specifications (TA = –40°C to +85°C).

Figure 16 shows a DAC7632 in a 4-20mA current output
configuration. The output current can be determined by
Equation 3:

I

OUT



VV N V

25 05

. – .



=







125 65 536



ΩΩ





•









V

OUT

V

DAC7632

V

REF

V

OUT

,

A Sense
L Sense

REF

H Sense

B Sense



05






V

OUT

V

REF

V

REF

V

OUT

.






125

32
31
30
29
28
27
26
25






1000pF

1000pF

+





A

L

H

B

At full-scale, the output current is 16mA, plus the 4mA, for the
zero current. At zero scale the output current is the offset
current of 4mA (0.5V/125Ω).

I

OUT

V

PROGRAMMED

125Ω

2200pF

100Ω

100Ω

2200pF

I

OUT

+V

OPA2350

20kΩ

80kΩ

+V

+2.5V

FIGURE 16. 4-20mA Digitally-Controlled Current Source.

DAC7632

SBAS234

V
125Ω

www.ti.com

PROGRAMMED

19

PACKAGE DRAWING

MTQF002B – JANUARY 1995 – REVISED MAY 2000

VF (S-PQFP-G32) PLASTIC QUAD FLATPACK

25

32

1,45
1,35

0,80

24

0,45
0,25

17

1

5,60 TYP
7,20

SQ

6,80
9,20

SQ

8,80

8

16

9

0,20

M

0,05 MIN

Seating Plane

0,13 NOM

Gage Plane

0,25

0°–7°

0,75
0,45

1,60 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

0,10

4040172/D 04/00

20

www.ti.com

DAC7632

SBAS234

PACKAGE OPTION ADDENDUM

www.ti.com

3-Oct-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

DAC7632VFBR ACTIVE LQFP VF 32 1000 TBD CU NIPDAU Level-3-235C-168 HR
DAC7632VFBT ACTIVE LQFP VF 32 250 TBD CU NIPDAU Level-3-235C-168 HR

DAC7632VFR ACTIVE LQFP VF 32 1000 TBD CU NIPDAU Level-3-235C-168 HR
DAC7632VFT ACTIVE LQFP VF 32 250 TBD CU NIPDAU Level-3-235C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Copyright  2005, Texas Instruments Incorporated