TEXAS INSTRUMENTS DAC7624 Technical data

®
DAC7624
DAC7625
12-Bit Quad Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
LOW POWER: 20mW
UNIPOLAR OR BIPOLAR OPERATION
SETTLING TIME: 10µs to 0.012%
12-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
RESET TO MID-SCALE (DAC7624) OR
ZERO-SCALE (DAC7625)
DATA READBACK
DOUBLE-BUFFERED DATA INPUTS
APPLICATIONS
PROCESS CONTROL
ATE PIN ELECTRONICS
CLOSED-LOOP SERVO-CONTROL
MOTOR CONTROL
DATA ACQUISITION SYSTEMS
DAC-PER-PIN PROGRAMMERS
GND
DESCRIPTION
The DAC7624 and DAC7625 are 12-bit quad voltage output digital-to-analog converters with guaranteed 12­bit monotonic performance over the specified tempera­ture range. They accept 12-bit parallel input data, have double-buffered DAC input logic (allowing simulta­neous update of all DACs), and provide a readback mode of the internal input registers. An asynchronous reset clears all registers to a mid-scale code of 800 (DAC7624) or to a zero-scale of 000H (DAC7625). The DAC7624 and DAC7625 can operate from a single +5V supply or from +5V and –5V supplies.
Low power and small size per DAC make the DAC7624 and DAC7625 ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closed-loop servo-control. The DAC7624 and DAC7625 are available in a 28-pin plastic double­wide or a 28-lead SOIC package, and offer guaranteed specifications over the –40°C to +85°C temperature range.
V
V
REFH
DD
H
SBAS083
12
DB0-DB11
A0 A1
R/W
CS
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1997 Burr-Brown Corporation PDS-1419C Printed in U.S.A. April, 2000
I/O
Buffer
Control
Logic
Input
Register A
Input
Register B
Input
Register C
Input
Register D
1
DAC
Register A
DAC
Register B
DAC
Register C
DAC
Register D
V
REFLRESET LDAC
DAC A
DAC B
DAC C
DAC D
V
V
V
V
V
SS
DAC7624/7625
OUTA
OUTB
OUTC
OUTD
®
SPECIFICATION
At TA = –40°C to +85°C, VDD = +5V, VSS = –5V, V
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ACCURACY
Linearity Error Linearity Matching
(1)
(3)
Differential Linearity Error VSS = 0V or –5V ±1 ±1 LSB Monotonicity T Zero-Scale Error Code = 000 Zero-Scale Drift 25 ✻✻ppm/°C Zero-Scale Matching Full-Scale Error Code = FFF Full-Scale Matching
(3)
(3)
Zero-Scale Error Code = 00A Zero-Scale Drift VSS = 0V 5 10 ✻✻ppm/°C Zero-Scale Matching
(3)
Full-Scale Error Code = FFF Full-Scale Matching
(3)
Power Supply Rejection 30 ppm/V
ANALOG OUTPUT
Voltage Output
(4)
Output Current –1.25 +1.25 ✻✻mA Load Capacitance No Oscillation 100 pF Short-Circuit Current +5, –120 mA Short-Circuit Duration
REFERENCE INPUT
V
Input Range VSS = 0V or –5V
REFH
V
Input Range VSS = 0V 0
REFL
V
Input Range VSS = –5V –2.5
REFL
DYNAMIC PERFORMANCE
Settling Time
(5)
Channel-to-Channel Crosstalk
Output Noise Voltage 0Hz to 1MHz 40 nV/Hz
DIGITAL INPUT/OUTPUT
Logic Family TTL-Compatible CMOS Logic Levels
V
IH
V
IL
V
OH
V
OL
Data Format Straight Binary
POWER SUPPLY REQUIREMENTS
V
DD
V
SS
I
DD
I
SS
Power Dissipation VSS = –5V 15 20 ✻✻ mW
TEMPERATURE RANGE
Specified Performance DAC7624P, U, PB, UB –40 +85 ✻✻°C
NOTES: (1) If VSS = 0V, specification applies at code 00AH and above. (2) LSB means Least Significant Bit, when V then one LSB equals 1.22mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error. (5) If V
= –5V, full-scale 5V step. If VSS = 0V, full-scale positive 2.5V step and negative step from code FFFH to 00AH.
SS
REFH
= +2.5V, V
= –2.5V, unless otherwise noted.
REFL
DAC7624P, U DAC7624PB, UB DAC7625P, U DAC7625PB, UB
VSS = 0V or –5V ±2 ±1 LSB VSS = 0V or –5V ±2 ±1 LSB
MIN
to T
MAX
H
12 Bits
±4 LSB
±2 ±1 LSB
H
±4 LS ±2 ±1 LSB
, VSS = 0V ±8 LSB
H
VSS = 0V ±4 ±2 LSB
, VSS = 0V ±8 LSB
H
VSS = 0V ±4 ±2 LSB
V
= 0V, VSS = 0V 0 V
REFL
V
= –5V V
SS
REFL
Momentary
V
+1.25
REFL
REFH
V
REFH
+2.5 ✻✻V
V
–1.25
REFH
V
–1.25
REFH
✻✻V ✻✻V
✻✻V ✻✻V
To ±0.012% 5 10 ✻✻ µs
Full-Scale Step
0.25 LSB
On any other DAC
IIH ±10µA 2.4 VDD +0.3 ✻✻V IIL ±10µA –0.3 0.8 ✻✻V
IOH = –0.8mA 3.6 V
DD
✻✻V
IOL = 1.6mA 0.0 0.4 ✻✻V
4.75 5.25 ✻✻V
If VSS 0V –5.25 –4.75 ✻✻V
1.5 1.9 ✻✻ mA
–2.1 –1.6 ✻✻ mA
= 0V 7.5 10 ✻✻ mW
V
SS
DAC7625P, U, PB, UB
equals +2.5V and V
REFH
REFL
(2)
equals –2.5V,
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
DAC7624/7625
2
ABSOLUTE MAXIMUM RATINGS
V
to VSS............................................................................. –0.3V to 11V
DD
to GND .......................................................................... –0.3V to 5.5V
V
DD
to VSS..............................................................–0.3V to (V
V
REFL
to V
V
DD
V
REFH
Digital Input Voltage to GND ................................... –0.3V to V
Digital Output Voltage to GND ................................. –0.3V to V
Maximum Junction Temperature................................................... +150°C
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
............................................................. –0.3V to (V
REFH
to V
..........................................................–0.3V to (V
REFL
(1)
ELECTROSTATIC DISCHARGE SENSITIVITY
– VSS)
DD DD DD
+ 0.3V
DD
+ 0.3V
DD
– VSS) – VSS)
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
MAXIMUM DIFFERENTIAL SPECIFICATION PACKAGE
LINEARITY LINEARITY TEMPERATURE DRAWING
PRODUCT ERROR (LSB) ERROR (LSB) RANGE PACKAGE NUMBER
DAC7624P ±2 ±1 –40°C to +85°C 28-Pin Plastic DIP 215 DAC7624U ±2 ±1 –40°C to +85°C 28-Lead SOIC 217 DAC7624PB ±1 ±1 –40°C to +85°C 28-Pin Plastic DIP 215 DAC7624UB ±1 ±1 –40°C to +85°C 28-Lead SOIC 217
DAC7625P ±2 ±1 –40°C to +85°C 28-Pin Plastic DIP 215 DAC7625U ±2 ±1 –40°C to +85°C 28-Lead SOIC 217 DAC7625PB ±1 ±1 –40°C to +85°C 28-Pin Plastic DIP 215 DAC7625UB ±1 ±1 –40°C to +85°C 28-Lead SOIC 217
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
MAXIMUM
(1)
®
3
DAC7624/7625
PIN CONFIGURATIONS
Top View
DIP SOIC
V
REFH
V
OUTB
V
OUTA
V
GND
RESET
LDAC
(LSB) DB0
DB1 DB2 DB3 DB4 DB5 DB6
1 2 3 4
SS
5 6 7
DAC7624 DAC7625
8
9 10 11 12 13 14
V
28
V
27
V
26
V
25
NIC
24
CS
23
A0
22
A1
21
R/W
20
DB11 (MSB)
19
DB10
18
DB9
17
DB8
16
DB7
15
REFL
OUTC
OUTD
DD
V
REFH
V
OUTB
V
OUTA
GND
RESET
LDAC
(LSB) DB0
DB1 DB2 DB3 DB4 DB5 DB6
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1V 2V 3V 4V
REFH OUTB OUTA
SS
5 GND Ground. 6 RESET Asynchronous Reset Input. Sets DAC and input registers to either mid-scale (800
7 LDAC Load DAC Input. All DAC Registers are transparent when LOW. 8 DB0 Data Bit 0. Least significant bit of 12-bit word.
9 DB1 Data Bit 1 10 DB2 Data Bit 2 11 DB3 Data Bit 3 12 DB4 Data Bit 4 13 DB5 Data Bit 5 14 DB6 Data Bit 6 15 DB7 Data Bit 7 16 DB8 Data Bit 8 17 DB9 Data Bit 9 18 DB10 Data Bit 10 19 DB11 Data Bit 11. Most significant bit of 12-bit word. 20 R/W Read/Write Control Input (read = HIGH, write = LOW). 21 A1 Register/DAC Select (C or D = HIGH, A or B = LOW). 22 A0 Register/DAC Select (B or D = HIGH, A or C = LOW). 23 CS Chip Select Input. 24 NIC Not Internally Connected. Pin has no internal connection to the device. 25 V 26 V 27 V 28 V
DD OUTD OUTC REFL
Reference Input Voltage High. Sets maximum output voltage for all DACs. DAC B Voltage Output. DAC A Voltage Output. Negative Analog Supply Voltage, 0V or –5V.
when LOW.
Positive Analog Supply Voltage, +5V nominal. DAC D Voltage Output. DAC C Voltage Output. Reference Input Voltage Low. Sets minimum output voltage for all DACs.
1 2 3
V
4
SS
5 6 7
DAC7624 DAC7625
8
9 10 11 12 13 14
, DAC7624) or zero-scale (000H, DAC7625)
H
V
28
V
27
V
26
V
25
NIC
24
CS
23
A0
22
A1
21
R/W
20
DB11 (MSB)
19
DB10
18
DB9
17
DB8
16
DB7
15
REFL
OUTC
OUTD
DD
®
DAC7624/7625
4
TYPICAL PERFORMANCE CURVES: VSS = 0V
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B)
200
H
000
H
FFF
H
Digital Input Code
DLE (LSB) LE (LSB)
0.50
0.00 –0.25 –0.50
0.50
0.25
0.00
–0.50
–0.25
0.25
400H600H800HA00HC00HE00
H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D)
200
H
000
H
FFF
H
Digital Input Code
DLE (LSB) LE (LSB)
0.50
0.00 –0.25 –0.50
0.50
0.25
0.00
–0.50
–0.25
0.25
400H600H800HA00HC00HE00
H
LINEARITY ERROR vs CODE
(DAC B, –40°C and +85°C)
200
H
000
H
FFF
H
Digital Input Code
LE (LSB) LE (LSB)
0.50
0.00 –0.25 –0.50
0.50
0.25
0.00
–0.50
–0.25
0.25
400H600H800HA00HC00HE00
H
+85°C
–40°C
At TA = +25°C, VDD = +5V, VSS = 0V, V
REFH
= +2.5V, V
= 0V, representative unit, unless otherwise specified.
REFL
0.50
0.25
0.00 –0.25 –0.50
0.50
0.25
0.00 –0.25
DLE (LSB) LE (LSB)
–0.50
0.50
0.25
0.00 –0.25 –0.50
0.50
0.25
0.00 –0.25
DLE (LSB) LE (LSB)
–0.50
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
(DAC A)
200
000
H
400H600H800HA00HC00HE00
H
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C)
200
000
H
400H600H800HA00HC00HE00
H
Digital Input Code
FFF
H
H
FFF
H
H
0.50
0.25
0.00
–0.25
+85°C
–0.50
0.50
0.25
0.00
LE (LSB) LE (LSB)
–0.25
–40°C
–0.50
000
200
H
H
LINEARITY ERROR vs CODE
(DAC A, –40°C and +85°C)
400H600H800HA00HC00HE00
Digital Input Code
FFF
H
H
®
5
DAC7624/7625
TYPICAL PERFORMANCE CURVES: VSS = 0V (CONT)
At TA = +25°C, VDD = +5V, VSS = 0V, V
REFH
= +2.5V, V
= 0V, representative unit, unless otherwise specified.
REFL
0.50
0.25
0.00
–0.25
+85°C
–0.50
0.50
0.25
0.00
LE (LSB) LE (LSB)
–0.25
–40°C
–0.50
000
200
H
ZERO-SCALE ERROR vs TEMPERATURE 6 5 4
DAC D
3 2
DAC C
1 0
Zero-Scale Error (LSB)
–1 –2
LINEARITY ERROR vs CODE
(DAC C, –40°C and +85°C)
400H600H800HA00HC00HE00
H
Digital Input Code
(Code 010
DAC A
20–40 100–20 0 40
)
H
DAC B
60 80
Temperature (°C)
LINEARITY ERROR vs CODE
(DAC D, –40°C and +85°C)
0.50
0.25
0.00
–0.25
+85°C
–0.50
0.50
0.25
0.00
LE (LSB) LE (LSB)
–0.25
–40°C
FFF
–0.50
H
H
000
200
400H600H800HA00HC00HE00
H
H
FFF
H
H
Digital Input Code
FULL-SCALE ERROR vs TEMPERATURE
6
(Code FFF
)
H
5 4
DAC D
3
DAC A
2
DAC C
1 0
Full-Scale Error (LSB)
DAC B
–1 –2
20–40 100–20 0 40
60 80
Temperature (°C)
®
DAC7624/7625
6
TYPICAL PERFORMANCE CURVES: VSS = –5V
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B)
200
H
000
H
FFF
H
Digital Input Code
DLE (LSB) LE (LSB)
0.50
0.00 –0.25 –0.50
0.50
0.25
0.00
–0.50
–0.25
0.25
400H600H800HA00HC00HE00
H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D)
200
H
000
H
FFF
H
Digital Input Code
DLE (LSB) LE (LSB)
0.50
0.00 –0.25 –0.50
0.50
0.25
0.00
–0.50
–0.25
0.25
400H600H800HA00HC00HE00
H
LINEARITY ERROR vs CODE
(DAC B, –40°C and +85°C)
200
H
000
H
FFF
H
Digital Input Code
LE (LSB) LE (LSB)
0.50
0.00 –0.25 –0.50
0.50
+85°C
–40°C
0.25
0.00
–0.50
–0.25
0.25
400H600H800HA00HC00HE00
H
At TA = +25°C, VDD = +5V, VSS = –5V, V
REFH
= +2.5V, V
= –2.5V, representative unit, unless otherwise specified.
REFL
0.50
0.25
0.00 –0.25 –0.50
0.50
0.25
0.00 –0.25
DLE (LSB) LE (LSB)
–0.50
0.50
0.25
0.00 –0.25 –0.50
0.50
0.25
0.00 –0.25
DLE (LSB) LE (LSB)
–0.50
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
(DAC A)
200
000
H
400H600H800HA00HC00HE00
H
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C)
200
000
H
400H600H800HA00HC00HE00
H
Digital Input Code
FFF
H
H
FFF
H
H
0.50
0.25
0.00 –0.25
+85°C
–0.50
0.50
0.25
0.00
LE (LSB) LE (LSB)
–0.25
–40°C
–0.50
000
200
H
H
LINEARITY ERROR vs CODE
(DAC A, –40°C and +85°C)
400H600H800HA00HC00HE00
Digital Input Code
FFF
H
H
®
7
DAC7624/7625
TYPICAL PERFORMANCE CURVES: VSS = –5V (CONT)
At TA = +25°C, VDD = +5V, VSS = –5V, V
REFH
= +2.5V, V
= –2.5V, representative unit, unless otherwise specified.
REFL
0.50
0.25
0.00
–0.25
+85°C
–0.50
0.50
0.25
0.00
LE (LSB) LE (LSB)
–0.25
–40°C
–0.50
000
200
H
H
ZERO-SCALE ERROR vs TEMPERATURE
3.0
2.5
2.0
DAC D
1.5
DAC A
1.0
DAC C
0.5
0.0
Zero-Scale Error (LSB)
–0.5 –1.0
LINEARITY ERROR vs CODE
(DAC C, –40°C and +85°C)
400H600H800HA00HC00HE00
Digital Input Code
(Code 000
)
H
DAC B
20–40 100–20 0 40
60 80
Temperature (°C)
LINEARITY ERROR vs CODE
(DAC D, –40°C and +85°C)
0.50
0.25
0.00
–0.25
+85°C
–0.50
0.50
0.25
0.00
LE (LSB) LE (LSB)
–0.25
–40°C
FFF
–0.50
H
H
000
200
400H600H800HA00HC00HE00
H
H
FFF
H
H
Digital Input Code
FULL-SCALE ERROR vs TEMPERATURE
3.0
(Code FFF
)
H
2.5
2.0
1.5
DAC D DAC A
DAC B
1.0
0.5
0.0
Full-Scale Error (LSB)
DAC C
–0.5 –1.0
20–40 100–20 0 40
60 80
Temperature (°C)
®
DAC7624/7625
8
THEORY OF OPERATION
The DAC7624 and DAC7625 are quad, voltage output, 12-bit digital-to-analog converters (DACs). The architecture is a classic R-2R ladder configuration followed by an opera­tional amplifier that serves as a buffer. Each DAC has its own R-2R ladder network and output op-amp, but all share the reference voltage inputs. The minimum voltage output (“zero-scale”) and maximum voltage output (“full-scale”)
DAC7624
V
REFH
V
OUTB
V
OUTA
V
SS
LDAC DB0 DB1 DB2 DB3 DB4 DB5 DB6
DAC7625
+2.500V
0V to +2.5V 0V to +2.5V
Load DAC Registers
0.1µF
Reset DACs
Data Bus
1 2 3 4 5 GND
(1)
6 RESET 7 8 9
10
11 12 13 14
are set by the external voltage references (V
REFL
and V respectively). The digital input is a 12-bit parallel word and the DAC input registers offer a readback capability. The converters can be powered from a single +5V supply or a dual ±5V supply. Each device offers a reset function which immediately sets all DAC output voltages and DAC regis­ters to mid-scale (DAC7624, code 800H) or to zero-scale (DAC7625, code 000H). See Figures 1 and 2 for the basic operation of the DAC7624/25.
V
28
REFL
V
OUTC
V
OUTD
V
NIC
R/W
DB11
DB10
DB9 DB8 DB7
CS
27 26 25
DD
24 23 22
A0
21
A1
20 19 18 17 16 15
0V to +2.5V 0V to +2.5V
0.1µF 1µF to 10µF
Chip Select
Address Bus or Decoder
Read/Write
Data Bus
+5V
+
REFH
,
NOTE: (1) Reset LOW sets all DACs to code 800
on the DAC7624 and to code 000H on the DAC7625.
H
FIGURE 1. Basic Single-Supply Operation of the DAC7624/25.
DAC7624
V
REFH
V
OUTB
V
OUTA
V
SS
LDAC DB0 DB1 DB2 DB3 DB4 DB5 DB6
DAC7625
–5V
+2.500V
–2.5V to +2.5V –2.5V to +2.5V
+
Load DAC Registers
0.1µF
0.1µF1µF to 10µF
Reset DACs
Data Bus
1 2 3 4 5 GND
(1)
6 RESET 7 8
9 10 11 12 13 14
V
REFL
V
OUTC
V
OUTD
V
NIC
R/W
DB11
DB10
DB9 DB8 DB7
CS
28 27 26 25
DD
24 23 22
A0
21
A1
20 19 18 17 16 15
0.1µF
–2.5V to +2.5V –2.5V to +2.5V
0.1µF 1µF to 10µF
Chip Select
Address Bus or Decoder
Read/Write
Data Bus
–2.500V
+5V
+
NOTE: (1) Reset LOW sets all DACs to code 800H on the DAC7624 and to code 000H on the DAC7625.
FIGURE 2. Basic Dual-Supply Operation of the DAC7624/25.
®
9
DAC7624/7625
ANALOG OUTPUTS
When VSS = –5V (dual supply operation), the output ampli­fier can swing to within 2.25V of the supply rails, guaran­teed over the –40°C to +85°C temperature range. With V
SS
= 0V (single-supply operation), the output can swing to ground. Note that the settling time of the output op-amp will be longer with voltages very near ground. Also, care must be taken when measuring the zero-scale error when VSS = 0V. Since the output voltage cannot swing below ground, the output voltage may not change for the first few digital input codes (000H, 001H, 002H, etc.) if the output amplifier has a negative offset.
The behavior of the output amplifier can be critical in some applications. Under short circuit conditions (DAC output shorted to ground), the output amplifier can sink a great deal more current than it can source. See the specification table for more details concerning short circuit current.
REFERENCE INPUTS
The reference inputs, V between VSS+2.25V and VDD–2.25V provided that V at least 1.25V greater than V each DAC is equal to V
REFL
and V
REFL
plus a small offset voltage
REFL
, can be any voltage
REFH
. The minimum output of
REFH
is
(essentially, the offset of the output op-amp). The maximum output is equal to V
plus a similar offset voltage. Note
REFH
that VSS (the negative power supply) must either be connected to ground or must be in the range of –4.75V to –5.25V. The voltage on VSS sets several bias points within the converter, if VSS is not in one of these two configura­tions, the bias values may be in error and proper operation of the device is not guaranteed.
The current into the V
input depends on the DAC output
REFH
voltages and can vary from a few microamps to approxi­mately 0.5 milliamp. The V
source will not be required
REFH
to sink current, only source it. Bypassing the reference voltage or voltages with at least a 0.1uF capacitor placed as close to the DAC7624/25 package is strongly recommended.
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7624/25. Note that each internal register is level triggered and not edge triggered. When the appropriate signal is LOW, the register becomes transparent. When this signal is returned HIGH, the digital word currently in the register is latched. The first set of registers (the Input Registers) are triggered via the A0, A1, R/W, and CS inputs. Only one of these registers is transparent at any given time. The second set of registers (the DAC Registers) are all transparent when LDAC input is pulled LOW.
Each DAC can be updated independently by writing to the appropriate Input Register and then updating the DAC Register. Alternatively, the entire DAC Register set can be configured as always transparent by keeping LDAC LOW— the DAC update will occur when the Input Register is written.
The double buffered architecture is mainly designed so that each DAC Input Register can be written at any time and then all DAC voltages updated simultaneously by pulling LDAC LOW. It also allows a DAC Input Register to be written to at any point and the DAC voltage to be synchronously changed via a trigger signal connected to LDAC.
SELECTED SELECTED STATE OF
A1 A0 R/W CS RESET LDAC REGISTER REGISTER REGISTERS
(1)
L
L H L L H L B Transparent Transparent H L L L H L C Transparent Transparent H H L L H L D Transparent Transparent
LLLLHH A Transparent Latched
L H L L H H B Transparent Latched H L L L H H C Transparent Latched H H L L H H D Transparent Latched
L L H L H H A Readback Latched
L H H L H H B Readback Latched H L H L H H C Readback Latched H H H L H H D Readback Latched
(3)
X
X X X H H H NONE (All Latched) Latched XXXXLX ALL Reset
NOTES: (1) L = Logic LOW. (2) H= Logic HIGH. (3) X = Don’t Care. (4) DAC7624 resets to 800H, DAC7625 resets to 000H. When RESET rises, all registers that are in their latched state retain the reset value.
LLLH
X X H H L NONE (All Latched) Transparent
(2)
L A Transparent Transparent
INPUT INPUT ALL DAC
STATE OF
(4)
Reset
(4)
TABLE I. DAC7624 and DAC7625 Control Logic Truth Table.
®
DAC7624/7625
10
DIGITAL TIMING
Figure 3 and Table II provide detailed timing for the digital interface of the DAC7624 and DAC7625.
t
CS
R/W
A0/A1
Data Out
t
RDS
Data Output Timing
RCS
t
RDH
t
AS
t
AH
t
DZ
Data Valid
t
CSD
DIGITAL INPUT CODING
The DAC7624 and DAC7625 input data is in straight binary format. The output voltage is given by the following equa­tion:
V
()
V
= V
OUT
REFL
REFH–VREFL
+
4096
•N
where N is the digital input code. This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors.
t
CS
R/W
A0/A1
LDAC
Data In
RESET
t
DS
WCS
t
WS
t
AS
t
LS
t
WH
t
AH
t
LH
Digital Input Timing
t
LWD
t
DH
t
RESET
FIGURE 3. Digital Input and Output Timing.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
RCS
t
RDS
t
RDH
t
t
CSD
t
WCS
t t
t t t t t t
t
LWD
t
RESET
DZ
WS WH AS AH
DS DH
CS HIGH to Data Bus in High Impedance 100 ns
LS LH
CS LOW for Read 200 ns
R/W HIGH to CS LOW 10 ns
R/W HIGH after CS HIGH 0 ns
CS LOW to Data Bus Valid 100 160 ns
CS LOW for Write 50 ns
R/W LOW to CS LOW 0 ns
R/W LOW after CS HIGH 0 ns
Address Valid to CS LOW 0 ns
Address Valid after CS HIGH 0 ns
LDAC LOW to CS LOW 70 ns
LDAC LOW after CS HIGH 50 ns
Data Valid to CS LOW 0 ns
Data Valid after CS HIGH 0 ns
LDAC LOW 50 ns
RESET LOW 50 ns
TABLE II. Timing Specifications (TA = –40°C to +85°C).
11
®
DAC7624/7625
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2006
PACKAGING INFORMATION
Orderable Device Status
DAC7624P NRND PDIP NTD 28 13 Green (RoHS &
DAC7624PB NRND PDIP NTD 28 13 Green (RoHS &
DAC7624PBG4 ACTIVE PDIP NTD 28 13 Green (RoHS &
DAC7624U ACTIVE SOIC DW 28 28 Green (RoHS &
DAC7624U/1K ACTIVE SOIC DW 28 1000 Green (RoHS &
DAC7624U/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS &
DAC7624UB ACTIVE SOIC DW 28 28 Green (RoHS &
DAC7624UB/1K ACTIVE SOIC DW 28 1000 Green (RoHS &
DAC7624UB/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS &
DAC7624UBG4 ACTIVE SOIC DW 28 28 Green (RoHS &
DAC7624UG4 ACTIVE SOIC DW 28 28 Green (RoHS &
DAC7625P NRND PDIP NTD 28 13 Green (RoHS &
DAC7625PB NRND PDIP NTD 28 13 Green (RoHS &
DAC7625PG4 ACTIVE PDIP NTD 28 13 Green (RoHS &
DAC7625U ACTIVE SOIC DW 28 28 Green (RoHS &
DAC7625U/1K ACTIVE SOIC DW 28 1000 Green (RoHS &
DAC7625U/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS &
DAC7625UB ACTIVE SOIC DW 28 28 Green (RoHS &
DAC7625UB/1K ACTIVE SOIC DW 28 1000 Green (RoHS &
DAC7625UB/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS &
DAC7625UBG4 ACTIVE SOIC DW 28 28 Green (RoHS &
DAC7625UG4 ACTIVE SOIC DW 28 28 Green (RoHS &
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(2)
Lead/Ball Finish MSL Peak Temp
A194 NIPDAU N / A for Pkg Type
A194 NIPDAU N / A for Pkg Type
A194 NIPDAU N / A for Pkg Type
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
A194 NIPDAU N / A for Pkg Type
A194 NIPDAU N / A for Pkg Type
A194 NIPDAU N / A for Pkg Type
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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2-Oct-2006
Addendum-Page 2
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