TEXAS INSTRUMENTS DAC7614 Technical data

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DAC7614

Quad, Serial Input, 12-Bit, Voltage Output

DIGITAL-TO-ANALOG CONVERTER

FEATURES

● LOW POWER: 20mW

● UNIPOLAR OR BIPOLAR OPERATION

● SETTLING TIME: 10µs to 0.012%

● 12-BIT LINEARITY AND MONOTONICITY:

–40°C to +85°C

● USER SELECTABLE RESET TO MID-

SCALE OR ZERO-SCALE

● SECOND-SOURCE for DAC8420

● SMALL 20-LEAD SSOP PACKAGE

DESCRIPTION

The DAC7614 is a quad, serial input, 12-bit, voltage output digital-to-analog converter (DAC) with guaranteed 12-bit monotonic performance over the –40°C to +85°C temperature range. An asynchronous reset clears all registers to either mid-scale (800H) or zeroscale (000H), selectable via the RESETSEL pin. The device can be powered from a single +5V supply or from dual +5V and –5V supplies.

APPLICATIONS

● ATE PIN ELECTRONICS

● PROCESS CONTROL

● CLOSED-LOOP SERVO-CONTROL

● MOTOR CONTROL

● DATA ACQUISITION SYSTEMS

Low power and small size makes the DAC7614 ideal for process control, data acquisition systems, and closed-loop servo-control. The device is available in 16-pin plastic DIP, 16-lead SOIC, or 20-lead SSOP packages, and is guaranteed over the –40°C to +85°C temperature range.

SBAS092

GND

DAC

RESET RESETSELLOADDACS

DAC

SDI

Serial-to-

Parallel

CLK

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

Shift

DAC

Select

REFH

DAC A

DAC B

DAC C

DAC D

REFL

OUTA

OUTB

OUTC

OUTD

SPECIFICATIONS

At TA = –40°C to +85°C, VDD = +5V, VSS = –5V, V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ACCURACY

Linearity Error Linearity Matching

(1)

(3)

Differential Linearity Error V Monotonicity 12 ✻ Bits Zero-Scale Error Code = 000 Zero-Scale Drift 25 ✻✻ppm/°C Zero-Scale Matching

(3)

Full-Scale Error Code = FFF Full-Scale Matching

(3)

Zero-Scale Error Code = 00A Zero-Scale Drift V Zero-Scale Matching

(3)

Full-Scale Error Code = FFF Full-Scale Matching

(3)

Power Supply Rejection 30 ✻ ppm/V

ANALOG OUTPUT

Voltage Output

(4)

Output Current –1.25 +1.25 ✻✻mA Load Capacitance No Oscillation 100 ✻ pF Short-Circuit Current +5, –15 ✻ mA Short-Circuit Duration

REFERENCE INPUT

Input Range VSS = 0V or –5V

REFH

Input Range VSS = 0V 0

REFL

Input Range VSS = –5V –2.5

REFL

DYNAMIC PERFORMANCE

Settling Time

(5)

Channel-to-Channel Crosstalk Full-Scale Step 0.1 ✻ LSB

On Any Other DAC, RL = 2kΩ

Output Noise Voltage Bandwidth: 0Hz to 1MHz 40 ✻ nV/√Hz

DIGITAL INPUT/OUTPUT

Logic Family TTL-Compatible CMOS ✻ Logic Levels

Data Format Straight Binary ✻

POWER SUPPLY REQUIREMENTS

Power Dissipation V

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

= +2.5V, and V

REFH

= –2.5V, unless otherwise noted.

REFL

DAC7614E, P, U DAC7614EB, PB, UB

VSS = 0V or –5V ±2 ±1 LSB VSS = 0V or –5V ±2 ±1 LSB

= 0V or –5V ±1 ±1 LSB

±4 ✻ LSB

±2 ±1 LSB

±4 ✻ LSB ±2 ±1 LSB

, VSS = 0V ±8 ✻ LSB

= 0V 5 10 ✻✻ppm/°C

VSS = 0V ±4 ±2 LSB

, VSS = 0V ±8 ✻ LSB

VSS = 0V ±4 ±2 LSB

VSS = 0V or –5V V

REFL

Indefinite

+1.25

REFH

✻✻V

✻

+2.5 ✻✻V V V

REFH REFH

–1.25 –1.25

✻✻V ✻✻V

To ±0.012% 5 10 ✻✻ µs

| I

| ≤ 10µA 2.4 VDD+0.3 ✻✻V

| I

| ≤ 10µA –0.3 0.8 ✻✻V

4.75 5.25 ✻✻V

If VSS ≠ 0V –5.25 –4.75 ✻✻V

1.5 1.9 ✻✻ mA

–2.1 –1.6 ✻✻ mA

= –5V 15 20 ✻✻ mW

= 0V 7.5 10 ✻✻ mW

(2)

✻ Specification same as grade to the left. NOTES: (1) If V

one LSB is 1.22mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error. (5) If V

to 00AH.

FFF

= 0V, specification applies at code 00AH and above. (2) LSB means Least Significant Bit, with V

= –5V, full-scale step from code 000H to FFFH or vice-versa. If VSS = 0V, full-scale positive step from code 000H to FFFH and negative step from code

equal to +2.5V and V

REFH

equal to –2.5V,

REFL

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

DAC7614

ABSOLUTE MAXIMUM RATINGS

VDD to VSS........................................................................... –0.3V to +11V

VDD to GND ........................................................................ –0.3V to +5.5V

to VSS...............................................................–0.3V to (VDD – VSS)

REFL

VDD to V V

REFH

Digital Input Voltage to GND...................................... –0.3V to V

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ......................................... –40°C to +85°C

Storage Temperature Range .......................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.

..............................................................–0.3V to (VDD – VSS)

REFH

to V

............................................................–0.3V to (VDD – VSS)

REFL

(1)

ELECTROSTATIC DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with

+ 0.3V

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

MAXIMUM MAXIMUM

LINEARITY DIFFERENTIAL PACKAGE SPECIFICATION

PRODUCT (LSB) (LSB) PACKAGE NUMBER

DAC7614P ±2 ±1 16-Pin DIP 180 –40°C to +85°C DAC7614P Rails DAC7614PB ±1

DAC7614U ±2 ±1 16-Lead SOIC 211 –40°C to +85°C DAC7614U Rails

ERROR LINEARITY DRAWING TEMPERATURE ORDERING TRANSPORT

""" "DAC7614PB Rails

"" """ "DAC7614U/1K Tape and Reel

DAC7614UB ±1 ±1 16-Lead SOIC 211 –40°C to +85°C DAC7614UB Rails

"" """ "DAC7614UB/1K Tape and Reel

DAC7614E ±2 ±1 20-Lead SSOP 334 –40°C to +85°C DAC7614E Rails

"" """ "DAC7614E/1K Tape and Reel

DAC7614EB ±1 ±1 20-Lead SSOP 334 –40°C to +85°C DAC7614EB Rails

"" """ "DAC7614EB/1K Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7614EB/1K” will get a single 1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

(1)

RANGE NUMBER

(2)

MEDIA

DAC7614

PIN CONFIGURATION—P, U Packages

PIN CONFIGURATION—E Package

Top View PDIP, SOIC

V V

V V V V

OUTD

OUTC

REFL

REFH

OUTB

OUTA

2 3 4

DAC7614P, U

5 6 7 8

RESETSEL

RESET

LOADDACS

NIC

CLK

SDI

GND

PIN DESCRIPTIONS—P, U Packages

PIN LABEL DESCRIPTION

1VDDPositive Analog Supply Voltage, +5V nominal. 2V 3V 4V

6V 7V 8V

OUTD

OUTC

REFL

REFH

OUTB

OUTA

9 GND Ground 10 SDI Serial Data Input 11 CLK Serial Data Clock 12 CS Chip Select Input 13 NIC Not Internally Connected. 14 LOADDACS The selected DAC register becomes transparent

15 RESET Asynchronous Reset Input. Sets all DAC registers

16 RESETSEL When LOW, a LOW on RESET will cause all DAC

DAC D Voltage Output DAC C Voltage Output Reference Input Voltage Low. Sets minimum out-

put voltage for all DACs. Reference Input Voltage High. Sets maximum out-

put voltage for all DACs. DAC B Voltage Output DAC A Voltage Output Negative Analog Supply Voltage, 0V or –5V nomi-

nal.

when LOADDACS is LOW. It is in the latched state when LOADDACS is HIGH.

to either zero-scale (000 when LOW. RESETSEL determines which code is

) or mid-scale (800H)

active.

registers to be set to code 000 is HIGH, a LOW on RESET will set the registers to code 800

. When RESETSEL

Top View SSOP

V V

V V V

OUTD

OUTC

REFH

OUTB

OUTA

REFL

NIC NIC

2 3 4 5

DAC7614E

6 7 8 9

RESETSEL

RESET

LOADDACS

NIC

CLK

SDI

GND

PIN DESCRIPTIONS—E Package

PIN LABEL DESCRIPTION

1VDDPositive Analog Supply Voltage, +5V nominal. 2V 3V 4V

OUTD

OUTC

REFL

5 NIC Not Internally Connected. 6 NIC Not Internally Connected. 7V

8V 9V 10 V

REFH

OUTB

OUTA

11 GND Ground 12 SDI Serial Data Input 13 CLK Serial Data Clock 14 CS Chip Select Input 15 NIC Not Internally Connected. 16 NIC Not Internally Connected. 17 NIC Not Internally Connected. 18 LOADDACS The selected DAC register becomes transparent

19 RESET Asynchronous Reset Input. Sets all DAC registers

20 RESETSEL When LOW, a LOW on RESET will cause all DAC

DAC D Voltage Output DAC C Voltage Output Reference Input Voltage Low. Sets minimum out-

put voltage for all DACs.

Reference Input Voltage High. Sets maximum output voltage for all DACs.

DAC B Voltage Output. DAC A Voltage Output. Negative Analog Supply Voltage, 0V or –5V nomi-

nal.

when LOADDACS is LOW. It is in the latched state when LOADDACS is HIGH.

to either zero-scale (000 when LOW. RESETSEL determines which code is

) or mid-scale (800H)

active.

registers to be set to code 000 is HIGH, a LOW on RESET will set the registers to code 800

. When RESETSEL

DAC7614

TYPICAL PERFORMANCE CURVES: VSS = 0V

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B)

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00 –0.25 –0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

LINEARITY ERROR and DIFFERENTIAL

LINEARITY ERROR vs CODE

(DAC D)

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00 –0.25 –0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

LINEARITY ERROR vs CODE

(DAC B, –40°C and +85°C)

000

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00 –0.25 –0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

+85°C

–40°C

200H400H600H800HA00HC00HE00HFFF

At TA = +25°C, VDD = +5V, VSS = 0V, V

= +2.5V, and V

REFH

= 0V, representative unit, unless otherwise specified.

REFL

0.50

0.25

0.00 –0.25 –0.50

0.50

0.25

0.00 –0.25

DLE (LSB) LE (LSB)

–0.50

0.50

0.25

0.00 –0.25 –0.50

0.50

0.25

0.00 –0.25

DLE (LSB) LE (LSB)

–0.50

DIFFERENTIAL LINEARITY ERROR vs CODE

LINEARITY ERROR and

(DAC A)

200

000

400H600H800HA00HC00HE00HFFF

Digital Input Code

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C)

200H400H600H800HA00HC00HE00HFFF

000

Digital Input Code

LINEARITY ERROR vs CODE

(DAC A, –40°C and +85°C)

0.50

+85°C

0.25

0.00 –0.25 –0.50

0.50

LE (LSB) LE (LSB)

–40°C

0.25

0.00 –0.25 –0.50

200H400H600H800HA00HC00HE00HFFF

000

Digital Input Code

DAC7614

TYPICAL PERFORMANCE CURVES: VSS = 0V (CONT)

At TA = +25°C, VDD = +5V, VSS = 0V, V

= +2.5V, and V

REFH

= 0V, representative unit, unless otherwise specified.

REFL

0.50 +85°C

0.25

0.00

–0.25 –0.50

0.50 –40°C

0.25

0.00

LE (LSB) LE (LSB)

–0.25 –0.50

2.75

2.25

1.75

1.25

0.75

A: Output Voltage (V)

0.25

200H400H600H800HA00HC00HE00HFFF

000

POSITIVE SLEW RATE and SETTLING TIME

LOADDACS

LINEARITY ERROR vs CODE

(DAC C, –40°C and +85°C)

Digital Input Code

LINEARITY ERROR vs CODE

0.50 +85°C

0.25

0.00

–0.25 –0.50

0.50 –40°C

0.25

0.00

LE (LSB) LE (LSB)

–0.25 –0.50

000

200H400H600H800HA00HC00HE00HFFF

2.75

2.25

1.75

(DAC D, –40°C and +85°C)

Digital Input Code

NEGATIVE SLEW RATE and SETTLING TIME

(LSB)

–3

–6

1.25

0.75

A: Output Voltage (V)

0.25

LOADDACS

–3

–6

–0.25

–2 8–1

0 1 2 3 4 5 6 7

Time (µs)

–9

–0.25

B: Output Voltage, Deviation from +2.5V (LSB)

–2 8–1

0 1 2 3 4 5 6 7

Time (µs)

–9

B: Output Voltage, Deviation from Code 00A

DAC7614

TYPICAL PERFORMANCE CURVES: VSS = –5V

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B)

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00 –0.25 –0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC D)

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00 –0.25 –0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

LINEARITY ERROR vs CODE

(DAC B, –40°C and +85°C)

000

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00 –0.25 –0.50

0.50

+85°C

–40°C

0.25

0.00

–0.50

–0.25

0.25

200H400H600H800HA00HC00HE00HFFF

At TA = +25°C, VDD = +5V, VSS = –5V, V

= +2.5V, and V

REFH

= –2.5V, representative unit, unless otherwise specified.

REFL

0.50

0.25

0.00 –0.25 –0.50

0.50

0.25

0.00 –0.25

DLE (LSB) LE (LSB)

–0.50

0.50

0.25

0.00 –0.25 –0.50

0.50

0.25

0.00 –0.25

DLE (LSB) LE (LSB)

–0.50

DIFFERENTIAL LINEARITY ERROR vs CODE

LINEARITY ERROR and

(DAC A)

200H400H600H800HA00HC00HE00HFFF

000

Digital Input Code

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C)

200H400H600H800HA00HC00HE00HFFF

000

Digital Input Code

LINEARITY ERROR vs CODE

(DAC A, –40°C and +85°C)

0.50 +85°C

0.25

0.00

–0.25 –0.50

LE (LSB) LE (LSB)

–40°C

0.25

0.00

–0.25

0.50

–0.50

000

200H400H600H800HA00HC00HE00HFFF

Digital Input Code

DAC7614

TYPICAL PERFORMANCE CURVES: VSS = –5V (CONT)

At TA = +25°C, VDD = +5V, VSS = –5V, V

= +2.5V, and V

REFH

= –2.5V, representative unit, unless otherwise specified.

REFL

0.50 +85°C

0.25

0.00

–0.25 –0.50

0.50 –40°C

0.25

0.00

LE (LSB) LE (LSB)

–0.25 –0.50

200

000

LOADDACS

–1

A: Output Voltage (V)

–2

LINEARITY ERROR vs CODE

(DAC C, –40°C and +85°C)

400H600H800HA00HC00HE00HFFF

Digital Input Code

POSITIVE SLEW RATE and SETTLING TIME

LINEARITY ERROR vs CODE

(DAC D, –40˚C and +85˚C)

0.50 +85˚C

0.25

0.00

–0.25 –0.50

0.50 –40˚C

0.25

0.00

LE (LSB) LE (LSB)

–0.25 –0.50

000

200

400H600H800HA00HC00HE00HFFF

Digital Input Code

–2

–1

A: Output Voltage (V)

–4

–2

NEGATIVE SLEW RATE and SETTLING TIME

LOADDACS

–2

–4

–3

–2 8–1

600

500

400

300

Current (µA)

200

REH

100

000

0 1 2 3 4 5 6 7

Time (µs)

CURRENT vs CODE

REFH

(All DACs Set to Indicated Code)

400

800

C00

Digital Input Code

FFF

–6

B: Output Voltage, Deviation from +2.5V (LSB)

–3

–2 8–1

0 1 2 3 4 5 6 7

(All DACs Set to Indicated Code)

–100

–200

–300

Current (µA)

REL

–400

–500

–600

000

400

Time (µs)

CURRENT vs CODE

REFL

800

Digital Input Code

–6

B: Output Voltage, Deviation from –2.5V (LSB)

C00

FFF

DAC7614

THEORY OF OPERATION

The DAC7614 is a quad, serial input, 12-bit, voltage output DAC. The architecture is a classic R-2R ladder configuration followed by an operational amplifier that serves as a buffer. Each DAC has its own R-2R ladder network and output op amp, but all share the reference voltage inputs. The minimum voltage output (“zero-scale”) and maximum voltage output (“full-scale”) are set by external voltage references (V and V

, respectively). The digital input is a 16-bit serial

REFH

word that contains the 12-bit DAC code and a 2-bit address code that selects one of the four DACs (the two remaining bits are unused). The converter can be powered from a single +5V supply or a dual ±5V supply. Each device offers a reset function which immediately sets all DAC output voltages and internal registers to either zero-scale (code 000H) or mid-scale (code 800H). The reset code is selected by the state of the RESETSEL pin (LOW = 000H, HIGH = 800H). See Figures 1 and 2 for the basic operation of the DAC7614.

REFL

ANALOG OUTPUTS

When VSS = –5V (dual supply operation), the output amplifier can swing to within 2.25V of the supply rails, over the –40°C to +85°C temperature range. With VSS = 0V (single-supply operation), the output can swing to ground. Note that the settling time of the output op amp will be longer with voltages very near ground. Also, care must be taken when measuring the zero-scale error when VSS = 0V. If the output amplifier has a negative offset, the output voltage may not change for the first few digital input codes (000H, 001H, 002H, etc.) since the output voltage cannot swing below ground.

The behavior of the output amplifier can be critical in some applications. Under short-circuit conditions (DAC output shorted to ground), the output amplifier can sink a great deal more current than it can source. See the Specifications table for more details concerning short-circuit current.

+5V

1µF to 10µF

0V to +2.5V 0V to +2.5V

+2.500V

0V to +2.5V 0V to +2.5V

NOTES: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal registers to code 000

(0V). If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800H (1.25V).

0.1µF

1 2 3 4 5 6 7 8

V V V V V V V V

OUTD

OUTC

REFL

REFH

OUTB

OUTA

DAC7614

FIGURE 1. Basic Single-Supply Operation of the DAC7614.

+5V

–2.5V to +2.5V –2.5V to +2.5V

–2.500V

+2.500V

–2.5V to +2.5V –2.5V to +2.5V

–5V

1µF to 10µF

DAC7614

0.1µF

NOTES: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal register to code 800

OUTD

OUTC

REFL

REFH

OUTB

OUTA

(0V). If RESETSEL is LOW, RESET LOW sets all internal registers to code 000H (–2.5V).

(1)

RESETSEL

RESET

LOADDACS

RESETSEL

LOADDACS

NIC

CLK

SDI

GND

(1)

RESET

NIC

CLK

SDI

GND

16 15 14 13 12 11 10

+5V

Reset DACs Update Selected Register

Chip Select Clock Serial Data In

Reset DACs Update Selected Register

Chip Select Clock Serial Data In

(2)

FIGURE 2. Basic Dual-Supply Operation of the DAC7614.

DAC7614

REFERENCE INPUTS

The reference inputs, V between V V

is at least 1.25V greater than V

REFH

+ 2.25V and V

output of each DAC is equal to V

REFL

and V

, can be any voltage

REFH

– 2.25V provided that

REFL

– 1LSB plus a small

REFL

. The minimum

offset voltage (essentially, the offset of the output op amp). The maximum output is equal to V

plus a similar

REFH

offset voltage. Note that VSS (the negative power supply) must either be connected to ground or must be in the range of –4.75V to –5.25V. The voltage on VSS sets several bias points within the converter. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not guaranteed.

The current into the reference inputs depends on the DAC output voltages and can vary from a few microamps to approximately 0.6 milliamp. Bypassing the reference voltage or voltages with a 0.1µF capacitor placed as close as possible to the DAC7614 package is strongly recommended.

DIGITAL INTERFACE

Figure 3 and Table I provide the basic timing for the DAC7614. The interface consists of a serial clock (CLK), serial data (SDI), and a load DAC signal (LOADDACS). In addition, a chip select (CS) input is available to enable serial communication when there are multiple serial devices. An

SYMBOL DESCRIPTION MIN TYP MAX UNITS

CSS

CSH

LD1

LD2

LDDW

RSSH

RSTW

Data Valid to CLK Rising

Data Held Valid after CLK Rises

CLK HIGH

CLK LOW

CS LOW to CLK Rising

CLK HIGH to CS Rising LOADDACS HIGH to CLK Rising CLK Rising to LOADDACS LOW

LOADDACS LOW Time

RESETSEL Valid to RESET LOW

RESET LOW Time

Settling Time

25 ns 20 ns 30 ns 50 ns 55 ns 15 ns 40 ns 15 ns 45 ns 25 ns 70 ns 10 µs

TABLE I. Timing Specifications (TA = –40°C to +85°C).

asynchronous reset input (RESET) is provided to simplify start-up conditions, periodic resets, or emergency resets to a known state.

The DAC code and address are provided via a 16-bit serial interface as shown in Figure 3. The first two bits select the DAC register that will be updated when LOADDACS goes LOW (see Table II). The next two bits are not used. The last 12 bits is the DAC code which is provided, most significant bit first.

SDI

CLK

LOADDAC

SDI

CLK

LOADDAC

OUT

RESET

RESETSEL

(MSB) (LSB)

A0 X X D11 D10 D9 D3 D2 D1 D0

css

LD1

LDDW

1 LSB ERROR BAND

RSSH

RSTW

CSH

LD2

LDDW

1 LSB ERROR BAND

FIGURE 3. DAC7614 Timing.

DAC7614

SELECTED SELECTED

A1 A0 LOADDACS RESET REGISTER REGISTER

(1)

L L H A Transparent

L H L H B Transparent H L L H C Transparent H H L H D Transparent

(2)

X H H NONE (All Latched)

X X X L ALL Reset

NOTES: (1) L = Logic LOW. (2) X = Don’t Care. (3) Resets to either 000H or

, per the RESETSEL state (LOW = 000H, HIGH = 800H). When RESET

800

rises, all registers that are in their latched state retain the reset value.

DAC DAC

STATE OF

(3)

TABLE II. Control Logic Truth Table.

Note that CS and CLK are combined with an OR gate and the output controls the serial-to-parallel shift register internal to the DAC7614 (see the block diagram on the front of this data sheet). These two inputs are completely interchangeable. In addition, care must be taken with the state of CLK when CS rises at the end of a serial transfer. If CLK is LOW when CS rises, the OR gate will provide a rising edge to the shift register, shifting the internal data one additional bit. The result will be incorrect data and possible selection of the wrong DAC.

If both CS and CLK are used, then CS should rise only when CLK is HIGH. If not, then either CS or CLK can be used to operate the shift register. See Table III for more information.

(1)

(2)

(4)

L ↑ ↑ L H H Advanced One Bit

(6)

NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH value is suggested in order to avoid a “false clock” from advancing the shift register and changing the shift register. (7) If data is clocked into the serial register while LOADDACS is LOW, the selected DAC register will change as the shift register bits “flow” through A1 and A0. This will corrupt the data in each DAC register that has been erroneously selected. (8) RESET LOW causes no change in the contents of the serial shift register.

(1)

CLK

LOADDACS

(3)

L H H No Change

(5)

XL XHL

H H No Change

H H Advanced One Bit

(7)

RESET SERIAL SHIFT REGISTER

H No Change

(8)

No Change

TABLE III. Serial Shift Register Truth Table.

Digital Input Coding

The DAC7614 input data is in Straight Binary format. The output voltage is given by the following equation:

= V

OUT

REFL

REFH

4096

– V

REFL

) • N

where N is the digital input code (in decimal). This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors.

DAC7614

LAYOUT

A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. As the DAC7614 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good performance from the converter.

Because the DAC7614 has a single ground pin, all return currents, including digital and analog return currents, must flow through the GND pin. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system (see Figure 4).

The power applied to VDD (as well as VSS, if not grounded) should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output.

As with the GND connection, VDD should be connected to a +5V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 1µF to 10µF and 0.1µF capacitors shown in Figure 4 are strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a “Pi” filter made up of inductors and capacitors—all designed to essentially lowpass filter the +5V supply, removing the high frequency noise (see Figure 4).

Digital Circuits

+5V

Power Supply

+5V

Ground

100µF

Optional

+5V

Ground

1µF to

10µF

Other

Analog

Components

0.1µF

DAC7614

GND

FIGURE 4. Suggested Power and Ground Connections for a DAC7614 Sharing a +5V Supply with a Digital System.

DAC7614

PACKAGE OPTION ADDENDUM

www.ti.com

4-Aug-2008

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

DAC7614E ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br)

DAC7614E/1K ACTIVE SSOP DB 20 1000 Green (RoHS &

no Sb/Br)

DAC7614E/1KG4 ACTIVE SSOP DB 20 1000 Green(RoHS &

no Sb/Br)

DAC7614EB ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br)

DAC7614EB/1K ACTIVE SSOP DB 20 1000 Green (RoHS &

no Sb/Br)

DAC7614EB/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS &

no Sb/Br)

DAC7614EBG4 ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br)

DAC7614EG4 ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br)

DAC7614P NRND PDIP N 16 25 Green (RoHS &

no Sb/Br)

DAC7614PB NRND PDIP N 16 25 Green (RoHS &

no Sb/Br)

DAC7614PBG4 NRND PDIP N 16 25 Green (RoHS &

no Sb/Br)

DAC7614PG4 NRND PDIP N 16 25 Green (RoHS &

no Sb/Br)

DAC7614U ACTIVE SOIC DW 16 48 Green (RoHS &

no Sb/Br)

DAC7614U/1K ACTIVE SOIC DW 16 1000 Green (RoHS &

no Sb/Br)

DAC7614U/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS &

no Sb/Br)

DAC7614UB ACTIVE SOIC DW 16 48 Green (RoHS &

no Sb/Br)

DAC7614UB/1K ACTIVE SOIC DW 16 1000 Green (RoHS &

no Sb/Br)

DAC7614UB/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS &

no Sb/Br)

DAC7614UBG4 ACTIVE SOIC DW 16 48 Green (RoHS &

no Sb/Br)

DAC7614UG4 ACTIVE SOIC DW 16 48 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU N / A for Pkg Type

Cu NiPdAu Level-3-260C-168 HR

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

4-Aug-2008

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

DAC7614E/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

DAC7614EB/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

DAC7614U/1K SOIC DW 16 1000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1

DAC7614UB/1K SOIC DW 16 1000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DAC7614E/1K SSOP DB 20 1000 346.0 346.0 33.0

DAC7614EB/1K SSOP DB 20 1000 346.0 346.0 33.0

DAC7614U/1K SOIC DW 16 1000 346.0 346.0 33.0

DAC7614UB/1K SOIC DW 16 1000 346.0 346.0 33.0

Pack Materials-Page 2

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TEXAS INSTRUMENTS DAC7614 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual