3 mm x 3 mm
Actual Size
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_
+
Interface
Logic
Input
Register
DAC
Register
String
DAC A
Power-Down
Logic
Power-On
Reset
V
DD
IOV
DD
V
REFA
V
FBA
V
OUT
A
V
REFB
GND
CLR
DCEN
SDIN
SYNC
SCLK
_
+
Input
Register
DAC
Register
String
DAC B
V
FBB
V
OUT
B
PD
SDO
FUNCTIONAL BLOCK DIAGRAM
DAC7552
查询DAC7552供应商
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES DESCRIPTION
• 2.7-V to 5.5-V Single Supply
• 12-Bit Linearity and Monotonicity
• Rail-to-Rail Voltage Output
• Settling Time: 5 µs (Max)
• Ultralow Glitch Energy: 0.1 nVs DAC7552 operates from a single 2.7-V to 5.5-V
• Ultralow Crosstalk: –100 dB
• Low Power: 440 µA (Max)
• Per-Channel Power Down: 2 µA (Max)
• Power-On Reset to Zero Scale
• SPI-Compatible Serial Interface: Up to 50 MHz to 50 MHz and is compatible with SPI, QSPI,
• Daisy-Chain Capability
• Asynchronous Hardware Clear
• Simultaneous or Sequential Update
• Specified Temperature Range: –40°C to 105°C
• Small 3-mm × 3-mm, 16-Lead QFN Package
APPLICATIONS
• Portable Battery-Powered Instruments
• Digital Gain and Offset Adjustment
• Programmable Voltage and Current Sources
• Programmable Attenuators
• Industrial Process Control
The DAC7552 is a 12-bit, dual-channel, voltage-output DAC with exceptional linearity and
monotonicity. Its proprietary architecture minimizes
undesired transients such as code-to-code glitch and
channel-to-channel crosstalk. The low-power
supply. The DAC7552 output amplifiers can drive a
2-k Ω , 200-pF load rail-to-rail with 5-µs settling time;
the output range is set using an external voltage
reference.
The 3-wire serial interface operates at clock rates up
Microwire™, and DSP interface standards. The out-
puts of all DACs may be updated simultaneously or
sequentially. The parts incorporate a power-on-reset
circuit to ensure that the DAC outputs power up to
zero volts and remain there until a valid write cycle to
the device takes place. The parts contain a
power-down feature that reduces the current consumption of the device to under 2 µA.
The small size and low-power operation makes the
DAC7552 ideally suited for battery-operated portable
applications. The power consumption is typically
1.5 mW at 5 V, 0.75 mW at 3 V, and reduces to 1 µW
in power-down mode.
The DAC7552 is available in a 16-lead QFN package
and is specified over –40°C to 105°C.
DAC7552
Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
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DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT PACKAGE TEMPERATURE
DAC7552 16 QFN RGT –40 °C TO 105 °C D752
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com .
PACKAGE PACKAGE ORDERING TRANSPORT
DESIGNATOR MARKING NUMBER MEDIA
SPECIFIED
RANGE
(1)
DAC7552IRGTT 250-piece Tape and Reel
DAC7552IRGTR 3000-piece Tape and Reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
V
to GND –0.3 V to 6 V
DD
Digital input voltage to GND –0.3 V to V
V
to GND –0.3 V to VDD+ 0.3 V
OUT
Operating temperature range –40°C to 105°C
Storage temperature range –65°C to 150°C
Junction temperature (TJMax) 150°C
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
(1)
UNIT
+ 0.3 V
DD
2
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DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS
V
= 2.7 V to 5.5 V, V
DD
specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution 12 Bits
Relative accuracy ±0.35 ±1 LSB
Differential nonlinearity Specified monotonic by design ±0.08 ±0.5 LSB
Offset error ±12 mV
Zero-scale error All zeroes loaded to DAC register ±12 mV
Gain error ±0.15 %FSR
Full-scale error ±0.5 %FSR
Zero-scale error drift 7 µV/ °C
Gain temperature coefficient 3 ppm of FSR/ °C
PSRR V
OUTPUT CHARACTERISTICS
Output voltage range 0 VREF V
Output voltage settling time RL= 2 k Ω; 0 pF < CL< 200 pF 5 µs
Slew rate 1.8 V/ µs
Capacitive load stability RL= ∞ 470
Digital-to-analog glitch impulse 1 LSB change around major carry 0.1 nV-s
Channel-to-channel crosstalk 1-kHz full-scale sine wave, –100 dB
Digital feedthrough 0.1 nV-s
Output noise density (10-kHz offset fre- 120 nV/rtHz
quency)
Total harmonic distortion F
DC output impedance 1 Ω
Short-circuit current V
Power-up time Coming out of power-down mode, 15
REFERENCE INPUT
VREF Input range 0 V
Reference input impedance V
Reference current µA
LOGIC INPUTS
Input current ±1 µA
V
, Input low voltage IOV
IN_L
V
, Input high voltage IOV
IN_H
Pin capacitance 3 pF
(1) Linearity tested using a reduced code range of 30 to 4065; output unloaded.
(2) Specified by design and characterization, not production tested. For 1.8 V < IOV
VIH= IOV
(2)
, VIL= GND.
DD
= V
REF
(1)
, RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications –40°C to 105°C, unless otherwise
DD
= 5 V 0.75 mV/V
(2)
DD
RL= 2 k Ω 1000
pF
outputs unloaded
= 1 kHz, FS= 1 MSPS, –85 dB
OUT
BW = 20 kHz
= 5 V 50
DD
V
= 3 V 20
DD
V
= 5 V
DD
Coming out of power-down mode, 15
V
= 3 V
DD
A and V
REF
V
A = V
REF
V
A and V
REF
V
A = V
REF
V
A and V
REF
≥ 2.7 V 0.3 IOV
DD
≥ 2.7 V 0.7 IOV
DD
B shorted together 50 k Ω
REF
B = V
REF
REF
B = V
REF
REF
= 5 V, 100 250
DD
B shorted together
= 3 V, 60 123
DD
B shorted together
DD
< 2.7 V, It is recommended that
DD
DD
DD
mA
µs
V
V
V
3
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DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)
V
= 2.7 V to 5.5 V, V
DD
specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
V
DD,
IDD(normal operation) DAC active and excluding load current
IDD(all power-down modes)
POWER EFFICIENCY
I
OUT
(3) IOV
(3)
, IOV
DD
V
= 3.6 V to 5.5 V 300 440
DD
V
= 2.7 V to 3.6 V 250 400
DD
V
= 3.6 V to 5.5 V 0.2 2
DD
V
= 2.7 V to 3.6 V 0.05 2
DD
/I
DD
operates down to 1.8 V with slightly degraded timing, as long as VIH= IOV
DD
= V
REF
, RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications –40°C to 105°C, unless otherwise
DD
VIH= IOV
VIH= IOV
I
LOAD
and VIL= GND µA
DD
and VIL= GND µA
DD
= 2 mA, V
= 5 V 93%
DD
2.7 5.5 V
and VIL= GND.
DD
4
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SCLK
SYNC
SDIN
D15 D14 D13
D12
D11 D1 D0 D15
t
8
t
4
t
3
t
2
t
1
t
7
t
6
t
5
D0
t
9
Input Word n Input Word n+1
Undefined
D15 D14
D0
Input Word n
t
10
SDO
CLR
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
TIMING CHARACTERISTICS
V
= 2.7 V to 5.5 V, RL= 2 k Ω to GND; all specifications –40°C to 105°C, unless otherwise specified
DD
(1) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
V
= 2.7 V to 3.6 V 20
(3)
t
SCLK cycle time ns
1
t
SCLK HIGH time ns
2
t
SCLK LOW time ns
3
SYNC falling edge to SCLK falling edge setup
t
4
time
t
Data setup time ns
5
t
Data hold time ns
6
t
SCLK falling edge to SYNC rising edge ns
7
t
Minimum SYNC HIGH time ns
8
t
SCLK falling edge to SDO valid ns
9
t
CLR pulse width low ns
10
DD
V
= 3.6 V to 5.5 V 20
DD
V
= 2.7 V to 3.6 V 10
DD
V
= 3.6 V to 5.5 V 10
DD
V
= 2.7 V to 3.6 V 10
DD
V
= 3.6 V to 5.5 V 10
DD
V
= 2.7 V to 3.6 V 4
DD
V
= 3.6 V to 5.5 V 4
DD
V
= 2.7 V to 3.6 V 5
DD
V
= 3.6 V to 5.5 V 5
DD
V
= 2.7 V to 3.6 V 4.5
DD
V
= 3.6 V to 5.5 V 4.5
DD
V
= 2.7 V to 3.6 V 0
DD
V
= 3.6 V to 5.5 V 0
DD
V
= 2.7 V to 3.6 V 20
DD
V
= 3.6 V to 5.5 V 20
DD
V
= 2.7 V to 3.6 V 10
DD
V
= 3.6 V to 5.5 V 10
DD
V
= 2.7 V to 3.6 V 10
DD
V
= 3.6 V to 5.5 V 10
DD
(1) All input signals are specified with tR= tF= 1 ns (10% to 90% of VDD) and timed from a voltage level of (V
(2) See Serial Write Operation timing diagram Figure 1 .
(3) Maximum SCLK frequency is 50 MHz at V
= 2.7 V to 5.5 V.
DD
DAC7552
ns
+ VIH)/2.
IL
Figure 1. Serial Write Operation
5
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1
2
3
4
12
11
10
9
SCLK
SYNC
IOV
DD
SDO
V
OUT
A
V
DD
GND
V
OUT
B
VFBA
VREFA
PD
DCEN
CLR
SDIN
VFBB
VREFB
16 15 14 13
5 6 7 8
DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
PIN DESCRIPTION
RGT PACKAGE
(TOP VIEW)
Terminal Functions
TERMINAL DESCRIPTION
NO. NAME
1 V
2 V
3 GND Ground
4 V
5 VFBB DAC B amplifier sense input. (For voltage output operation, connect to VOUTB externally.)
6 VREFB Positive reference voltage input for DAC B
7 PD Power-down
8 DCEN Daisy-chain enable
9 SDO Serial data output
10 IOVDD I/O voltage supply input. (For single supply operation, connect to VDD externally.)
11 SYNC Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out
12 SCLK Serial clock input
13 SDIN Serial data input
14 CLR Asynchronous input to clear the DAC registers. When CLR is low, the DAC registers are set to 000H and the output
15 VREFA Positive reference voltage input for DAC A
16 VFBA DAC A amplifier sense input. (For voltage output operation, connect to VOUTA externally.)
A Analog output voltage from DAC A
OUT
DD
OUT
Analog voltage supply input
B Analog output voltage from DAC B
to the DAC7552
voltage to 0 V.
6
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−1
−0.5
0
0.5
1
Linearity Error − LSB
−0.5
−0.25
0
0.25
0.5
0 512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
Differential Linearity Error − LSB
Channel A V
REF
= 4.096 V VDD = 5 V
Channel B V
REF
= 4.096 V VDD = 5 V
Linearity Error − LSB
Digital Input Code
Differential Linearity Error − LSB
−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0
512 1024 1536
2048 2560 3072 3584 4096
Linearity Error − LSB
Digital Input Code
Differential Linearity Error − LSB
−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 512 1024 1536 2048 2560 3072 3584 4096
Channel A V
REF
= 2.5 V VDD = 2.7 V
−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 512 1024 1536 2048 2560 3072 3584 4096
Channel B V
REF
= 2.5 V VDD = 2.7 V
Linearity Error − LSB
Digital Input Code
Differential Linearity Error − LSB
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs vs
DIGITAL INPUT CODE DIGITAL INPUT CODE
DAC7552
Figure 2. Figure 3.
LINEARITY ERROR AND LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs vs
DIGITAL INPUT CODE DIGITAL INPUT CODE
Figure 4. Figure 5.
7
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−40 −10 20 50 80
0
1
2
3
−1
TA − Free-Air Temperature − °C
Zero-Scale Error − mV
Channel A
Channel B
VDD = 5 V ,
V
REF
= 4.096 V
−1
0
1
2
3
−40 −10 20 50 80
TA − Free-Air Temperature − °C
Zero-Scale Error − mV
Channel A
Channel B
VDD = 2.7 V ,
V
REF
= 2.5 V
−2
−1
0
1
−40 −10 20 50 80
TA − Free-Air Temperature − °C
Full-Scale Error − mV
Channel A
Channel B
VDD = 2.7 V ,
V
REF
= 2.5 V
−40 −10 20 50 80
−2
−1
0
1
TA − Free-Air Temperature − °C
Full-Scale Error − mV
Channel A
Channel B
VDD = 5 V ,
V
REF
= 4.096 V
DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
ZERO-SCALE ERROR ZERO-SCALE ERROR
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 6. Figure 7.
FULL-SCALE ERROR FULL-SCALE ERROR
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
8
Figure 8. Figure 9.
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0
0.05
0.1
0.15
0.2
0 5 10 15
Typical for All Channels
VDD = 2.7 V ,
V
REF
= 2.5 V
VDD = 5.5 V ,
V
REF
= 4.096 V
− Output Voltage − V
V
O
I
SINK
− Sink Current − mA
DAC Loaded with 000h
5.20
5.30
5.40
5.50
0 5 10 15
Typical for All Channels
VDD = V
REF
= 5.5 V
− Output Voltage − V
V
O
I
SOURCE
− Source Current − mA
DAC Loaded with FFFh
2.4
2.5
2.6
2.7
0 5 10 15
Typical for All Channels
VDD = V
REF
= 2.7 V
− Output Voltage − V
V
O
I
SOURCE
− Source Current − mA
DAC Loaded with FFFh
0
50
100
150
200
250
300
350
400
0 512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
VDD = 5.5 V ,
V
REF
= 4.096 V
VDD = 2.7 V ,
V
REF
= 2.5 V
All Channels Powered, No Load
DD
I Supply Current − − Aµ
TYPICAL CHARACTERISTICS (continued)
SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL
DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
Figure 10. Figure 11.
SOURCE CURRENT AT POSITIVE RAIL SUPPLY CURRENT
Figure 12. Figure 13.
DIGITAL INPUT CODE
vs
9
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200
250
300
350
400
−40 −10 20 50 80 110
VDD = 5.5 V ,
V
REF
= 4.096 V
VDD = 2.7 V ,
V
REF
= 2.5 V
All Channels Powered, No Load
DD
I Supply Current − − Aµ
TA − Free-Air Temperature − °C
200
250
300
350
400
2.7 3.1 3.4 3.8 4.1 4.5 4.8 5.2 5.5
DD
I Supply Current − − Aµ
VDD − Supply Volatge − V
All DACs Powered,
No Load,
V
REF
= 2.5 V
0
500
1000
1500
2000
253 264 275 286 297 308 319 330 341
f − Frequency − Hz
IDD − Current Consumption − A
VDD = 5.5 V ,
V
REF
= 4.096 V
V
LOGIC
− Logic Input Voltage − V
0
400
800
1200
1600
0 1 2 3 4 5
DD
I Supply Current − − Aµ
TA = 25C, SCL Input
(All Other Inputs = GND)
VDD = 5.5 V ,
V
REF
= 4.096 V
VDD = 2.7 V ,
V
REF
= 2.5 V
DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT SUPPLY CURRENT
vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 14. Figure 15.
SUPPLY CURRENT HISTOGRAM OF CURRENT CONSUMPTION - 5.5 V
vs
LOGIC INPUT VOLTAGE
Figure 16. Figure 17.
10
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0
500
1000
1500
239 249 259 269 279 289 299 309 319
f − Frequency − Hz
IDD − Current Consumption − A
VDD = 2.7 V ,
V
REF
= 2.5 V
−4
−2
0
2
4
0
512 1024 1536 2048 2560 3072 3584
Digital Input Code
Total Error − mV
4095
Channel A Output
Channel B Output
VDD = 5 V ,
V
REF
= 4.096 V ,
TA = 25C
−4
−2
0
2
4
0 512 1024 1536 2048 2560 3072 3584
Digital Input Code
Total Error − mV
4095
Channel A Output
Channel B Output
VDD = 2.7 V ,
V
REF
= 2.5 V ,
TA = 25C
0
1
2
3
4
5
− Output Voltage − V
V
O
t − Time − 4 s/div
VDD = 5 V ,
V
REF
= 4.096 V ,
Power-Up Code 4000
TYPICAL CHARACTERISTICS (continued)
HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V TOTAL ERROR - 5 V
DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
Figure 18. Figure 19.
TOTAL ERROR - 2.7 V EXITING POWER-DOWN MODE
Figure 20. Figure 21.
11
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0
1
2
3
4
5
VDD = 5 V ,
Output Loaded With 200 pF to GND
Code 41 to 4055
− Output Voltage − V
V
O
t − Time − 5 s/div
V
REF
= 4.096 V
0
1
2
3
VDD = 2.7 V ,
Output Loaded With 200 pF to GND
Code 41 to 4055
− Output Voltage − V
V
O
t − Time − 5 s/div
V
REF
= 2.5 V
Time - (400 nS/Div)
Trigger Pulse
V
O
(5 mV/Div)
-
Trigger Pulse
V
O
(5 mV/Div)
-
Time - (400 nS/Div)
DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
LARGE-SIGNAL SETTLING TIME - 5 V LARGE-SIGNAL SETTLING TIME - 2.7 V
Figure 22. Figure 23.
MIDSCALE GLITCH WORST-CASE GLITCH
Figure 24. Figure 25.
12
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Time - (400 nS/Div)
Trigger Pulse
V
O
(5 mV/Div)
-
Time - (400 nS/Div)
Trigger Pulse
V
O
(5 mV/Div)
-
−100
−90
−80
−70
−60
−50
−40
0 1 2 3 4 5 6 7 8 9 10
VDD = 5 V , V
REF
= 4.096 V
−1 dB FSR Digital Input, Fs = 1 Msps
Measurement Bandwidth = 20 kHz
2nd Harmonic
3rd Harmonic
THD − Total Harmonic Distortion − dB
Output Frequency (Tone) − kHz
THD
TYPICAL CHARACTERISTICS (continued)
DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
DIGITAL FEEDTHROUGH ERROR CHANNEL-TO-CHANNEL CROSSTALK
Figure 26. Figure 27.
TOTAL HARMONIC DISTORTION
vs
OUTPUT FREQUENCY
FOR A FULL-SCALE SWING
Figure 28.
13
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DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
3-Wire Serial Interface
The DAC7552 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface.
Table 1. Serial Interface Programming
CONTROL DATA BITS DAC(s) FUNCTION
DB15 DB14 DB13 DB12 DB11-DB10
0 0 0 0 data A Single Channel Store. The input register of channel A is updated.
0 0 1 0 data B Single Channel Store. The input register of channel B is updated.
0 1 0 0 data A Single Channel Update. The input and DAC registers of channel A are
0 1 1 0 data B Single Channel Update. The input and DAC registers of channel A are
1 0 0 0 data A Single Channel Update. The input and DAC registers of channel B are
1 0 1 0 data B Single Channel Update. The input and DAC registers of channel B are
1 1 0 0 data A–B All Channel Update. The input and DAC registers of channels A and B are
1 1 1 0 data A–B All Channel DAC Update. The DAC register of channels A and B are updated
updated.
updated and the DAC register of channel B is updated with input register data.
updated.
updated and the DAC register of channel A is updated with input register data.
updated.
with input register data.
POWER-DOWN MODE
In power-down mode, the DAC outputs are programmed to one of three output impedances, 1 k Ω , 100 k Ω , or
floating.
Table 2. Power-Down Mode Control
EXTENDED CONTROL DATA BITS
DB15 DB14 DB13 DB12 DB11 DB10 DB9-DB0
0 0 X 1 0 0 X PWD Hi-Z (all channels)
0 0 X 1 0 1 X PWD 1 k Ω (all channels)
0 0 X 1 1 0 X PWD 100 k Ω (all channels)
0 0 X 1 1 1 X PWD Hi-Z (all channels)
0 1 X 1 0 0 X PWD Hi-Z (selected channel = A)
0 1 X 1 0 1 X PWD 1 k Ω (selected channel = A)
0 1 X 1 1 0 X PWD 100 k Ω (selected channel = A)
0 1 X 1 1 1 X PWD Hi-Z (selected channel = A)
1 0 X 1 0 0 X PWD Hi-Z (selected channel = B)
1 0 X 1 0 1 X PWD 1 k Ω (selected channel = B)
1 0 X 1 1 0 X PWD 100 k Ω (selected channel = B)
1 0 X 1 1 1 X PWD Hi-Z (selected channel = B)
1 1 X 1 0 0 X PWD Hi-Z (all channels)
1 1 X 1 0 1 X PWD 1 k Ω (all channels)
1 1 X 1 1 0 X PWD 100 k Ω (all channels)
1 1 X 1 1 1 X PWD Hi-Z (all channels)
FUNCTION
14
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_
+
Resistor String
Ref +
Ref −
DAC Register
V
OUT
V
REF
GND
V
FB
100 k100 k
50 k
V
REF
To Output
Amplifier
R
R R
R
GND
DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
THEORY OF OPERATION
D/A SECTION OUTPUT BUFFER AMPLIFIERS
The architecture of the DAC7552 consists of a string The output amplifier is capable of generating
DAC followed by an output buffer amplifier. Figure 29 rail-to-rail voltages on its output, which gives an
shows a generalized block diagram of the DAC output range of 0 V to V
architecture. load of 2 k Ω in parallel with up to 1000 pF to GND.
The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is
1.8 V/µs with a typical settling time of 3 µs with the
output unloaded.
DAC External Reference Input
Two separate reference pins are provided for two
DACs, providing maximum flexibility. VREFA serves
DAC A and VREFB serves DAC B. VREFA and
Figure 29. Typical DAC Architecture
VREFB can be externally shorted together for simplicity.
The input coding to the DAC7552 is unsigned binary,
which gives the ideal output voltage as:
V
= VREF × D/4096
OUT
Where D = decimal equivalent of the binary code that
is loaded to the DAC register which can range from 0
to 4095.
It is recommended to use a buffered reference in the
external circuit (e.g., REF3140). The input impedance
is typically 100 k Ω for each reference input pin.
Amplifier Sense Input
The DAC7552 contains two amplifier feedback input
pins, VFBA and VFBB. For voltage output operation,
VFBA and VFBB must externally connect to VOUTA
and VOUTB, respectively. For better DC accuracy,
these connections should be made at load points.
The VFBA and VFBB pins are also useful for a
variety of applications, including digitally controlled
current sources. Each feedback input pin is internally
connected to the DAC amplifier's negative input
Figure 30. Typical Resistor String
terminal through a 100-k Ω resistor; and, the amplifier's negative input terminal internally connects to
ground through another 100-k Ω resistor (See Fig-
RESISTOR STRING
The resistor string section is shown in Figure 30 . It is
simply a string of resistors, each of value R. The
digital code loaded to the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier. The voltage is tapped
off by closing one of the switches connecting the
string to the amplifier. Because it is a string of
resistors, it is specified monotonic. The DAC7552
architecture uses two separate resistor strings to
minimize channel-to-channel crosstalk.
ure 29 ). This forms a gain-of-two, noninverting ampli-
fier configuration. Overall gain remains one because
the resistor string has a divide-by-two configuration.
The resistance seen at each VFBx pin is approximately 200 k Ω to ground.
Power-On Reset
On power up, all internal registers are cleared and all
channels are updated with zero-scale voltages. Until
valid data is written, all DAC outputs remain in this
state. This is particularly useful in applications where
it is important to know the state of the DAC outputs
while the device is powering up. In order not to turn
on ESD protection devices, V
before any other pin is brought high.
. It is capable of driving a
DD
should be applied
DD
15
www.ti.com
DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
Power Down
The DAC7552 has a flexible power-down capability
as described in Table 2 . Individual channels could be
powered down separately or all channels could be
powered down simultaneously. During a power-down
condition, the user has flexibility to select the output
impedance of each channel. During power-down
operation, each channel can have either 1-k Ω ,
100-k Ω , or Hi-Z output impedance to ground.
register, DAC register, or both are updated with shift
register input data. Bit 13 (DB13) determines whether
the data is for DAC A, DAC B, or both DACs. Bit 12
(DB12) determines either normal mode or
power-down mode (see Table 2 ). All channels are
updated when bits 15 and 14 (DB15 and DB14) are
high.
The SYNC input is a level-triggered input that acts as
a frame synchronization signal and chip enable. Data
can only be transferred into the device while SYNC is
Asynchronous Clear
The DAC7552 output is asynchronously set to
zero-scale voltage immediately after the CLR pin is
brought low. The CLR signal resets all internal
registers and therefore behaves like the Power-On
Reset. The DAC7552 updates at the first rising edge
of the SYNC signal that occurs after the CLR pin is
brought back to high.
IOVDD and Level Shifters
The DAC7552 can be used with different logic families that require a wide range of supply voltages (from
low. To start the serial data transfer, SYNC should be
taken low, observing the minimum SYNC to SCLK
falling edge setup time, t4. After SYNC goes low,
serial data is shifted into the device's input shift
register on the falling edges of SCLK for 16 clock
pulses.
When DCEN is low, SDO pin is brought to a Hi-Z
state. The first 16 data bits that follow the falling edge
of SYNC are stored in the shift register. The rising
edge of SYNC that follows the 16
th
data bit updates
the DAC(s). If SYNC is brought high before the 16
data bit, no action occurs.
1.8 V to 5.5 V). To enable this useful feature, the When DCEN is high, data can continuously be shifted
IOVDD pin must be connected to the logic supply into the shift register, enabling the daisy-chain opervoltage of the system. All DAC7552 digital input and ation. SDO pin becomes active and outputs SDIN
output pins are equipped with level-shifter circuits. data with 16 clock cycle delay. A rising edge of SYNC
Level shifters at the input pins ensure that external loads the shift register data into the DAC(s). The
logic high voltages are translated to the internal logic loaded data consists of the last 16 data bits received
high voltage, with no additional power dissipation. into the shift register before the rising edge of SYNC.
Similarly, the level shifter for the SDO pin translates
the internal logic high voltage (AVDD) to the external
logic high level (IOVDD). For single-supply operation,
the IOVDD pin can be tied to the AVDD pin.
SERIAL INTERFACE
The DAC7552 is controlled over a versatile 3-wire
serial interface, which operates at clock rates up to
If daisy-chain operation is not needed, DCEN should
permanently be tied to a logic low voltage.
Daisy-Chain Operation
When DCEN pin is brought high, daisy chaining is
enabled. Serial Data Output (SDO) pin is provided to
daisy-chain multiple DAC7552 devices in a system.
50 MHz and is compatible with SPI, QSPI, Microwire, As long as SYNC is high or DCEN is low, the SDO
and DSP interface standards. pin is in a high-impedance state. When SYNC is
In daisy-chain mode (DCEN = 1), the DAC7552
requires a falling SCLK edge after the rising SYNC, in
order to initialize the serial interface for the next
update.
16-Bit Word and Input Shift Register
The input shift register is 16 bits wide. DAC data is
loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK, as shown in the
Figure 1 timing diagram. The 16-bit word, illustrated
in Table 1 , consists of four control bits followed by 12
bits of DAC data. The data format is straight binary
with all zeroes corresponding to 0-V output and all
ones corresponding to full-scale output (V
REF
– 1
brought low the output of the internal shift register is
tied to the SDO pin. As long as SYNC is low and
DCEN is high, SDO duplicates SDIN signal with a
16-cycle delay. To support multiple devices in a daisy
chain, SCLK and SYNC signals are shared across all
devices, and SDO of one DAC7552 should be tied to
the SDIN of the next DAC7552. For n devices in such
a daisy chain, 16 n SCLK cycles are required to shift
the entire input data stream. After 16 n SCLK falling
edges are received, following a falling SYNC, the
data stream becomes complete and SYNC can be
brought high to update n devices simultaneously.
SDO operation is specified at a maximum SCLK
speed of 10 MHz.
LSB). Data is loaded MSB first (bit 15) where the first
two bits (DB15 and DB14) determine if the input
th
16
www.ti.com
DAC7552
V
REF
H
DAC7552
_
+
V
dac
R2
R1
REF3140
V
REF
V
tail
V
OUT
OPA130
V
out
V
REF
R2
R1
1
Din
4096
V
tail
R2
R1
DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
INTEGRAL AND DIFFERENTIAL LINEARITY
The DAC7552 uses precision thin-film resistors providing exceptional linearity and monotonicity. Integral
linearity error is typically within (+/-) 0.35 LSBs, and
differential linearity error is typically within (+/-) 0.08
LSBs.
GLITCH ENERGY
The DAC7552 uses a proprietary architecture that
minimizes glitch energy. The code-to-code glitches
are so low, they are usually buried within the
wide-band noise and cannot be easily detected. The
DAC7552 glitch is typically well under 0.1 nV-s. Such
low glitch energy provides more than 10X improvement over industry alternatives.
CHANNEL-TO-CHANNEL CROSSTALK
The DAC7552 architecture is designed to minimize
channel-to-channel crosstalk. The voltage change in
one channel does not affect the voltage output in
another channel. The DC crosstalk is in the order of a
few microvolts. AC crosstalk is also less than –100
dBs. This provides orders of magnitude improvement
over certain competing architectures.
APPLICATION INFORMATION
Waveform Generation
Due to its exceptional linearity, low glitch, and low
crosstalk, the DAC7552 is well suited for waveform
generation (from DC to 10 kHz). The DAC7552
large-signal settling time is 5 µs, supporting an
update rate of 200 KSPS. However, the update rates
can exceed 1 MSPS if the waveform to be generated
consists of small voltage steps between consecutive
DAC updates. To obtain a high dynamic range,
REF3140 (4.096 V) or REF02 (5 V) are recommended for reference voltage generation.
change the loop can generate. A DNL error less than
–1 LSB (non-monotonicity) can create loop instability.
A DNL error greater than +1 LSB implies unnecessarily large voltage steps and missed voltage targets.
With high DNL errors, the loop loses its stability,
resolution, and accuracy. Offering 12-bit ensured
monotonicity and ± 0.08 LSB typical DNL error, 755X
DACs are great choices for precision control loops.
Loop Speed:
Many factors determine control loop speed. Typically,
the ADC's conversion time and the MCU's computation time are the two major factors that dominate
the time constant of the loop. DAC settling time is
rarely a dominant factor because ADC conversion
times usually exceed DAC conversion times. DAC
offset, gain, and linearity errors can slow the loop
down only during the start-up. Once the loop reaches
its steady-state operation, these errors do not affect
loop speed any further. Depending on the ringing
characteristics of the loop's transfer function, DAC
glitches can also slow the loop down. With its 1
MSPS (small-signal) maximum data update rate,
DAC7552 can support high-speed control loops.
Ultralow glitch energy of the DAC7552 significantly
improves loop stability and loop settling time.
Generating Industrial Voltage Ranges:
For control loop applications, DAC gain and offset
errors are not important parameters. This could be
exploited to lower trim and calibration costs in a
high-voltage control circuit design. Using an operational amplifier (OPA130), and a voltage reference
(REF3140), the DAC7552 can generate the wide
voltage swings required by the control loop.
Generating ±5-V, ±10-V, and ± 12-V Outputs For
Precision Industrial Control
Industrial control applications can require multiple
feedback loops consisting of sensors, ADCs, MCUs,
DACs, and actuators. Loop accuracy and loop speed
are the two important parameters of such control
loops.
Loop Accuracy:
In a control loop, the ADC has to be accurate. Offset,
gain, and the integral linearity errors of the DAC are
not factors in determining the accuracy of the loop.
As long as a voltage exists in the transfer curve of a
monotonic DAC, the loop can find it and settle to it.
On the other hand, DAC resolution and differential
linearity do determine the loop accuracy, because
each DAC step determines the minimum incremental
Figure 31. Low-cost, Wide-swing Voltage Gener-
ator for Control Loop Applications
The output voltage of the configuration is given by:
(1)
Fixed R1 and R2 resistors can be used to coarsely
set the gain required in the first term of the equation.
Once R2 and R1 set the gain to include some
minimal over-range, a DAC7552 channel could be
used to set the required offset voltage. Residual
17
www.ti.com
DAC7552
SLAS442B – JANUARY 2005 – REVISED JUNE 2005
errors are not an issue for loop accuracy because For ±10-V operation: R1=10 k Ω, R2 = 39 k Ω, V
offset and gain errors could be tolerated. One 2.56 V, V
DAC7552 channel can provide the Vtail voltage, while
the other DAC7552 channel can provide Vdac voltage
to help generate the high-voltage outputs.
For ±5-V operation: R1=10 k Ω, R2 = 15 k Ω, V
3.33 V, V
REF
= 4.096 V
=
tail
For ±12-V operation: R1=10 k Ω, R2 = 49 k Ω, V
2.45 V, V
REF
REF
= 4.096 V
= 4.096 V
=
tail
=
tail
18
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jul-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
DAC7552IRGT PREVIEW QFN RGT 16 121 TBD Call TI Call TI
DAC7552IRGTR ACTIVE QFN RGT 16 3000 TBD CU NIPDAU Level-3-220C-168 HR
DAC7552IRGTT ACTIVE QFN RGT 16 250 TBD CU NIPDAU Level-3-220C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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