TEXAS INSTRUMENTS DAC7552 Technical data

3 mm x 3 mm

Actual Size

www.ti.com

_

+

Interface

Logic

Input

Register

DAC

Register

String
DAC A

Power-Down

Logic

Power-On

Reset

V

DD

IOV

DD

V

REFA

V

FBA

V

OUT

A

V

REFB

GND

CLR

DCEN

SDIN

SYNC

SCLK

_
+

Input

Register

DAC

Register

String
DAC B

V

FBB

V

OUT

B

PD

SDO

FUNCTIONAL BLOCK DIAGRAM

DAC7552

查询DAC7552供应商

SLAS442B – JANUARY 2005 – REVISED JUNE 2005

12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT

DIGITAL-TO-ANALOG CONVERTER

FEATURES DESCRIPTION

• 2.7-V to 5.5-V Single Supply

• 12-Bit Linearity and Monotonicity

• Rail-to-Rail Voltage Output

• Settling Time: 5 µs (Max)

• Ultralow Glitch Energy: 0.1 nVs DAC7552 operates from a single 2.7-V to 5.5-V

• Ultralow Crosstalk: –100 dB

• Low Power: 440 µA (Max)

• Per-Channel Power Down: 2 µA (Max)

• Power-On Reset to Zero Scale

• SPI-Compatible Serial Interface: Up to 50 MHz to 50 MHz and is compatible with SPI, QSPI,

• Daisy-Chain Capability

• Asynchronous Hardware Clear

• Simultaneous or Sequential Update

• Specified Temperature Range: –40°C to 105°C

• Small 3-mm × 3-mm, 16-Lead QFN Package

APPLICATIONS

• Portable Battery-Powered Instruments

• Digital Gain and Offset Adjustment

• Programmable Voltage and Current Sources

• Programmable Attenuators

• Industrial Process Control

The DAC7552 is a 12-bit, dual-channel, volt­age-output DAC with exceptional linearity and
monotonicity. Its proprietary architecture minimizes
undesired transients such as code-to-code glitch and
channel-to-channel crosstalk. The low-power

supply. The DAC7552 output amplifiers can drive a
2-k Ω , 200-pF load rail-to-rail with 5-µs settling time;
the output range is set using an external voltage
reference.

The 3-wire serial interface operates at clock rates up
Microwire™, and DSP interface standards. The out-

puts of all DACs may be updated simultaneously or
sequentially. The parts incorporate a power-on-reset
circuit to ensure that the DAC outputs power up to
zero volts and remain there until a valid write cycle to
the device takes place. The parts contain a
power-down feature that reduces the current con­sumption of the device to under 2 µA.

The small size and low-power operation makes the
DAC7552 ideally suited for battery-operated portable
applications. The power consumption is typically

1.5 mW at 5 V, 0.75 mW at 3 V, and reduces to 1 µW
in power-down mode.

The DAC7552 is available in a 16-lead QFN package
and is specified over –40°C to 105°C.

DAC7552

Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2005, Texas Instruments Incorporated

www.ti.com

DAC7552

SLAS442B – JANUARY 2005 – REVISED JUNE 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

ORDERING INFORMATION

PRODUCT PACKAGE TEMPERATURE

DAC7552 16 QFN RGT –40 °C TO 105 °C D752

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com .

PACKAGE PACKAGE ORDERING TRANSPORT

DESIGNATOR MARKING NUMBER MEDIA

SPECIFIED

RANGE

(1)

DAC7552IRGTT 250-piece Tape and Reel
DAC7552IRGTR 3000-piece Tape and Reel

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V

to GND –0.3 V to 6 V

DD

Digital input voltage to GND –0.3 V to V
V

to GND –0.3 V to VDD+ 0.3 V

OUT

Operating temperature range –40°C to 105°C
Storage temperature range –65°C to 150°C
Junction temperature (TJMax) 150°C

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

(1)

UNIT

+ 0.3 V

DD

2

www.ti.com

DAC7552

SLAS442B – JANUARY 2005 – REVISED JUNE 2005

ELECTRICAL CHARACTERISTICS

V

= 2.7 V to 5.5 V, V

DD

specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution 12 Bits
Relative accuracy ±0.35 ±1 LSB
Differential nonlinearity Specified monotonic by design ±0.08 ±0.5 LSB
Offset error ±12 mV
Zero-scale error All zeroes loaded to DAC register ±12 mV
Gain error ±0.15 %FSR
Full-scale error ±0.5 %FSR
Zero-scale error drift 7 µV/ °C
Gain temperature coefficient 3 ppm of FSR/ °C
PSRR V

OUTPUT CHARACTERISTICS

Output voltage range 0 VREF V
Output voltage settling time RL= 2 k Ω; 0 pF < CL< 200 pF 5 µs
Slew rate 1.8 V/ µs
Capacitive load stability RL= ∞ 470

Digital-to-analog glitch impulse 1 LSB change around major carry 0.1 nV-s
Channel-to-channel crosstalk 1-kHz full-scale sine wave, –100 dB

Digital feedthrough 0.1 nV-s
Output noise density (10-kHz offset fre- 120 nV/rtHz

quency)
Total harmonic distortion F

DC output impedance 1 Ω
Short-circuit current V

Power-up time Coming out of power-down mode, 15

REFERENCE INPUT

VREF Input range 0 V
Reference input impedance V

Reference current µA

LOGIC INPUTS

Input current ±1 µA
V

, Input low voltage IOV

IN_L

V

, Input high voltage IOV

IN_H

Pin capacitance 3 pF

(1) Linearity tested using a reduced code range of 30 to 4065; output unloaded.
(2) Specified by design and characterization, not production tested. For 1.8 V < IOV

VIH= IOV

(2)

, VIL= GND.

DD

= V

REF

(1)

, RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications –40°C to 105°C, unless otherwise

DD

= 5 V 0.75 mV/V

(2)

DD

RL= 2 k Ω 1000

pF

outputs unloaded

= 1 kHz, FS= 1 MSPS, –85 dB

OUT

BW = 20 kHz

= 5 V 50

DD

V

= 3 V 20

DD

V

= 5 V

DD

Coming out of power-down mode, 15
V

= 3 V

DD

A and V

REF

V

A = V

REF

V

A and V

REF

V

A = V

REF

V

A and V

REF

≥ 2.7 V 0.3 IOV

DD

≥ 2.7 V 0.7 IOV

DD

B shorted together 50 k Ω

REF

B = V

REF

REF

B = V

REF

REF

= 5 V, 100 250

DD

B shorted together

= 3 V, 60 123

DD

B shorted together

DD

< 2.7 V, It is recommended that

DD

DD

DD

mA

µs

V

V
V

3

www.ti.com

DAC7552

SLAS442B – JANUARY 2005 – REVISED JUNE 2005

ELECTRICAL CHARACTERISTICS (continued)

V

= 2.7 V to 5.5 V, V

DD

specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

POWER REQUIREMENTS

V

DD,

IDD(normal operation) DAC active and excluding load current

IDD(all power-down modes)

POWER EFFICIENCY

I

OUT

(3) IOV

(3)

, IOV

DD

V

= 3.6 V to 5.5 V 300 440

DD

V

= 2.7 V to 3.6 V 250 400

DD

V

= 3.6 V to 5.5 V 0.2 2

DD

V

= 2.7 V to 3.6 V 0.05 2

DD

/I

DD

operates down to 1.8 V with slightly degraded timing, as long as VIH= IOV

DD

= V

REF

, RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications –40°C to 105°C, unless otherwise

DD

VIH= IOV

VIH= IOV

I

LOAD

and VIL= GND µA

DD

and VIL= GND µA

DD

= 2 mA, V

= 5 V 93%

DD

2.7 5.5 V

and VIL= GND.

DD

4

www.ti.com

SCLK

SYNC

SDIN

D15 D14 D13

D12

D11 D1 D0 D15

t

8

t

4

t

3

t

2

t

1

t

7

t

6

t

5

D0

t

9

Input Word n Input Word n+1

Undefined

D15 D14

D0

Input Word n

t

10

SDO

CLR

SLAS442B – JANUARY 2005 – REVISED JUNE 2005

TIMING CHARACTERISTICS

V

= 2.7 V to 5.5 V, RL= 2 k Ω to GND; all specifications –40°C to 105°C, unless otherwise specified

DD

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

V

= 2.7 V to 3.6 V 20

(3)

t

SCLK cycle time ns

1

t

SCLK HIGH time ns

2

t

SCLK LOW time ns

3

SYNC falling edge to SCLK falling edge setup

t

4

time

t

Data setup time ns

5

t

Data hold time ns

6

t

SCLK falling edge to SYNC rising edge ns

7

t

Minimum SYNC HIGH time ns

8

t

SCLK falling edge to SDO valid ns

9

t

CLR pulse width low ns

10

DD

V

= 3.6 V to 5.5 V 20

DD

V

= 2.7 V to 3.6 V 10

DD

V

= 3.6 V to 5.5 V 10

DD

V

= 2.7 V to 3.6 V 10

DD

V

= 3.6 V to 5.5 V 10

DD

V

= 2.7 V to 3.6 V 4

DD

V

= 3.6 V to 5.5 V 4

DD

V

= 2.7 V to 3.6 V 5

DD

V

= 3.6 V to 5.5 V 5

DD

V

= 2.7 V to 3.6 V 4.5

DD

V

= 3.6 V to 5.5 V 4.5

DD

V

= 2.7 V to 3.6 V 0

DD

V

= 3.6 V to 5.5 V 0

DD

V

= 2.7 V to 3.6 V 20

DD

V

= 3.6 V to 5.5 V 20

DD

V

= 2.7 V to 3.6 V 10

DD

V

= 3.6 V to 5.5 V 10

DD

V

= 2.7 V to 3.6 V 10

DD

V

= 3.6 V to 5.5 V 10

DD

(1) All input signals are specified with tR= tF= 1 ns (10% to 90% of VDD) and timed from a voltage level of (V
(2) See Serial Write Operation timing diagram Figure 1 .
(3) Maximum SCLK frequency is 50 MHz at V

= 2.7 V to 5.5 V.

DD

DAC7552

ns

+ VIH)/2.

IL

Figure 1. Serial Write Operation

5

www.ti.com

1
2
3
4

12

11

10

9

SCLK
SYNC
IOV

DD

SDO

V

OUT

A

V

DD

GND

V

OUT

B

VFBA

VREFA

PD

DCEN

CLR

SDIN

VFBB

VREFB

16 15 14 13

5 6 7 8

DAC7552

SLAS442B – JANUARY 2005 – REVISED JUNE 2005

PIN DESCRIPTION

RGT PACKAGE

(TOP VIEW)

Terminal Functions

TERMINAL DESCRIPTION

NO. NAME

1 V
2 V
3 GND Ground
4 V
5 VFBB DAC B amplifier sense input. (For voltage output operation, connect to VOUTB externally.)
6 VREFB Positive reference voltage input for DAC B
7 PD Power-down
8 DCEN Daisy-chain enable

9 SDO Serial data output
10 IOVDD I/O voltage supply input. (For single supply operation, connect to VDD externally.)
11 SYNC Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out

12 SCLK Serial clock input
13 SDIN Serial data input
14 CLR Asynchronous input to clear the DAC registers. When CLR is low, the DAC registers are set to 000H and the output

15 VREFA Positive reference voltage input for DAC A
16 VFBA DAC A amplifier sense input. (For voltage output operation, connect to VOUTA externally.)

A Analog output voltage from DAC A

OUT
DD

OUT

Analog voltage supply input

B Analog output voltage from DAC B

to the DAC7552

voltage to 0 V.

6

www.ti.com

−1

−0.5

0

0.5

1

Linearity Error − LSB

−0.5

−0.25

0

0.25

0.5

0 512 1024 1536 2048 2560 3072 3584 4096

Digital Input Code

Differential Linearity Error − LSB

Channel A V

REF

= 4.096 V VDD = 5 V

Channel B V

REF

= 4.096 V VDD = 5 V

Linearity Error − LSB

Digital Input Code

Differential Linearity Error − LSB

−1

−0.5

0

0.5

1

−0.5

−0.25

0

0.25

0.5

0

512 1024 1536

2048 2560 3072 3584 4096

Linearity Error − LSB

Digital Input Code

Differential Linearity Error − LSB

−1

−0.5

0

0.5

1

−0.5

−0.25

0

0.25

0.5

0 512 1024 1536 2048 2560 3072 3584 4096

Channel A V

REF

= 2.5 V VDD = 2.7 V

−1

−0.5

0

0.5

1

−0.5

−0.25

0

0.25

0.5

0 512 1024 1536 2048 2560 3072 3584 4096

Channel B V

REF

= 2.5 V VDD = 2.7 V

Linearity Error − LSB

Digital Input Code

Differential Linearity Error − LSB

SLAS442B – JANUARY 2005 – REVISED JUNE 2005

TYPICAL CHARACTERISTICS

LINEARITY ERROR AND LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs vs

DIGITAL INPUT CODE DIGITAL INPUT CODE

DAC7552

Figure 2. Figure 3.

LINEARITY ERROR AND LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs vs

DIGITAL INPUT CODE DIGITAL INPUT CODE

Figure 4. Figure 5.

7