DAC7512
DAC7512
DAC7512
SBAS156B – JULY 2002
Low-Power, Rail-to-Rail Output, 12-Bit Serial Input
DIGITAL-TO-ANALOG CONVERTER
FEATURES
● microPOWER OPERATION:
● POWER-DOWN: 200nA at 5V, 50nA at 3V
● POWER SUPPLY: +2.7V to +5.5V
●
TESTED MONOTONIC BY DESIGN
● POWER-ON RESET TO 0V
● THREE POWER-DOWN FUNCTIONS
● LOW POWER SERIAL INTERFACE WITH
SCHMITT-TRIGGERED INPUTS
● ON-CHIP OUTPUT BUFFER AMPLIFIER,
RAIL-TO-RAIL OPERATION
● SYNC INTERRUPT FACILITY
● SOT23-6 AND MSOP-8 PACKAGES
135µA at 5V
APPLICATIONS
● PORTABLE BATTERY-POWERED
INSTRUMENTS
● DIGITAL GAIN AND OFFSET
ADJUSTMENT
● PROGRAMMABLE VOLTAGE AND
CURRENT SOURCES
DESCRIPTION
The DAC7512 is a low-power, single, 12-bit buffered voltage
output Digital-to-Analog Converter (DAC). Its on-chip precision output amplifier allows rail-to-rail output swing to be
achieved. The DAC7512 uses a versatile three-wire serial
interface that operates at clock rates up to 30MHz and is
compatible with standard SPI
DSP interfaces.
The reference for the DAC7512 is derived from the power
supply, resulting in the widest dynamic output range possible.
The DAC7512 incorporates a power-on reset circuit that
ensures that the DAC output powers up at 0V and remains
there until a valid write takes place in the device. The
DAC7512 contains a power-down feature, accessed over the
serial interface, that can reduce the current consumption of
the device to 50nA at 5V.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment. The power consumption is 0.7mW at 5V reducing to
1µW in power-down mode.
The DAC7512 is available in a SOT23-6 package and an
MSOP-8 package.
SPI and QSPI are registered trademarks of Motorola.
Microwire is a registered trademark of National Semiconductor.
™
, QSPI™, Microwire™, and
SYNC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Power-On
Reset
DAC
Register
Input
Control
Logic
SCLK D
V
GND
DD
REF (+) REF (–)
12-Bit
DAC
Power-Down
Control Logic
IN
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Output
Buffer
V
OUT
Resistor
Network
Copyright © 2002, Texas Instruments Incorporated
ABSOLUTE MAXIMUM RATINGS
V
to GND ........................................................................... –0.3V to +6V
DD
Digital Input Voltage to GND .................................. –0.3V to +VDD + 0.3V
V
to GND ........................................................... –0.3V to +VDD + 0.3V
OUT
Operating Temperature Range ..................................... –40°C to +105°C
Storage Temperature Range ......................................... –65°C to +150°C
Junction Temperature Range (TJ max) ......................................... +150°C
SOT23 Package:
Power Dissipation .................................................. (TJ max — TA)/
Thermal Impedance .........................................................240°C/W
JA
Lead Temperature, Soldering:
Vapor Phase (60s) ............................................................... +215°C
Infrared (15s) ........................................................................ +220°C
MSOP Package:
Power Dissipation ........................................................ (T
Thermal Impedance .........................................................206°C/W
JA
Thermal Impedance ........................................................... 44°C/W
JC
Lead Temperature, Soldering:
Vapor Phase (60s) ............................................................... +215°C
Infrared (15s) ........................................................................ +220°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
max — TA)/
J
JA
JA
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE DIFFERENTIAL SPECIFIED
PRODUCT (LSB) (LSB) PACKAGE-LEAD DESIGNATOR
ACCURACY NONLINEARITY PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
DAC7512E ±8 ±1 MSOP-8 DGK –40°C to +105°C D12E DAC7512E/250 Tape and Reel, 250
"" " " " " "
DAC7512N ±8 ±1 SOT23-6 DBV –40°C to +105°C D12N DAC7512N/250 Tape and Reel, 250
"" " " " " "
NOTES: (1) For the most current specifications and package information, refer to our web site at www.ti.com. (2) Models with a slash (/) are available only in Tape
and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7512E/2K5” will get a single 2500-piece Tape and Reel.
(1)
RANGE MARKING NUMBER
(1)
MEDIA, QUANTITY
DAC7512E/2K5 Tape and Reel, 2500
DAC7512N/3K Tape and Reel, 3000
PIN CONFIGURATIONS
Top View SOT23-6
1
V
OUT
2
GND
V
DD
V
NC
NC
V
OUT
DD
DAC7512
3
MSOP-8
1
2
DAC7512
3
4
NC = No Internal Connection
DAC7512N LOT TRACE LOCATION
Top View
D12N
PIN DESCRIPTION (SOT23-6)
PIN NAME DESCRIPTION
6
SYNC
5
SCLK
4
D
IN
8
GND
7
D
IN
6
SCLK
5
SYNC
Pin 1
1V
2 GND Ground reference point for all circuitry on the part.
3VDDPower Supply Input, +2.7V to 5.5V.
4DINSerial Data Input. Data is clocked into the 16-bit
5 SCLK Serial Clock Input. Data can be transferred at rates
6 SYNC Level triggered control input (active LOW). This is
Bottom View
OUT
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
input shift register on the falling edge of the serial
clock input.
up to 30MHz.
the frame sychronization signal for the input data.
When SYNC goes LOW, it enables the input shift
register and data is transferred in on the falling
edges of the following clocks. The DAC is updated
following the 16th clock cycle unless SYNC is taken
HIGH before this edge, in which case the rising
edge of SYNC acts as an interrupt and the write
sequence is ignored by the DAC7512.
YMLL
Pin 1
2
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Lot Trace Code
DAC7512
SBAS156B
ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.5V; RL = 2ký to GND; CL = 200pF to GND.
DAC7512E, N
PARAMETER CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution 12 Bits
Relative Accuracy ±8 LSB
Differential Nonlinearity Tested Monotonic by Design ±1 LSB
Zero Code Error All Zeroes Loaded to DAC Register +5 +20 mV
Full-Scale Error All Ones Loaded to DAC Register –0.15 –1.25 % of FSR
Gain Error ±1.25 % of FSR
Zero Code Error Drift –20 µV/°C
Gain Temperature Coefficient –5 ppm of FSR/°C
OUTPUT CHARACTERISTICS
Output Voltage Range 0V
Output Voltage Settling Time 1/4 Scale to 3/4 Scale Change
Slew Rate 1 V/µs
(1)
(2)
DD
(400
to C00H)810µs
R
L
H
= 2kΩ; 0pF < CL < 200pF
R
= 2kΩ; CL = 500pF 12 µs
L
V
Capacitive Load Stability R
Code Change Glitch Impulse 1LSB Change Around Major Carry 20 nV-s
= × 470 pF
L
R
= 2kΩ 1000 pF
L
Digital Feedthrough 0.5 nV-s
DC Output Impedance 1 Ω
Short-Circuit Current V
Power-Up Time Coming Out of Power-Down Mode
Coming Out of Power-Down Mode
LOGIC INPUTS
(2)
= +5V 50 mA
DD
V
= +3V 20 mA
DD
V
= +5V 2.5 µs
DD
V
= +3V 5 µs
DD
Input Current ±1 µA
V
L, Input Low Voltage VDD = +5V 0.8 V
IN
V
L, Input Low Voltage VDD = +3V 0.6 V
IN
V
H, Input High Voltage VDD = +5V 2.4 V
IN
V
H, Input High Voltage VDD = +3V 2.1 V
IN
Pin Capacitance 3pF
POWER REQUIREMENTS
V
DD
I
(normal mode)
DD
VDD = +3.6V to +5.5V VIH = VDD and VIL = GND 135 200 µA
V
= +2.7V to +3.6V VIH = VDD and VIL = GND 115 160 µA
DD
I
(all power-down modes)
DD
V
= +3.6V to +5.5V VIH = VDD and VIL = GND 0.2 1 µ A
DD
V
= +2.7V to +3.6V VIH = VDD and VIL = GND 0.05 1 µA
DD
DAC Active and Excluding Load Current
2.7 5.5 V
POWER EFFICIENCY
I
OUT/IDD
I
= 2mA. VDD = +5V 93 %
LOAD
TEMPERATURE RANGE
Specified Performance –40 +105 °C
NOTES: (1) Linearity calculated using a reduced code range of 48 to 4047; output unloaded. (2) Guaranteed by design and characterization, not production tested.
DAC7512
SBAS156B
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3
TIMING CHARACTERISTICS
(1, 2)
VDD = +2.7V to +5.5V; all specifications –40°C to +105°C, unless otherwise noted.
DAC7512E, N
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNITS
(3)
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
NOTES: (1) All input signals are specified with t
diagram, below. (3) Maximum SCLK frequency is 30MHz at V
SCLK Cycle Time
SCLK HIGH Time
SCLK LOW Time
SYNC to SCLK Rising
Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to
SYNC Rising Edge
Minimum SYNC HIGH Time
V
= 2.7V to 3.6V 50 ns
DD
V
= 3.6V to 5.5V 33 ns
DD
V
= 2.7V to 3.6V 13 ns
DD
V
= 3.6V to 5.5V 13 ns
DD
V
= 2.7V to 3.6V 22.5 ns
DD
V
= 3.6V to 5.5V 13 ns
DD
V
= 2.7V to 3.6V 0 ns
DD
V
= 3.6V to 5.5V 0 ns
DD
V
= 2.7V to 3.6V 5 ns
DD
V
= 3.6V to 5.5V 5 ns
DD
V
= 2.7V to 3.6V 4.5 ns
DD
V
= 3.6V to 5.5V 4.5 ns
DD
V
= 2.7V to 3.6V 0 ns
DD
V
= 3.6V to 5.5V 0 ns
DD
V
= 2.7V to 3.6V 50 ns
DD
V
= 3.6V to 5.5V 33 ns
DD
= tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timing
R
= +3.6V to +5.5V and 20MHz at VDD = +2.7V to +3.6V.
DD
SERIAL WRITE OPERATION
SCLK
t
SYNC
D
8
IN
t
4
DB15 DB0
t
1
t
t
3
t
6
t
5
2
t
7
4
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DAC7512
SBAS156B
TYPICAL CHARACTERISTICS: VDD = +5V
FULL-SCALE ERROR vs TEMPERATURE
–40
Error (mV)
Temperature (°C)
0 40 80 120
30
20
10
0
–10
–20
–30
TYPICAL TOTAL UNADJUSTED ERROR
0
TUE (LSBs)
CODE
200
H
400H600H800HA00HC00HE00HFFF
H
16
8
0
–8
–16
At TA = +25°C, +VDD = +5V, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR vs CODE
16.0
12.0
8.0
4.0
0.0
–4.0
LE (LSB)
–8.0
–12.0
–16.0
1.0
0.5
0.0
DLE (LSB)
–0.5
–1.0
0 200H400H600H800
DIFFERENTIAL LINEARITY ERROR vs CODE
16.0
12.0
8.0
4.0
0.0
–4.0
LE (LSB)
–8.0
–12.0
–16.0
1.0
0.5
0.0
DLE (LSB)
–0.5
–1.0
0 200H400H600H800
LINEARITY ERROR AND
(–40°C)
A00
H
H
CODE
LINEARITY ERROR AND
(+105°C)
A00
H
H
CODE
C00HE00HFFF
C00HE00HFFF
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
(+25°C)
16.0
12.0
8.0
4.0
0.0
–4.0
LE (LSB)
–8.0
–12.0
–16.0
1.0
0.5
0.0
DLE (LSB)
–0.5
–1.0
H
0 200H400H600H800
A00
H
C00HE00HFFF
H
H
CODE
H
30
ZERO-SCALE ERROR vs TEMPERATURE
20
10
0
Error (mV)
–10
–20
–30
–40
0 40 80 120
DAC7512
SBAS156B
Temperature (°C)
www.ti.com
5
TYPICAL CHARACTERISTICS: VDD = +5V (Cont.)
At TA = +25°C, +VDD = +5V, unless otherwise noted.
3000
2500
2000
1500
Frequency
1000
500
0
500
400
300
(µA)
DD
I
200
100
5060708090
SUPPLY CURRENT vs CODE
IDD HISTOGRAM
100
110
120
130
IDD (µA)
140
150
160
170
180
190
(V)
V
(µA)
I
OUT
DD
300
250
200
150
100
5
SOURCE AND SINK CURRENT CAPABILITY
4
DAC Loaded with FFF
H
3
2
1
DAC Loaded with 000
H
0
0
51015
I
SOURCE/SINK
(mA)
SUPPLY CURRENT vs TEMPERATURE
50
300
0
0
200
400H600H800HA00HC00HE00HFFF
H
H
CODE
SUPPLY CURRENT vs SUPPLY VOLTAGE
0
–40
0 40 80 120
Temperature (°C)
POWER-DOWN CURRENT vs SUPPLY VOLTAGE
100
90
250
200
150
(µA)
DD
I
100
50
0
2.7
3.2 3.7 4.2 4.7 5.2 5.7
V
(V)
DD
(nA)
DD
I
80
70
60
+105°C
50
40
–40°C
30
20
10
+25°C
0
2.7
3.2 3.7 4.2 4.7 5.2 5.7
VDD (V)
6
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DAC7512
SBAS156B
TYPICAL CHARACTERISTICS: VDD = +5V (Cont.)
POWER-ON RESET TO 0V
Time (20µs/div)
Loaded with 2kΩ to V
DD
.
VDD (1V/div)
V
OUT
(1V/div)
HALF-SCALE SETTLING TIME
Time (1µs/div)
CLK (5V/div)
V
OUT
(1V/div)
Half-Scale Code Change
400
H
to C00
H
Output Loaded with
2kΩ and 200pF to GND
FULL-SCALE SETTLING TIME
CLK (5V/div)
V
OUT
(1V/div)
Time (1µs/div)
Full-Scale Code Change
000
H
to FFF
H
Output Loaded with
2kΩ and 200pF to GND
At TA = +25°C, +VDD = +5V, unless otherwise noted.
(µA)
I
DD
2500
2000
1500
1000
500
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
0
0
12345
V
(V)
LOGIC
FULL-SCALE SETTLING TIME
CLK (5V/div)
Full-Scale Code Change
FFF
to 000
H
Output Loaded with
2kΩ and 200pF to GND
H
V
(1V/div)
OUT
Time (1µs/div)
HALF-SCALE SETTLING TIME
CLK (5V/div)
Half-Scale Code Change
C00
to 400
H
Output Loaded with
H
2kΩ and 200pF to GND
V
(1V/div)
OUT
Time (1µs/div)
DAC7512
SBAS156B
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7
TYPICAL CHARACTERISTICS: VDD = +5V (Cont.)
At TA = +25°C, +VDD = +5V, unless otherwise noted.
EXITING POWER-DOWN
(800
Loaded)
H
CLK (5V/div)
(20mV/div)
OUT
V
(1V/div)
OUT
V
CODE CHANGE GLITCH
Loaded with 2kΩ
and 200pF to GND.
Code Change:
800
to 7FFH.
H
Time (5µs/div)
TYPICAL CHARACTERISTICS: VDD = +2.7V
At TA = +25°C, +VDD = +2.7V, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR vs CODE
16.0
12.0
8.0
4.0
0.0
–4.0
LE (LSB)
–8.0
–12.0
–16.0
1.0
0.5
0.0
DLE (LSB)
–0.5
–1.0
0 200H400H600H800
LINEARITY ERROR AND
(–40°C)
A00
H
H
CODE
C00HE00HFFF
16.0
12.0
8.0
4.0
0.0
–4.0
LE (LSB)
–8.0
–12.0
–16.0
1.0
0.5
0.0
DLE (LSB)
–0.5
–1.0
H
0 200H400H600H800
Time (0.5µs/div)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(+25°C)
A00
H
C00HE00HFFF
H
CODE
H
LE (LSB)
DLE (LSB)
8
DIFFERENTIAL LINEARITY ERROR vs CODE
LINEARITY ERROR AND
16
12
8
4
0
–4
–8
–12
–16
1.0
0.5
0
–0.5
–1.0
000H200H400H600H800
(+105°C)
H
CODE
A00
C00HE00HFFF
H
H
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16
8
0
TUE (LSBs)
–8
–16
0
TYPICAL TOTAL UNADJUSTED ERROR
400H600H800HA00HC00HE00HFFF
200
H
CODE
H
DAC7512
SBAS156B
TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.)
FULL-SCALE ERROR vs TEMPERATURE
–40
Error (mV)
Temperature (°C)
0 40 80 120
30
20
10
0
–10
–20
–30
SOURCE AND SINK CURRENT CAPABILITY
0
V
OUT
(V)
I
SOURCE/SINK
(mA)
51015
3
2
1
0
DAC Loaded with FFF
H
DAC Loaded with 000
H
VDD = +3V
At TA = +25°C, +VDD = +2.7V, unless otherwise noted.
30
20
10
0
Error (mV)
–10
–20
–30
–40
3000
2500
2000
1500
Frequency
1000
ZERO-SCALE ERROR vs TEMPERATURE
0 40 80 120
Temperature (°C)
IDD HISTOGRAM
V
tied to VDD.
REF
500
0
5060708090
500
400
300
(µA)
DD
I
200
100
100
SUPPLY CURRENT vs CODE
0
0
200
H
400H600H800HA00HC00HE00HFFF
DAC7512
SBAS156B
110
120
IDD (µA)
CODE
130
140
150
160
170
180
190
H
www.ti.com
300
250
200
(µA)
150
DD
I
100
50
0
–40
SUPPLY CURRENT vs TEMPERATURE
0 40 80 120
Temperature (°C)
9
TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.)
At TA = +25°C, +VDD = +2.7V, unless otherwise noted.
2500
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
FULL-SCALE SETTLING TIME
CLK (2.7V/div)
2000
1500
(µA)
DD
1000
I
Full-Scale Code Change
500
0
0
12345
V
(V)
LOGIC
FULL-SCALE SETTLING TIME
CLK (2.7V/div)
V
(1V/div)
OUT
HALF-SCALE SETTLING TIME
CLK (2.7V/div)
Time (1µs/div)
000
to FFF
H
Output Loaded with
H
2kΩ and 200pF to GND
V
(1V/div)
OUT
Time (1µs/div)
HALF-SCALE SETTLING TIME
Full-Scale Code Change
FFF
to 000
H
Output Loaded with
H
2kΩ and 200pF to GND
Half-Scale Code Change
400
to C00
H
V
(1V/div)
OUT
Output Loaded with
2kΩ and 200pF to GND
H
Time (1µs/div)
POWER-ON RESET to 0V
CLK (2.7V/div)
Half-Scale Code Change
C00
to 400
H
H
Output Loaded with
V
(1V/div)
OUT
Time (1µs/div)
2kΩ and 200pF to GND
Time (20µs/div)
10
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DAC7512
SBAS156B
TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.)
CODE CHANGE GLITCH
Time (0.5µs/div)
Loaded with 2kΩ
and 200pF to GND.
Code Change:
800
H
to 7FFH.
V
OUT
(20mV/div)
At TA = +25°C, +VDD = +2.7V, unless otherwise noted.
EXITING POWER-DOWN
(800
Loaded)
H
CLK (2.7V/div)
V
(1V/div)
OUT
Time (5µs/div)
THEORY OF OPERATION
DAC SECTION
The DAC7512 is fabricated using a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Since there is no reference input pin, the
power supply (V
) acts as the reference. Figure 1 shows a
DD
block diagram of the DAC architecture.
V
DD
REF (+)
DAC Register
Resistor
String
REF(–)
Amplifier
GND
Output
V
OUT
FIGURE 1. DAC7512 Architecture.
The input coding to the DAC7512 is straight binary, so the
ideal output voltage is given by:
V
OUT
= VDD•
D
4096
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 4095.
RESISTOR STRING
The resistor string section is shown in Figure 2. It is simply
a string of resistors, each of value R. The code loaded into
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by
closing one of the switches connecting the string to the
amplifier. It is tested monotonic because it is a string of
resistors.
R
R
R
R
R
To Output
Amplifier
FIGURE 2. Resistor String.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-torail voltages on its output which gives an output range of
0V to V
with 1000pF to GND. The source and sink capabilities of the
output amplifier can be seen in the typical characteristics.
The slew rate is 1V/µs with a half-scale settling time of 8µs
with the output unloaded.
. It is capable of driving a load of 2kΩ in parallel
DD
DAC7512
SBAS156B
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11
SERIAL INTERFACE
The DAC7512 has a three-wire serial interface (SYNC,
SCLK, and D
Microwire interface standards as well as most Digital Signal
Processors (DSPs). See the Serial Write Operation timing
diagram for an example of a typical write sequence.
The write sequence begins by bringing the SYNC line LOW.
Data from the D
on the falling edge of SCLK. The serial clock frequency can
be as high as 30MHz, making the DAC7512 compatible with
high-speed DSPs. On the 16th falling edge of the serial
clock, the last data bit is clocked in and the programmed
function is executed (i.e., a change in DAC register contents
and/or a change in the mode of operation).
At this point, the SYNC line may be kept LOW or brought
HIGH. In either case, it must be brought HIGH for a minimum
of 33ns before the next write sequence so that a falling edge
of SYNC can initiate the next write sequence. Since the
SYNC buffer draws more current when the SYNC signal is
HIGH than it does when it is LOW, SYNC should be idled
LOW between write sequences for lowest power operation of
the part. As mentioned above, however, it must be brought
HIGH again just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide, as shown in Figure 3.
The first two bits are “don’t cares”. The next two bits (PD1
and PD0) are control bits that control which mode of operation the part is in (normal mode or one of three power-down
modes). There is a more complete description of the various
modes in the Power-Down Modes section. The next 12 bits
are the data bits. These are transferred to the DAC register
on the 16th falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept LOW for
at least 16 falling edges of SCLK and the DAC is updated on
the 16th falling edge. However, if SYNC is brought HIGH
before the 16th falling edge, this acts as an interrupt to the
), which is compatible with SPI, QSPI, and
IN
line is clocked into the 16-bit shift register
IN
write sequence. The shift register is reset and the write
sequence is seen as invalid. Neither an update of the DAC
register contents or a change in the operating mode occurs,
as shown in Figure 4.
POWER-ON RESET
The DAC7512 contains a power-on reset circuit that controls
the output voltage during power-up. On power-up, the DAC
register is filled with zeros and the output voltage is 0V; it
remains there until a valid write sequence is made to the
DAC. This is useful in applications where it is important to
know the state of the output of the DAC while it is in the
process of powering up.
POWER-DOWN MODES
The DAC7512 contains four separate modes of operation.
These modes are programmable by setting two bits (PD1
and PD0) in the control register. Table I shows how the state
of the bits corresponds to the mode of operation of the
device.
DB13 DB12 OPERATING MODE
0 0 Normal Operation
Power-Down Modes:
0 1 Output 1kΩ to GND
1 0 Output 100kΩ to GND
1 1 High-Z
TABLE I. Modes of Operation for the DAC7512.
When both bits are set to 0, the part works normally with its
normal power consumption of 135µA at 5V. However, for the
three power-down modes, the supply current falls to 200nA
at 5V (50nA at 3V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has
the advantage that the output impedance of the part is known
while the part is in power-down mode. There are three
different options. The output is connected internally to GND
through a 1kΩ resistor, a 100kΩ resistor, or it is left opencircuited (High-Z). See Figure 5 for the output stage.
DB15 DB0
X X PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FIGURE 3. Data Input Register.
CLK
SYNC
D
IN
DB15 DB0 DB15 DB0
Invalid Write Sequence:
SYNC HIGH before 16th Falling Edge
Valid Write Sequence: Output Updates
on the 16th Falling Edge
FIGURE 4. SYNC Interrupt Facility.
12
www.ti.com
DAC7512
SBAS156B
Resistor
SYNC
SCLK
D
IN
Microwire
TM
CS
SK
SO
DAC7513
(1)
String DAC
Amplifier
V
OUT
Power-down
Circuitry
Resistor
Network
FIGURE 5. Output Stage During Power-Down.
All linear circuitry is shut down when the power-down mode
is activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit powerdown is typically 2.5µs for V
= 5V and 5µs for VDD = 3V.
DD
See the Typical Characteristics for more information.
MICROPROCESSOR
INTERFACING
DAC7512 TO 8051 INTERFACE
Figure 6 shows a serial interface between the DAC7512 and
a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the
DAC7512, while RXD drives the serial data line of the part.
The SYNC signal is derived from a bit programmable pin on
the port. In this case, port line P3.3 is used. When data is to
be transmitted to the DAC7512, P3.3 is taken LOW. The
8051 transmits data only in 8-bit bytes; thus only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left LOW after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second
byte of data. P3.3 is taken HIGH following the completion of
this cycle. The 8051 outputs the serial data in a format which
has the LSB first. The DAC7512 requires its data with the
MSB as the first bit received. The 8051 transmit routine must
therefore take this into account, and “mirror” the data as
needed.
NOTE: (1) Additional pins omitted for clarity.
Microwire is a registered trademark of National Semiconductor.
FIGURE 7. DAC7512 to Microwire Interface.
DAC7512 TO 68HC11 INTERFACE
Figure 8 shows a serial interface between the DAC7512 and
the 68HC11 microcontroller. SCK of the 68HC11 drives the
SCLK of the DAC7512, while the MOSI output drives the
serial data line of the DAC. The SYNC signal is derived from
a port line (PC7), similar to what was done for the 8051.
(1)
68HC11
PC7
SCK
MOSI
NOTE: (1) Additional pins omitted for clarity.
DAC7513
SYNC
SCLK
D
IN
FIGURE 8. DAC7512 to 68HC11 Interface.
The 68HC11 should be configured so that its CPOL bit is a
0 and its CPHA bit is a 1. This configuration causes data
appearing on the MOSI output is valid on the falling edge of
SCK. When data is being transmitted to the DAC, the SYNC
line is taken LOW (PC7). Serial data from the 68HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
In order to load data to the DAC7512, PC7 is left LOW after
the first eight bits are transferred, and a second serial write
operation is performed to the DAC and PC7 is taken HIGH
at the end of this procedure.
(1)
80C51/80L51
NOTE: (1) Additional pins omitted for clarity.
(1)
P3.3
TXD
RXD
DAC7512
SYNC
SCLK
D
(1)
IN
FIGURE 6. DAC7512 to 80C51/80L51 Interface.
DAC7512 TO MICROWIRE™ INTERFACE
Figure 7 shows an interface between the DAC7512 and any
Microwire compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the
DAC7512 on the rising edge of the SK signal.
www.ti.com
DAC7512
SBAS156B
APPLICATIONS
USING REF02 AS A POWER
SUPPLY FOR THE DAC7512
Due to the extremely low supply current required by the
DAC7512, an alternative option is to use a REF02 +5V
precision voltage reference to supply the required voltage to
the part, see Figure 9. This is especially useful if the power
supply is too noisy or if the system supply voltages are at
some value other than 5V. The REF02 will output a steady
supply voltage for the DAC7512. If the REF02 is used, the
current it needs to supply to the DAC7512 is 135µA. This is
with no load on the output of the DAC. When the DAC output
13
+15
This is an output voltage range of ±5V with 000H corresponding to a –5V output and FFF
corresponding to a +5V output.
H
SYNC
SCLK
D
+5V
135µA
= 0V to 5V
V
DAC7512
IN
OUT
REF02
Three-Wire
Serial
Interface
FIGURE 9. REF02 as Power Supply to DAC7512.
is loaded, the REF02 also needs to supply the current to the
load. The total current required (with a 5kΩ load on the DAC
output) is:
135µA + (5V/5kΩ) = 1.14mA
The load regulation of the REF02 is typically 0.005%/mA,
which results in an error of 285µV for the 1.14mA current
drawn from it. This corresponds to a 0.2LSB error.
BIPOLAR OPERATION USING THE DAC7512
The DAC7512 has been designed for single-supply operation
but a bipolar output range is also possible using the circuit in
Figure 10. The circuit shown will give an output voltage range
of ±5V. Rail-to-rail operation at the amplifier output is achievable using an OPA340 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
D
R
+ R
V
O
= V •
4096
•
1
2
– V
R
1
DD
where D represents the input code in decimal (0 - 4095).
With V
= 5V, R1 = R2 = 10kΩ:
DD
VO=
5V
10•D
4096
– 5V
R
2
•
R
1
LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies.
As the DAC7512 offers single-supply operation, it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good
performance from the converter.
Due to the single ground pin of the DAC7512, all return
currents, including digital and analog return currents, must
flow through the GND pin. Ideally, GND would be connected
directly to an analog ground plane. This plane would be
separate from the ground connection for the digital components until they were connected at the power entry point of
the system.
The power applied to V
noise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high-frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between the power connections and analog output. This is particularly true for the
DAC7512, as the power supply is also the reference voltage
for the DAC.
As with the GND connection, VDD should be connected to a
+5V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 1µF to 10µF and 0.1µF
bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a
100µF electrolytic capacitor or even a “Pi” filter made up of
inductors and capacitors—all designed to essentially lowpass filter the +5V supply, removing the high-frequency noise.
should be well regulated and low
DD
R
2
10kΩ
V
DD
10 F 0.1 F
Three-Wire
Interface
FIGURE 10. Bipolar Operation with the DAC7512.
14
Serial
R
1
10kΩ
DAC7512
www.ti.com
+5V
OPA703
V
OUT
—5V
–5V
DAC7512
SBAS156B
PACKAGE DRAWINGS
MPDS028B – JUNE 1997 – REVISED SEPTEMBER 2001
DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE
0,65
8
1
1,07 MAX
3,05
2,95
0,38
0,25
5
3,05
2,95
4
Seating Plane
0,15
0,05
0,08
4,98
4,78
M
0,10
0,15 NOM
Gage Plane
0°–6°
0,25
0,69
0,41
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
4073329/C 08/01
DAC7512
SBAS156B
www.ti.com
15
PACKAGE DRAWINGS (Cont.)
MPDS026D FEBRUARY 1997 REVISED FEBRU ARY 2002
DBV (R-PDSO-G6) PLASTIC SMALL-OUTLINE
0,95
1,45
0,95
3,00
2,80
46
31
0,05 MIN
6X
0,50
0,25
1,70
1,50
0,20
3,00
2,60
Seating Plane
M
0,15 NOM
Gage Plane
0,25
0° 8 °
0,10
0,55
0,35
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D.
Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation.
4073253-5/G 01/02
16
www.ti.com
DAC7512
SBAS156B
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
DAC7512E/250 ACTIVE MSOP DGK 8 250 TBD CU NIPDAU Level-3-220C-168 HR
DAC7512E/2K5 ACTIVE MSOP DGK 8 2500 TBD CU NIPDAU Level-3-220C-168 HR
DAC7512N/250 ACTIVE SOT-23 DBV 6 250 Green (RoHS&
no Sb/Br)
DAC7512N/250G4 ACTIVE SOT-23 DBV 6 250 Green (RoHS &
no Sb/Br)
DAC7512N/3K ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br)
DAC7512N/3KG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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