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DAC1007
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Texas Instruments DAC1006, DAC1007, DAC1008 User Manual

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DAC1006,DAC1007,DAC1008
DAC1006/DAC1007/DAC1008 P Compatible, Double-Buffered D to A Converters
Literature Number: SNAS540
DAC1006/DAC1007/DAC1008 µP Compatible, Double-Buffered D to A Converters
General Description
These devices, combinedwith an external amplifier and volt­age reference, can be used as standard D/A converters; and they are very attractive for multiplying applications (such as digitally controlled gain blocks) since their linearity error is essentially independent of the voltage reference. They be­come equally attractive in audio signal processing equip­ment as audio gain controls or as programmable attenuators which marry high quality audio signal processing to digitally based systems under microprocessor control.
All of these DACs are double buffered. They can load all 10 bits or two 8-bit bytes and the data format is left justified. The analog section of these DACs is essentially the same as that of the DAC1020.
#
Part
DAC1006 10 For left­DAC1007 9 20 justified DAC1008 8 data
Accuracy Pin Description
(bits)
™
). For
Features
n Uses easy to adjust END POINT specs, NOT BEST
STRAIGHT LINE FIT
n Low power consumption n Direct interface to all popular microprocessors n Integrated thin film on CMOS structure n Double-buffered, single-buffered or flow through digital
data inputs
n Loads two 8-bit bytes or a single 10-bit word n Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
n Works with
multiplication
n Operates STAND ALONE (without µP) if desired n Available in 0.3" standard 20-pin package n Differential non-linearity selection available as special
order
±
10V reference— full 4-quadrant
Key Specifications
n Output Current Settling Time: 500 ns n Resolution: 10 bits n Linearity: 10, 9, and 8 bits (guaranteed over temp.) n Gain Tempco: −0.0003%of FS/˚C n Low Power Dissipation: 20 mW (including ladder) n Single Power Supply: 5 to 15 V
DC
April 1998
DAC1006/DAC1007/DAC1008 µP Compatible, Double-Buffered D to A Converters
DAC1006/DAC1007/DAC1008
Typical Application
DAC1006/1007/1008
*
NOTE: FOR DETAILS OF BUS CONNECTION SEE SECTION 6.0
MICRO-DAC™and BI-FET™are trademarks of National Semiconductor Corp.
© 1998 National Semiconductor Corporation DS005688 www.national.com
PrintDate=1998/11/17 PrintTime=11:38:07 46711 ds005688 Rev. No. 4 cmserv
DS005688-1
Proof 1
1
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (V Voltage at Any Digital Input VCCto GND Voltage at V Storage Temperature Range −65˚C to +150˚C Package Dissipation at T
(Note 3) 500 mW
DC Voltage Applied to I
(Note 4) −100 mV to V
)17V
CC
REF
Input
OUT1
=
25˚C
A
or I
OUT2
±
25V
ESD Susceptibility (Note 11) 800V Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic) 260˚C Dual-In-Line Package (ceramic) 300˚C
DC
Operating Ratings (Note 1)
Temperature Range T
Part numbers with “LCN” and “LCWN” suffix 0˚C to 70˚C
Voltage at Any Digital Input V
CC
MIN
≤ TA≤ T
to GND
CC
MAX
Electrical Characteristics
Tested at V
=
4.75 V
CC
and 15.75 VDC,T
DC
Parameter Conditions
Resolution 10 10 bits Linearity Error Endpoint adjust only 4,7
<
<
T
T
T
MIN
A
−10V≤V
MAX
≤+10V 5
REF
DAC1006 0.05 0.05 DAC1007 0.1 0.1 DAC1008 0.2 0.2
Differential Endpoint adjust only 4,7
<
Nonlinearity T
MIN
−10V≤V
<
T
T
A
MAX
≤+10V 5
REF
DAC1006 0.1 0.1 DAC1007 0.2 0.2 DAC1008 0.4 0.4
<
Monotonicity T
MIN
−10V≤V
<
T
T
A
MAX
≤+10V 5
REF
DAC1006 10 10 bits DAC1007 9 9 bits DAC1008 8 8 bits
Gain Error Using internal R
Gain Error Tempco T
−10V≤V
MIN
≤+10V 5 −1.0±0.3 1.0 −1.0±0.3 1.0
REF
<
<
T
T
A
MAX
Using internal R
Power Supply All digital inputs
Rejection latched high
=
V
14.5V to 15.5V 0.003 0.008
CC
11.5V to 12.5V 0.004 0.010
4.75V to 5.25V 0.033 0.10
Reference Input
Resistance 10 15 20 10 15 20 kΩ
Output Feedthrough V
REF
=
20V
p-p
Error All data inputs 90 90 mV
latched low
=
A
fb
fb
,f=100 kHz
25˚C, V
=
10.000 V
REF
See
Note
Min. Typ. Max. Min. Typ. Max.
unless otherwise noted
DC
=
12V
±
DC
±
5
DC
V
CC
to 15V
=
%
5
V
±
%
5
5V
CC
DC
%
6
6
4,6
6 9 −0.0003 −0.001 −0.0006 −0.002%of FS/˚C
% % %
% % %
%
% % %
Units
of FSR of FSR of FSR
of FSR of FSR of FSR
of FS
FSR/V FSR/V FSR/V
p-p
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PrintDate=1998/11/17 PrintTime=11:38:07 46711 ds005688 Rev. No. 4 cmserv Proof 2
Electrical Characteristics (Continued)
Tested at V
=
4.75 V
CC
and 15.75 VDC,T
DC
Parameter Conditions
Output I
Capacitance I
Supply Current Drain
Output Leakage T
Current I
All data inputs 60 60 pF
OUT1 OUT2
I
OUT1
I
OUT2
OUT1
latched low 250 250 pF
All data inputs 250 250 pF
latched high 60 60 pF
T
MIN≤TA≤TMAX
MIN≤TA≤TMAX
All data inputs
latched low 10 200 200 nA
I
All data inputs
OUT2
latched high 200 200 nA
Digital Input T
MIN≤TA≤TMAX
Voltages Low level
LCN and LCWM suffix 0.8, 0.8 0.7, 0.8 V
High level (all parts) 2.0 2.0 V
Digital Input T
Currents Digital inputs
MIN≤TA≤TMAX
<
Digital inputs>2.0V 1.0 +10 1.0 +10 µA
=
Current tSV
IL
0V, V
=
IH
Settling Time
=
Write and t
XFER Pulse
Width T
Data Set Up t
Time T
Data Hold t
Time T
Control Set t
Up Time T
Control Hold t
Time T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking. Note 4: For current switching applications, both I
by approximately V
Note 5: Guaranteed at V Note 6: T Note 7: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a par-
ticular V
REF
after performing a zero and full scale adjustment (See Sections 2.5 and 2.6), the plot of the 1024 analog voltage outputs will each be within 0.05%xV line which passes through zero and full scale.
Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (t of only 100 ns. The entire write pulse must occur within the valid data interval for the specified tW,tDS,tDH, and tSto apply.
Note 9: Guaranteed by design but not tested.
WVIL
T
A MIN≤TA≤TMAX
DSVIL
A
T
MIN≤TA≤TMAX
DHVIL
A
T
MIN≤TA≤TMAX
CSVIL
A
T
MIN≤TA≤TMAX
CHVIL
A
T
MIN≤TA≤TMAX
÷
V
. For example, if V
OS
REF
=
±
REF
=
0˚C and T
MIN
value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC1006 is “0.05%of FSR (MAX).” This guarantees that
=
70˚C for “LCN” and “LCWM” suffix parts.
MAX
=
0V, V
5V,
IH
=
25˚C 8 150 60 320 200 ns
=
0V, V
IH
=
25˚C 9 150 80 320 170 ns
=
=
OV, V
5V
IH
=
25˚C 9 200 100 320 220 ns
=
=
0V, V
5V,
IL
=
25˚C 9 150 60 320 180 ns
=
=
0V, V
5V,
IH
=
25˚C 9 10 0 10 0 ns
10 VDCand V
=
A
25˚C, V
=
10.000 V
REF
See
Note
Min. Typ. Max. Min. Typ. Max.
unless otherwise noted
DC
=
12V
±
DC
±
5
DC
V
CC
to 15V
%
5
V
%
=
±
%
5
5V
CC
DC
6 0.5 3.5 0.5 3.5 mA
6
6
6
0.8V −40 −150 −40 −150 µA
5V 500 500 ns
9 320 100 500 250 ns
=
5V,
320 120 500 250 ns
250 120 500 320 ns
320 100 500 260 ns
10 0 10 0 ns
and I
OUT1
=
10Vthena1mVoffset, V
REF
=
±
REF
must go to ground or the “Virtual Ground” of an operational amplifier.Thelinearity error is degraded
OUT2
1VDC.
OS
,onI
OUT1
or I
will introduce an additional 0.01%linearity error.
OUT2
) of 320 ns. A typical part will operate with t
W
of a straight
REF
Units
DC DC
DC DC
W
PrintDate=1998/11/17 PrintTime=11:38:08 46711 ds005688 Rev. No. 4 cmserv Proof 3
www.national.com3
Electrical Characteristics (Continued)
Note 10: A 200 nA leakage current with R Note 11: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
=
20K and V
fb
=
10V corresponds to a zero error of (200x10
REF
Switching Waveforms
−9
x20x103)x100÷10 which is 0.04%of FS.
DS005688-2
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PrintDate=1998/11/17 PrintTime=11:38:08 46711 ds005688 Rev. No. 4 cmserv Proof 4
Typical Performance Characteristics
Errors vs. Supply Voltage
Control Setup Time, t
CS
Digital Threshold vs. Supply Voltage
DS005688-29
DS005688-32
Errors vs. Temperature
Data Setup Time, t
DS
Digital Input Threshold vs. Temperature
DS005688-30
DS005688-33
Write Width, t
w
Data Hold Time, t
DS005688-31
DH
DS005688-34
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DS005688-35
DS005688-36
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Block and Connection Diagrams
DAC1006/1007/1008 (20-Pin Parts)
Use DAC1006/1007/1008 for left justified data.
DS005688-5
DAC1006/1007/1008
(20-Pin Parts)
Dual-In-Line Package
DS005688-28
Top View
See Ordering Information
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DAC1006/1007/1008—Simple Hookup for a “Quick Look”
*
A TOTAL OF 10 INPUT SWITCHES & 1K RESISTORS
Notes:
=
REF
−10.240 V
1. For V
2. SW1 is a normally closed switch. While SW1 is closed, the DAC register is latched and new data can be loaded into the input latch via the 10 SW2 switches. When SW1 is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SW1 again closes.
1.0 DEFINITION OF PACKAGE PINOUTS
1.1 Control Signals (All control signals are level actuated.) CS: Chip Select — active low, it will enable WR. WR: Write — The active low WR is used to load the digital
Byte1/Byte2: Byte Sequence Control — When this control is high, all ten locations of the input latch are enabled. When low, only two locations of the input latch are enabled and these two locations are overwritten on the second byte write. On the DAC1006, 1007, and 1008, the Byte1/Byte2 must be low to transfer the 10-bit data in the input latch to the DAC register.
XFER: Transfer Control Signal, active low — This signal, in combination with others, is used to transfer the 10-bit data which is available in the input latch to the DAC register — see timing diagrams.
1.2 Other Pin Functions DI
(i=0to9):Digital Inputs — DI0is the least significant bit
i
(LSB) and DI
: DAC Current Output 1 — I
I
OUT1
digital input code of all 1s and is zero for a digital input code of all 0s.
I
: DAC Current Output 2 — I
OUT2
I
,or
OUT1
the output voltage steps are approximately 10 mV each.
DC
is the most significant bit (MSB).
g
is a maximum for a
OUT1
is a constant minus
OUT2
amp is used to provide an output voltage for the DAC. This on-chip resistor should always be used (not an external re­sistor) because it matches the resistors used in the on-chip R-2R ladder and tracks these resistors over temperature.
V
: Reference Voltage Input — This is the connection for
REF
can range from −10 to +10 volts. This is also the
REF
cation.
V
: Digital Supply Voltage — This is the power supply pin
CC
for the part. V timum for +15V. The input threshold voltages are nearly in­dependent of V and Description in Section 3.0, T
can be from +5 to +15 VDC. Operation is op-
CC
. (See Typical Performance Characteristics
CC
GND: Ground — the ground pin for the part.
1.3 Definition of Terms Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC1006
10
has 2
or 1024 steps and therefore has 10-bit resolution.
Linearity Error: Linearity error is the maximum deviation from a
straight line passing through the endpoints of the
DAC transfer characteristic.
National’s linearity test (a) and the “best straight line” test (b) used by other suppliers are illustrated below. The “best straight line” requires a special zero and FS adjustment for each part, which is almost impossible for user to determine. The “end point test” uses a standard zero and FS adjustment procedure and is a much more stringent test for DAC linear-
DS005688-7
2
L compatible logic inputs.)
It is measured after adjusting for
ity. Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
where R≅15 kΩ.
: Feedback Resistor — This is provided on the IC chip
R
FB
for use as the shunt feedback resistor when an external op
full-scale output (which is the worst case).
PrintDate=1998/11/17 PrintTime=11:38:08 46711 ds005688 Rev. No. 4 cmserv Proof 7
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DAC1006/1007/1008—Simple Hookup for a “Quick Look” (Continued)
a. End Point Test After Zero and FS Adj.
DS005688-37
Settling Time: Settling time is the time required from a code transition until the DAC output reaches within
1
±
⁄2LSB of the final output value. Full-scale settling time requires a zero to full-scale or full-scale to zero output change.
Full-Scale Error: Full scale error is a measure of the output error between an ideal DAC and the actual device output. Ideally, for the DAC1006 series, full-scale is V For V V
FULL-SCALE
adjustable to zero.
=
−10V and unipolar operation,
REF
=
10.0000V −9.8mV=9.9902V.Full-scale error is
REF
−1 LSB.
Monotonicity: If the output of a DAC increases for increas­ing digital input code, then the DAC is monotonic. A 10-bit DAC with 10-bit monotonicity will produce an increasing ana­log output when all 10 digital inputs are exercised. A 10-bit DAC with 9-bit monotonicity will be monotonic when only the most significant 9 bits are exercised. Similarly, 8-bit monoto­nicity is guaranteed when only the most significant 8 bits are exercised.
2.0 DOUBLE BUFFERING
These DACs are double-buffered, microprocessor compat­ible versions of the DAC1020 10-bit multiplying DAC. The addition of the buffers for the digital input data not only al­lows for storage of this data, but also provides a way to as­semble the 10-bit input data word from two write cycles when using an 8-bit data bus. Thus, the next data update for the DAC output can be made with the complete new set of 10-bit data. Further, the double buffering allows many DACs in a system to store current data and also the next data. The up­dating of the new data for each DAC is also not time critical. When all DACs are updated, a common strobe signal can then be used to cause all DACs to switch to their new analog output levels.
b. Best Straight Line
DS005688-38
3.0 TTL COMPATIBLE LOGIC INPUTS
To guarantee TTL voltage compatibility of the logic inputs, a novel bipolar (NPN) regulator circuit is used. This makes the input logic thresholds equal to the forward drop of two diodes (and also matches the temperature variation) as occurs naturally in TTL. The basic circuit is shown in
Figure 1
.A curve of digital input threshold as a function of power supply voltage is shown in the Typical Performance Characteristics section.
4.0 APPLICATION HINTS
The DC stability of the V factor to maintain accuracy of the DAC over time and tem-
source is the most important
REF
perature changes. A good single point ground for the analog signals is next in importance.
These MICRO-DAC converters are CMOS products and rea­sonable care should be exercised in handling them prior to fi­nal mounting on a PC board. The digital inputs are protected, but permanent damage may occur if the part is subjected to high electrostatic fields. Store unused parts in conductive foam or anti-static rails.
4.1 Power Supply Sequencing & Decoupling
OUT1
or I
to ground may be required to pre-
OUT2
OUT1
or I
OUT2
. If an LM741 or
The standard power supply decoupling capacitors which are used for the op amp are adequate for the DAC.
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DAC1006/1007/1008—Simple Hookup for a “Quick Look” (Continued)
DS005688-9
FIGURE 1. Basic Logic Threshold Loop
4.2 Op Amp Bias Current & Input Leads
The op amp bias current (I
™
BI-FET
op amps have very low bias current, and therefore
) CAN CAUSE DC ERRORS.
B
the error introduced is negligible. BI-FET op amps are strongly recommended for these DACs.
The distance from the I input of the op amp should be kept as short as possible to
pin of the DAC to the inverting
OUT1
prevent inadvertent noise pickup.
5.0 ANALOG APPLICATIONS
The analog section of these DACs uses an R-2R ladder which can be operated both in the current switching mode and in the voltage switching mode.
The major product changes (compared with the DAC1020) have been made in the digital functioning of the DAC. The analog functioning is reviewed here for completeness. For additional analog applications, such as multipliers, attenua­tors, digitally controlled amplifiers and low frequency sine wave oscillators, refer to the DAC1020 data sheet. Some ba­sic circuit ideas are presented in this section in addition to complete applications circuits.
5.1 Operation in Current Switching Mode
The analog circuitry,
Figure 2
, consists of a silicon-chromium (Si-Cr) thin film R-2R ladder which is deposited on the sur­face oxide of the monolithic chip. As a result, there is no parasitic diode connected to the V diffused resistors were used. The reference voltage input (V
) can therefore range from −10V to +10V.
REF
pin as would exist if
REF
The digital input code to the DAC simply controls the position of the SPDT current switches, SW0 to SW9. A logical 1 digi­tal input causes the current switch to steer the available lad-
der current to the I erate in the current mode with a small voltage drop across them and can therefore switch currents of either polarity. This is the basis for the 4-quadrant multiplying feature of this DAC.
5.1.1 Providing a Unipolar Output Voltage with the DAC in the Current Switching Mode
Avoltage output is provided by making use of an external op amp as a current-to-voltage converter.The idea is to use the internal feedback resistor, R amp to the inverting (−) input. Now, when current is entered at this inverting input, the feedback action of the op amp keeps that input at ground potential. This causes the applied input current to be diverted to the feedback resistor. The out­put voltage of the op amp is forced to a voltage given by:
Notice that the sign of the output voltage depends on the di­rection of current flow through the feedback resistor.
In current switching mode applications, both current output pins (I accomplished as shown in
OUT1
and I
used to compensate for the output capacitance of the DAC and the input capacitance of the op amp. The required feed­back resistor, R nally tied to I tor will not provide the needed matching and temperature
OUT1
tracking. This circuit can therefore be simplified as shown in
Figure 4
, where the sign of the reference voltage has been changed to provide a positive output voltage. Note that the output current, I
output pin. These MOS switches op-
OUT1
, from the output of the op
FB
=
V
−(I
OUT
OUT1xRFB
) should be operated at 0 VDC. This is
OUT2
, is available on the chip (one end is inter-
FB
) and must be used since an external resis-
OUT1
Figure 3
. The capacitor, CC,is
, now flows through the RFBpin.
)
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DAC1006/1007/1008—Simple Hookup for a “Quick Look” (Continued)
DIGITAL INPUT CODE
DS005688-39
FIGURE 2. Current Mode Switching
DS005688-40
C pF
R
C
ts µS
j
∞
3
∞
4
to V
OUT
OUT
OP
AMP
LF356 22 LF351 24 LF357 10 2.4k 1.5
FIGURE 3. Converting I
5.1.2 Providing a Bipolar Output Voltage with the DAC in the Current Switching Mode
The addition of a second op amp to the circuit of
Figure 4
(−512≤D≤+511 or 1000000000≤D≤0111111111). If the ap­plied digital input is interpreted as the decimal equivalent of a true binary word, V
can be found by:
OUT
can be used to generate a bipolar output voltage from a fixed reference voltage
Figure 5
. This, in effect, gives sign signifi­cance to the MSB of the digital input word to allow two quad­rant multiplication of the reference voltage. The polarity of the reference can also be reversed to realize the full four-quadrant multiplication.
The applied digital word is offset binary which includes a code to output zero volts without the need of a large valued resistor common to existing bipolar multiplying DAC circuits. Offset binary code can be derived from 2’s complement data (most common for signed processor arithmetic) by inverting the state of the MSB in either software or hardware. After do­ing this the output then responds in accordance to the follow­ing expression:
With this configuration, only the offset voltage of amplifier 1 need be nulled to preserve linearity of the DAC. The offset voltage error of the second op amp has no effect on linearity. It presents a constant output voltage error and should be nulled only if absolute accuracy is needed. Another advan­tage of this configuration is that the values of the external re­sistors required do not have to match the value of the inter­nal DAC resistors; they need only to match and temperature track each other.
A thin film 4 resistor network available from Beckman Instru­ments, Inc. (part no. 694-3-R10K-D) is ideally suited for this application. Two of the four available 10 kΩ resistor can be paralleled to form R in
Figure 5
and the other two can be
used separately as the resistors labeled 2R.
where V decimal equivalent of the 2’s complement processor data.
www.national.com 10
can be positive or negative and D is the signed
REF
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DAC1006/1007/1008—Simple Hookup for a “Quick Look” (Continued)
Operation is summarized in the table below:
Applied
2’s Comp. 2’s Comp. Applied True Binary V
(Decimal) (Binary) Digital Input (Decimal) +V
+511 0111111111 1111111111 1023 V +256 0100000000 1100000000 768 V
REF
−1 LSB −|V
REF
REF
0 0000000000 1000000000 512 0 0
−1 1111111111 0111111111 511 −1 LSB +1 LSB
−256 1100000000 0100000000 256 −V
−512 1000000000 0000000000 0 −V
REF
REF
DS005688-41
FIGURE 4. Providing a Unipolar Output Voltage
OUT
REF
/2 −|V
/2 +|V
−V
REF
REF
+|V
REF
|+1 LSB
REF
|/2
|/2
|
DS005688-42
FIGURE 5. Providing a Bipolar Output Voltage with the DAC in the Current Switching Mode
5.2 Analog Operation in the Voltage Switching Mode
Some useful application circuits result if the R-2R ladder is operated in the voltage switching mode. There are two very important things to remember when using the DAC in the voltage mode. The reference voltage (+V) must always be positive since there are parasitic diodes to ground on the I
pin which would turn on if the reference voltage went
OUT1
negative. To maintain a degradation of linearity less than
±
0.005%, keep +V ≤ 3VDCand VCCat least 10V more posi-
tive than +V.
Figures 6, 7
show these errors for the voltage switching mode. This operation appears unusual, since a ref­erence voltage (+V) is applied to the I age output is the V
8
.
This V gain stage as shown in
range can be scaled by use of a non-inverting
OUT
pin. This basic idea is shown in
REF
Figure 9
.
pin and the volt-
OUT1
Figure
single op amp as shown in of all zeros, the output voltage from the V volts. The external op amp now has a single input of +V and
Figure 10
. For a digital input code
REF
pin is zero
is operating with a gain of −1 to this input. The output of the op amp therefore will be at −V for a digital input of all zeros. As the digital code increases, the output voltage at the V pin increases.
REF
=
V
OUT
(+V) (−1)+V
REF
(+2)
Notice that this is unipolar operation since all voltages are positive. A bipolar output voltage can be obtained by using a
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DAC1006/1007/1008—Simple Hookup for a “Quick Look” (Continued)
DS005688-43
FIGURE 6.
FIGURE 7.
DIGITAL INPUT CODE
DS005688-45
FIGURE 8. Voltage Mode Switching
DS005688-46
FIGURE 9. Amplifying the Voltage Mode Output (Single Supply Operation)
DS005688-44
FIGURE 10. Providing a Bipolar Output Voltage with a Single Op Amp
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DS005688-47
DAC1006/1007/1008—Simple Hookup for a “Quick Look” (Continued)
DS005688-48
FIGURE 11. Increasing the Output Voltage Swing
The output voltage swing can be expanded by adding 2 re­sistors to
Figure 10
as shown in
Figure 11
. These added re­sistors are used to attenuate the +V voltage. The overall gain, A
(−), from the +V terminal to the output of the op amp
V
determines the most negative output voltage, −4(+V) (when the V
voltage at the + input of the op amp is zero) with the
REF
is provided by the gain from the (+) input of the op
OUT
amp. As the voltage at the V +V(1023/1024) the output of the op amp will range from −10 V
to +10V (1023/1024) when using a +V voltage of +2.500
DC
V
. The 2.5 VDCreference voltage can be easily developed
DC
by using the LM336 zener which can be biased through the R
internal resistor, connected to VCC.
FB
5.3 Op Amp V Switching Mode
Adjust (Zero Adjust) for Current
OS
pin ranges from 0V to
REF
, of the external op amp cannot be tolerated as ev-
OS
ery millivolt of V ror. At first this seems unusually sensitive, until it becomes
will introduce 0.01%of added linearity er-
OS
(ground). Therefore offset volt-
DC
clear the 1 mV is 0.01%of the 10V reference! High resolu­tion converters of high accuracy require attention to every detail in an application to achieve the available performance which is inherent in the part. To prevent this source of error, the V
of the op amp has to be initially zeroed. This is the
OS
“zero adjust” of the DAC calibration sequence and should be done first.
If the V Note that no “dc balancing” resistance should be used in the
is to be adjusted there are a few points to consider.
OS
grounded positive input lead of the op amp. This resistance and the input current of the op amp can also create errors. The low input biasing current of the BI-FET op amps makes them ideal for use in DAC current to voltage applications. The V
of the op amp should be adjusted with a digital input
OS
of all zeros to force I porarily connected from the inverting input to ground to pro­vide a dc gain of approximately 15 to the V and make the zeroing easier to sense.
=
0mA.A1kΩresistor can be tem-
OUT
of the op amp
OS
5.4 Full-Scale Adjust
The full-scale adjust procedure depends on the application circuit and whether the DAC is operated in the current switching mode or in the voltage switching mode. Tech­niques are given below for all of the possible application cir­cuits.
5.4.1 Current Switching with Unipolar Output Voltage
After doing a “zero adjust,” set all of the digital input levels HIGH and adjust the magnitude of V
REF
This completes the DAC calibration.
5.4.2 Current Switching with Bipolar Output Voltage
The circuit of
Figure 12
shows the 3 adjustments needed. The first step is to set all of the digital inputs LOW (to force I
to 0) and then trim “zero adj.” for zero volts at the in-
OUT1
verting input (pin 2) of 0A1. Next, with a code of all zeros still applied, adjust “−FS adj.”, the reference voltage, for
=
±
V
|(ideal V
OUT
opposite that of the applied reference. Finally,set all of the digital inputs HIGH and adjust “+FS adj.”
=
for V will be the same as that of the reference voltage. The addi-
OUT
V
)|. The sign of the output voltage will be
REF
(511/512).The sign of the output at this time
REF
tion of the 200Ω resistor in series with the V DAC is to force the circuit gain error from the DAC to be negative. This insures that adding resistance to R 500Ω pot, will always compensate the gain error of the DAC.
5.4.3 Voltage Switching with a Unipolar Output Voltage
Refer to the circuit of LOW. Trim the “zero adj.” for V all digital inputs HIGH and trim the “FS Adj.” for:
Figure 13
and set all digital inputs
=
0V
OUT
5.4.4 Voltage Switching with a Bipolar Output Voltage
Figure 14
Refer to “−FS Adj.” for V HIGH and trim the “+FS Adj.” for V Test the zero by setting the MS digital input HIGH and all the rest LOW. Adjust V the full-scale values.
and set all digital inputs LOW. Trim the
OUT
=
OS
. Then set all digital inputs
−2.5 V
DC
=
OUT
of amp#3, if necessary, and recheck
for
pin of the
REF
, with the
fb
±
1 mV. Then set
DC
+2.5 (511/512) V
.
DC
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DAC1006/1007/1008—Simple Hookup for a “Quick Look” (Continued)
DS005688-49
FIGURE 12. Full Scale Adjust — Current Switching with Bipolar Output Voltage
FIGURE 13. Full Scale Adjust — Voltage Switching with a Unipolar Output Voltage
FIGURE 14. Voltage Switching with a Bipolar Output Voltage
6.0 DIGITAL CONTROL DESCRIPTION
The DAC1006 series of products can be used in a wide va­riety of operating modes. Most of the options are shown in
Table1
. Also shown in this table are the section numbers of
this data sheet where each of the operating modes is dis-
www.national.com 14
DS005688-50
DS005688-15
cussed. For example, if your main interest in interfacing to a µP with an 8-bit data bus you will be directed to Section
6.1.0. The first consideration is “will the DAC be interfaced to a µP
with an 8-bit or a 16-bit data bus or used in the stand-alone mode?” For the 8-bit data bus, a second selection is made
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DAC1006/1007/1008—Simple Hookup for a “Quick Look”
on how the 2nd digital data buffer (the DAC Latch) is up­dated by a transfer from the 1st digital data buffer (the Input Latch). Three options are provided: 1) an automatic transfer when the 2nd data byte is written to the DAC, 2) a transfer which is under the control of the µP and can include more than one DAC in a simultaneous transfer, or 3) a transfer which is under the control of external logic. Further, the data format can be either left justified or right justified.
When interfacing to a µP with a 16-bit data bus only two se­lections are available: 1) operating the DAC with a single digital data buffer (the transfer of one DAC does not have to be synchronized with any other DACs in the system), or 2) operating with a double digital data buffer for simultaneous transfer, or updating, of more than one DAC.
For operating without a µP in the stand alone mode, three options are provided: 1) using only a single digital data
Operating Mode Automatic Transfer µP Control Transfer External Transfer
Section Figure No. Section Figure No. Section Figure No.
Data Bus
8-Bit Data Bus (6.1.0)
Left Justified (6.1.1) 6.2.1 16 6.2.2 16 6.2.3 16
16-Bit Data Bus (6.3.0) Single Buffered Double Buffered Flow Through
6.3.1 17 6.3.2 17 Not Applicable
Stand Alone (6.4.0) Single Buffered Double Buffered Flow Through
6.4.1 17 6.4.2 17 NA
(Continued)
buffer, 2) using both digital data buffers — “double buff­ered,” or 3) allowing the input digital data to “flow through” to provide the analog output without the use of any data latches.
To reduce the required reading, only the applicable sections of 6.1 through 6.4 need be considered.
6.1 Interfacing to an 8-Bit Data Bus
1. Is the data to be left justified (considered as fractional bi-
nary data with the binary point to the left) or right justified (considered as binary weighted data with the binary point to the right)?
2. Which byte will be transfered first, the most significant
byte (MS byte) or the least significant byte (LS byte)?
TABLE 1.
These data possibilities are shown in the justification of data depends on how the 10-bit data word is located within the 16-bit data source (CPU) register. In ei­ther case, there is a surplus of 6 bits and these are shown as “don’t care” terms (“x”) in this figure.
All of these DACs load 10 bits on the 1st write cycle. A par­ticular set of 2 bits is then overwritten on the 2nd write cycle, depending on the justification of the data. For all left justified data options, the 1st write cycle must contain the MS or Hi Byte data group.
6.1.1 For Left Justified Data
For applications which require left justified data, DAC1006–1008 can be used. A simplified logic diagram which shows the external connections to the data bus and the internal functions of both of the data buffer registers (In­put Latch and DAC Register) is shown in parts require the MS or Hi Byte data group to be transferred on the 1st write cycle.
Figure 15
Figure 16
. Note that
. These
6.2 Controlling Data Transfer for an 8-Bit Data Bus
Three operating modes are possible for controlling the trans­fer of data from the Input Latch to the DAC Register, where it will update the analog output voltage. The simplest is the automatic transfer mode, which causes the data transfer to occur at the time of the 2nd write cycle. This is recom­mended when the exact timing of the changes of the DAC analog output are not critical. This typically happens where each DAC is operating individually in a system and the ana­log updating of one DAC is not required to be synchronized to any other DAC. For synchronized DAC updating, two op­tions are provided: µP control via a common XFER strobe or external update timing control via an external strobe. The de­tails of these options are now shown.
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DAC1006/1007/1008—Simple Hookup for a “Quick Look” (Continued)
DAC1006/1007/1008 (20-Pin Parts for Left Justified Data)
DS005688-16
FIGURE 15. Fitting a 10-Bit Data Word into 16 Available Bit Locations
FIGURE 16. Input Connections and Controls for DAC1006/1007/1008 Left Justified Data
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DS005688-17
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DAC1006/1007/1008—Simple Hookup for a “Quick Look”
6.2.1 Automatic Transfer
This makes use of a double byte (double precision) write. The first byte (8 bits) is strobed into the input latch and the second byte causes a simultaneous strobe of the two re­maining bits into the input latch and also the transfer of the complete 10-bit word from the input latch to the DAC regis­ter.This is shown in the following timing diagram; the point in time where the analog output is updated is also indicated on this diagram.
DAC1006/1007/1008 (20-Pin Parts)
*
SIGNIFIES CONTROL INPUTS WHICH ARE DRIVEN IN PARALLEL
6.2.2 Transfer Using µP Write Stroke
The input latch is loaded with the first two write strobes. The XFER signal is provided by external logic, as shown below, to cause the transfer to be accomplished on a third write strobe. This is shown in the following diagram:
(Continued)
DS005688-18
DAC1006/1007/1008 (20–Pin Parts)
DS005688-19
6.2.3 Transfer Using an External Strobe
This is similar to the previous operation except the XFER signal is not provided by the µP. The timing diagram for this is:
DAC1006/1007/1008 (20–Pin Parts)
6.3 Interfacing to a 16-Bit Data Bus
DS005688-20
The interface to a 16-bit data bus is easily handled by con­necting to 10 of the available bus lines. This allows a wiring selected right justified or left justified data format. This is shown in the connection diagram of
Figure 17
, where the use of DB6 to DB15 gives left justified data operation. Note that any part number can be used and the Byte1/Byte2 con­trol should be wired Hi.
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DAC1006/1007/1008—Simple Hookup for a “Quick Look” (Continued)
DS005688-21
FIGURE 17. Input Connections and Logic for DAC1006/1007/1008 with 16-Bit Data Bus
Three operating modes are possible: flow through, single buffered, or double buffered. The timing diagrams for these are shown below:
6.3.1 Single Buffered
DAC1006/1007/1008 (20-Pin Parts)
6.4.1 Single Buffered
DAC1006/1007/1008 (20-Pin Parts)
6.4.2 Double Buffered
DS005688-53
DS005688-51
6.3.2 Double Buffered
DAC1006/1007/1008 (20-Pin Parts)
DS005688-52
6.4 Stand Alone Operation
For applications for a DAC which are not under µP control (stand alone) there are two basic operating modes, single buffered and double buffered. The timing diagrams for these are shown below:
www.national.com 18
DAC1006/1007/1008 (20-Pin Parts) (Note 12)
Note 12: For a connection diagram of this operating mode use
the Logic and
Figure 17
for the Data Input connections.
DS005688-54
Figure 16
7.0 MICROPROCESSOR INTERFACE
The logic functions of the DAC1006 family have been ori­ented towards an ease of interface with all popular µPs. The following sections discuss in detail a few useful interface schemes.
7.1 DAC1001/1/2 to INS8080A Interface
Figure 18
illustrates the simplicity of interfacing the
DAC1006 to an INS8080A based microprocessor system. The circuit will perform an automatic transfer of the 10 bits of
output data from the CPU to the DAC register as outlined in Section 6.2.1, “Controlling Data Transfer for an 8-Bit Data Bus.”
Since a double byte write is necessary to control the DAC with the INS8080A, a possible instruction to achieve this is a PUSH of a register pair onto a “stack” in memory. The 16-bit register pair word will contain the 10 bits of the eventual DAC input data in the proper sequence to conform to both the re­quirements of the DAC (with regard to left justified data) and
for
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DAC1006/1007/1008—Simple Hookup for a “Quick Look”
the implementation of the PUSH instruction which will output the higher order byte of the register pair (i.e., register B of the BC pair) first. The DAC will actually appear as a two-byte “stack” in memory to the CPU. The auto-decrementing of the
(Continued)
stack pointer during a PUSH allows using address bit 0 of the stack pointer as the Byte1/Byte2 and XFER strobes if bit 0 of the stack pointer address −1, (SP−1), is a “1” as pre­sented to the DAC. Additional address decoding by the DM8131 will generate a unique DAC chip select (CS) and synchronize this CS to the two memory write strobes of the PUSH instruction.
NOTE: DOUBLE BYTE STORES CAN BE USED. e.g. THE INSTRUCTION SHLD F001 STORES THE L REG INTO B1 AND THE H REG INTO B2 AND TRANSFERS THE RESULT TO THE DAC REGISTER.
THE OPERAND OF THE SHLD INSTRUCTION MUST BE AN ODD ADDRESS FOR PROPER TRANSFER.
DS005688-24
FIGURE 18. Interfacing the DAC1000 to the INS8080A CPU Group
To reset the stack pointer so new data may be output to the same DAC, a POP instruction followed by instructions to in­sure that proper data is in the DAC data register pair before it is “PUSHED” to the DAC should be executed, as the POP instruction will arbitrarily alter the contents of a register pair.
Another double byte write instruction is Store H and L Direct (SHLD), where the HL register pair would temporarily con­tain the DAC data and the two sequential addresses for the DAC are specified by the instruction op code. The auto incre­menting of the DAC address by the SHLD instruction permits the same simple scheme of using address bit 0 to generate the byte number and transfer strobes.
7.2 DAC1006 to MC6820/1 PIA Interface
In
Figure 19
the DAC1006 is interfaced to an M6800 system through an MC6820/1 Peripheral Interface Adapter (PIA). In this case the CS pin of the DAC is grounded since the PIA is already mapped in the 6800 system memory space and no decoding is necessary. Furthermore, by using both Ports A and B of the PIA the 10-bit data transfer, assumed left justi­fied again in two 8-bit bytes, is greatly simplified. The HIGH byte is loaded into Output Register A (ORA) of the PIA, and the LOW byte is loaded into ORB. The 10-bit data transfer to the DAC and the corresponding analog output change occur simultaneously upon CB2 going LOW under program con-
trol. The 10-bit data word in the DAC register will be latched (and hence V HIGH.
will be fixed) when CB2 is brought back
OUT
7.3 Noise Considerations
In low frequency or DC applications, low pass filtering can reduce these noise spikes. This is accomplished by over-compensating the DAC output amplifier by increasing the value of the feedback capacitor (C
C
in
Figure 3
).
In applications requiring a fast transient response from the DAC and op amp, filtering may not be feasible. Adding a latch, DM74LS374, as shown in
Figure 20
isolates the de-
vice from the data bus, thus eliminating noise spikes that oc-
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DAC1006/1007/1008—Simple Hookup for a “Quick Look”
cur every time the data bus changes state. Another method
FIGURE 19. DAC1000 to MC6820/1 PIA Interface
(Continued)
for eliminating noise spikes is to add a sample and hold after the DAC op amp. This also has the advantage of eliminating noise spikes when changing digital codes.
DS005688-25
NOTE: DATA HOLD TIME REDUCED TO THAT OF DM74LS374 (≈10 ns)
FIGURE 20. Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling
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DS005688-55
DAC1006/1007/1008—Simple Hookup for a “Quick Look” (Continued)
DS005688-56
FIGURE 21. Digitally Controlled Amplifier/Attenuator
7.4 Digitally Controlled Amplifier/Attenuator
Figure 21
An unusual application of the DAC,
, applies the in­put voltage via the on-chip feedback resistor. The lower op amp automatically adjusts the V I
is equal to the input current (VIN/RfB). The magnitude
OUT1
of this V in the DAC register. I nitude of V verts I
voltage depends on the digital word which is
REF IN
and the digital word. The second op amp con-
IN
to a voltage, V
OUT2
then depends upon both the mag-
OUT2
, which is given by:
OUT
REF IN
voltage such that
To provide a digitally controlled divider, the output op amp can be eliminated. Ground the I V
is now taken from the lower op amp (which also drives
OUT
the V
input of the DAC). The expression for V
REF
given by
pin of the DAC and
OUT2
OUT
is now
Note that N=0 (or a digital code of all zeros) is not allowed or this will cause the output amplifier to saturate at either
±
V
, depending on the sign of VIN.
MAX
FIGURE 22. Digital to Synchro Converter
DS005688-27
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Book Extract End
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THIS PAGE IS IGNORED IN THE DATABOOK
PrintDate=1998/11/17 PrintTime=11:38:11 46711 ds005688 Rev. No. 4 cmserv Proof 22
22
Ordering Information For Left Justified Data
— 20-pin package.
Accuracy Temperature Range
0˚ to +70˚C
0.05%(10-bit) DAC1006LCN DAC1006LCWM
0.10%(9-bit) DAC1007LCN
0.20%(8-bit) DAC1008LCN
Package Outline N20A M20B
Physical Dimensions inches (millimeters) unless otherwise noted
PrintDate=1998/11/17 PrintTime=11:38:11 46711 ds005688 Rev. No. 4 cmserv
Order Number DAC1006LCWM
NS Package Number M20B
www.national.com23
Proof 23
23
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number DAC1006LCN, DAC1007LCN or DAC1008LCN
NS Package Number N20A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE­VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI­CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys­tems which, (a) are intended for surgical implant into
DAC1006/DAC1007/DAC1008 µP Compatible, Double-Buffered D to A Converters
the body, or (b) support or sustain life, and whose fail­ure to perform when properly used in accordance
2. A critical component in any component of a life support device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
National Semiconductor Corporation
Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com
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Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80
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Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com
National Semiconductor Japan Ltd.
Tel: 81-3-5620-6175 Fax: 81-3-5620-6179
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
PrintDate=1998/11/17 PrintTime=11:38:11 46711 ds005688 Rev. No. 4 cmserv Proof 24
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