Datasheet CY74FCT2574ATQCT, CY74FCT2574ATQC, CY74FCT2574TSOCT, CY74FCT2574TSOC, CY74FCT2574CTSOCT Datasheet (Texas Instruments)
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8-Bit Registers
CY74FCT2374T
CY74FCT2574T
SCCS040 - September 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
Features
• Function and pinout compatible with FCT and F logic
•25Ωoutputseriesresistorstoreducetransmissionline
reflection noise
• FCT-C speed at 5.2 ns max.
• Reduced V
OH
(typically=3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
• Sink current 12 mA
Source current 15 mA
• Edge-triggered D-type inputs
• 250 MHz typical toggle rate
• Extended commercial temp. range of –40˚C to +85˚C
Functional Description
The FCT2374T and FCT2574T are high-speed low-power
octalD-typeflip-flops featuring separate D-type inputsforeach
flip-flop.On-chip termination resistors have been added to the
outputs to reduce system noise caused by reflections. The
FCT2374T and FCT2574T can be used to replace the
FCT374T and FCT574T to reduce noise in an existing design.
Both devices have three-state outputs for bus oriented applications. A buffered clock (CP) and output enable (
OE) are
common to all flip-flops. The FCT2574T is identical to the
FCT2374T except that all the outputs are on one side of the
package and inputs on the other side. The flip-flops contained
in the FCT2374T and FCT2574T will store the state of their
individual D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. When
OE is
LOW, the contents of the flip-flops are availableat the outputs.
When
OE is HIGH, the outputs will be in the high-impedence
state. The state of output enable does not affect the state of
the flip-flops.
The outputs are designed with a power-off disable feature to
allow for liv e insertion of boards.
Logic Block Diagram
Pin Configurations
Logic Symbol
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
13
14
V
CC
FCT2374T-2
15
SOIC/QSOP
Top View
O
0
D
0
D
1
O
2
D
2
D
3
O
3
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
OE
GND
O
7
O
1
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
13
14
V
CC
FCT2374T-4
15
SOIC/QSOP
Top View
D
0
D
1
D
2
D
4
D
5
D
6
D
7
O
1
O
2
O
3
O
4
O
5
O
6
O
7
CP
OE
GND
O
0
D
3
FCT2374T-5
CP
OE
D
0
O
0
D
1
O
1
D
2
O
2
D
3
O
3
D
4
O
4
D
5
O
5
D
6
O
6
D
7
O
7
FCT2374T-6
CP
D
O
0
D
0
CP
OE
CP D
O
1
D
1
CP D
O
2
D
2
CP D
O
3
D
3
CP D
O
4
D
4
CP D
O
5
D
5
CP D
O
6
D
6
CP D
O
7
D
7
QQQQQQQQ
FCT2574
FCT2374T
CY74FCT2374T
CY74FCT2574T
2
Function Table
[1]
Maximum Ratings
[2, 3]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–65°C to +135°C
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Input Voltage ........................................... –0.5V to +7.0V
DC Output Voltage......................................... –0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ......120 mA
Power Dissipation..........................................................0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Inputs Outputs
DCP
OE O
HLH
LLL
XXH Z
Operating Range
Range
Ambient
Temperature V
CC
Commercial –40°C to +85°C 5V ± 5%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.
[5]
Max. Unit
V
OH
Output HIGH Voltage VCC=Min., IOH=–15 mA 2.4 3.3 V
V
OL
Output LOW Voltage VCC=Min., IOL=12 mA 0.3 0.55 V
R
OUT
Output Resistance VCC=Min., IOL=12 mA 20 25 40 Ω
V
IH
Input HIGH Voltage 2.0 V
V
IL
Input LOW Voltage 0.8 V
V
H
Hysteresis
[6]
All inputs 0.2 V
V
IK
Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
I
I
Input HIGH Current VCC=Max., VIN=V
CC
5 µA
I
IH
Input HIGH Current VCC=Max., VIN=2.7V ±1 µA
I
IL
Input LOW Current VCC=Max., VIN=0.5V ±1 µA
I
OZH
Off State HIGH-Level Output
Current
VCC=Max., V
OUT
=2.7V 10 µA
I
OZL
Off State LOW-Level
Output Current
VCC=Max., V
OUT
=0.5V –10 µA
I
OS
Output Short Circuit Current
[7]
VCC=Max., V
OUT
=0.0V –60 –120 –225 mA
I
OFF
Power-Off Disable VCC=0V, V
OUT
=4.5V ±1 µA
Capacitance
[6]
Parameter Description Test Conditions Typ.
[5]
Max. Unit
C
IN
Input Capacitance 5 10 pF
C
OUT
Output Capacitance 9 12 pF
Notes:
1. H = HIGH Voltage Level.
L = LOW Voltage Level
X = Don’t Care
Z = HIGH Impedance
= LOW-to-HIGH clock transition
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
4. T
A
is the “instant on” case temperature.
5. Typical values are at V
CC
=5.0V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values.Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
CY74FCT2374T
CY74FCT2574T
3
Power Supply Characteristics
Parameter Description Test Conditions Typ.
[5]
Max. Unit
I
CC
Quiescent Power Supply Current VCC=Max., VIN≤0.2V,
V
IN≥VCC
–0.2V
0.1 0.2 mA
∆I
CC
Quiescent Power Supply Current
(TTL inputs)
VCC=Max., VIN=3.4V,
[8]
f1=0, Outputs Open
0.5 2.0 mA
I
CCD
Dynamic Power Supply
Current
[9]
VCC=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
OE=GND,
V
IN
≤0.2V or VIN≥VCC–0.2V
0.06 0.12 mA/
MHz
I
C
Total Power Supply Current
[10]
VCC=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f
1
=5 MHz, f0=10 MHz
OE=GND, VIN≤0.2V or VIN≥VCC–0.2V
0.7 1.4 mA
VCC=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f
1
=5 MHz, f0=10 MHz
OE=GND, VIN=3.4V or VIN=GND
1.2 3.4 mA
VCC=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f
1
=2.5 MHz,
Fo=10 MHz,
OE=GND,
V
IN
≤0.2V or VIN≥VCC–0.2V
1.6 3.2
[11]
mA
VCC=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f
1
=2.5 MHz,
Fo=10 MHz,
OE=GND,
V
IN
=3.4V or VIN=GND
3.9 12.2
[11]
mA
Switching Characteristics Over the Operating Range
[11]
Parameter Description
CY74FCT2374T
CY74FCT2574T
CY74FCT2374AT
CY74FCT2574AT
CY74FCT2374CT
CY74FCT2574CT
Unit
Fig.
No.
[13]
Min. Max. Min. Max. Min. Max.
t
PLH
t
PHL
Propagation Delay
Clock to Output
2.0 10.0 2.0 6.5 2.0 5.2 ns 1, 5
t
PZH
t
PZL
Output Enable Time 1.5 12.5 1.5 6.5 1.5 6.2 ns 1, 7, 8
t
PHZ
t
PLZ
Output Disable Time 1.5 8.0 1.5 5.5 1.5 5.0 ns 1, 7, 8
t
S
Set-Up Time, HIGH or LOW
D to CP
2.0 2.0 1.5 ns 4
t
H
Hold Time, HIGH or LOW
D to CP
1.5 1.5 1.0 ns 4
t
W
Clk Pulse Width HIGH or LOW 7.0 5.0 4.0 ns 5
Notes:
8. Per TTL driven input (V
IN
=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. I
C=IQUIESCENT
+ I
INPUTS
+ I
DYNAMIC
IC=ICC+∆ICCDHNT+I
CCD(f0
/2 + f1N1)
I
CC
= Quiescent Current with CMOS input levels
∆I
CC
= Power Supply Current for a TTL HIGH input
(V
IN
=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair
(HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
f
1
= Input signal frequency
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the I
CC
formula. These limits are specified but not tested.
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
CY74FCT2374T
CY74FCT2574T
4
Ordering Information
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
5.2 CY74FCT2374CTQCT Q5 20-Lead (150-Mil) QSOP Commercial
CY74FCT2374CTSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC
6.5 CY74FCT2374ATQCT Q5 20-Lead (150-Mil) QSOP Commercial
CY74FCT2374ATSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC
10.0 CY74FCT2374TSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC Commercial
Ordering Information
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
5.2 CY74FCT2574CTQCT Q5 20-Lead (150-Mil) QSOP Commercial
CY74FCT2574CTSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC
6.5 CY74FCT2574ATQCT Q5 20-Lead (150-Mil) QSOP Commercial
10.0 CY74FCT2574TSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC Commercial
Document #: 38-00345-B
CY74FCT2374T
CY74FCT2574T
5
Package Diagrams
20-Lead Quarter Size Outline Q5
20-Lead (300-Mil) Molded SOIC
S5
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Copyright 2000, Texas Instruments Incorporated
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