Datasheet CY74FCT163827CPVCT, CY74FCT163827CPVC, CY74FCT163827CPACT, CY74FCT163827CPAC, CY74FCT163827APVCT Datasheet (Texas Instruments)

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Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered.
CY74FCT163827
SCCS049 - March 1997 - Revised March 2000
• Low power, pin-compatible replacement for LCX and LPT families
• 5V tolerant inputs and outputs
• 24 mA & 6 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.1 ns
• Latch-up performance exceedsJEDEC standard no. 17
• Typical output skew < 250 ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical Std 883D
•V
V
olp
= 2.7V to 3.6V
CC
(groundbounce)performanceexceedsMil
Functional Description
The CY74FCT163827 is a 20-bit buffer/linedriver that provides high-performance bus interf ace b uff ering for wide data/address paths or buses carrying parity . It can be used as a single 20-bit bufferortwo 10-bit buffers.Each 10-bitbufferhasa pair of NANDed OE for increased flexibility.
The CY74FCT163827 has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The inputs and outputs were designed to be capable of being driven by
5.0V buses, allowing its use in mixed voltage systems as a translator. The outputs are also designed with a power-off disable feature enabling its use in applications requiring live insertion.
20-Bit Buffe
• ESD (HBM) > 2000V
Logic Block Diagrams CY74FCT163827 Pin Configuration
SSOP/TSSOP
Top View
1OE1 1OE2
1A1
2OE1 2OE2
2A1
TO 9 OTHER CHANNELS
TO 9 OTHER CHANNELS
1Y1
FCT163827-1
2Y1
FCT163827-2
1OE1
1Y1 1Y2
GND
1Y3 1Y4
V
1Y5 1Y6 1Y7
GND
1Y8 1Y9
1Y10
2Y1 2Y2 2Y3
GND
2Y4 2Y5 2Y6
V
2Y7 2Y8
GND
2Y9 2Y10
2OE1
1 2 3 4 5 6
CC
7 8 9 10 11 12
13 14
15 16 17 18 19 20 21
CC
22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47
46 45 44 43 42 41 40 39 38 37 36 35 34 33
32 31
30 29
1OE2 1A1 1A2
GND
1A3 1A4
V
CC 1A5 1A6 1A7
GND
1A8 1A9 1A10
2A1 2A2 2A3
GND
2A4 2A5 2A6
V
CC 2A7 2A8
GND
2A9 2A10 2OE2
Copyright © 2000, Texas Instruments Incorporated
CY74FCT163827
Pin Description
Name Description
OE Output Enable Inputs (Active LOW) A Data Inputs Y Three-State Outputs
Function Table
OE
1
L L L L
L L H H H X X Z X H X Z
[1]
Inputs Outputs
OE
2
A Y
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................ 55°C to +125°C
Ambient Temperature with
Power Applied............................................ 55°C to +125°C
Supply Voltage Range..................................... 0.5V to +4.6V
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation..........................................................1.0W
Operating Range
Range
[2, 3]
Ambient
Temperature V
CC
Commercial –40°C to +85°C 2.7V to 3.6V
Electrical Characteristics Over the Operating Range V
Parameter Description Test Conditions Min. Typ.
V
IH
V
IL
V
H
V
IK
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
OFF
I
CC
I
CC
Note:
1. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, Z = HIGH Impedance.
2. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
4. Typical values are at V
5. This parameter is specified but not tested.
6. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internalchip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, I
7. Per TTL driven input; all other inputs at V
Input HIGH Voltage All Inputs 2.0 5.5 V Input LOW Voltage 0.8 V Input Hysteresis
[5]
Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 – 1.2 V Input HIGH Current VCC=Max., VI=5.5 ±1 µA
Input LOW Current VCC=Max., VI=GND ±1 µA High Impedance Output Current
VCC=Max., V
(Three-State Output pins) High Impedance Output Current
VCC=Max., V
(Three-State Output pins) Short Circuit Current
[6]
VCC=Max., V Power-Off Disable VCC=0V, V Quiescent Power Supply Current VIN≤0.2V,
V Quiescent Power Supply Current
VIN=VCC–0.6V (TTL inputs HIGH)
=3.3V, TA = +25˚C ambient.
CC
tests should be performed last.
OS
or GND.
CC
CC
IN>VCC
=2.7V to 3.6V
[4]
100 mV
=5.5V ±1 µA
OUT
=GND ±1 µA
OUT
=GND –60 –135 –240 mA
OUT
4.5V ±100 µA
OUT
VCC=Max. 0.1 10 µA
–0.2V
[7]
VCC=Max. 2.0 30 µA
or ground.
CC
Max. Unit
2
CY74FCT163827
Electrical Characteristics For Balanced Drive Devices Over the Operating Range V
CC
Parameter Description Test Conditions Min. Typ.
I
ODL
I
ODH
V
OH
Output LOW Dynamic Current
Output HIGH Dynamic Current
Output HIGH Voltage VCC=Min., IOH= –0.1 mA VCC–0.2 V
[6]
[6]
VCC=3.3V, VIN=V or VIL, V
OUT
=1.5V
VCC=3.3V, VIN=V or VIL, V
OUT
=1.5V
IH
IH
45 180 mA
–45 –180 mA
VCC=Min., IOH= –8 mA 2.4
[8]
VCC=3.0V, IOH= –24 mA 2.0 3.0 V
V
OL
Output LOW Voltage VCC=Min., IOL= 0.1mA 0.2 V
VCC=Min., IOL= 24 mA 0.3 0.55
Capacitance
Parameter Description Test Conditions Typ.
C
IN
C
OUT
Note:
8. V
OH=VCC
[5]
(TA = +25˚C, f = 1.0 MHz)
[4]
Input Capacitance VIN = 0V 4.5 6.0 pF Output Capacitance V
–0.6V at rated current.
= 0V 5.5 8.0 pF
OUT
Power Supply Characteristics
Parameter Description Test Conditions Typ.
I
CCD
I
C
Dynamic Power Supply Current
Total Power Supply Current
[9]
[10]
VCC=Max.,One Input Toggling, 50% Duty Cycle, Outputs Open,
OE=GND
VCC=Max., f1=10 MHz, 50% DutyCycle,OutputsOpen, One Bit Toggling,
=Max., f1=2.5 MHz, 50%
V
CC
Duty Cycle, Outputs Open, Six­teen Bits Toggling,
OE=GND
OE=GND
V
IN=VCC
V
=GND
IN
V
IN=VCC
V
=GND
IN
V
IN=VCC
V
=GND
IN
V
IN=VCC
V
=GND
IN
V
IN=VCC
V
=GND
IN
or
or
–0.6V or
or
–0.6V or
50 75 µA/MHz
0.5 0.8 mA
0.5 0.8 mA
2.0 3.0
2.0 3.3
=2.7V to 3.6V
[4]
Max. Unit
3.0 V
Max. Unit
[4]
Max. Unit
[11]
[11]
mA
mA
3
CY74FCT163827
Switching Characteristics Over the Operating Range V
=3.0V to 3.6V
CC
[12,13]
CY74FCT163827A CY74FCT163827C
Parameter Description
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SK(O)
Notes:
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. I
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. For V
14. See “Parameter Measurement Information” in the General Information section.
15. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
=I
C
IC=ICC+ICCDHNT+I
= Quiescent Current with CMOS input levels
I
CC
= Power Supply Current for a TTL HIGH input (VIN=3.4V)
I
CC
= Duty Cycle for TTL inputs HIGH
D
H
= Number of TTL inputs at D
N
T
I
= Dynamic Current caused by an input transition pair (HLH or LHL)
CCD
= Clock frequency for registered devices, otherwise zero
f
0
= Input signal frequency
f
1
= Number of inputs changing at f
N
1
All currents are in milliamps and all frequencies are in megahertz.
=2.7, propagation delay, output enable and output disable times should be degraded by 20%.
CC
Propagation Delay Data to Output
Output Enable Time 1.5 6.2 1.5 5.8 ns 1, 7, 8
Output Disable Time 1.5 5.6 1.5 5.2 ns 1, 7, 8
QUIESCENT
Output Skew
+ I
INPUTS
CCD(f0
[15]
+ I
DYNAMIC
/2 + f1N1)
H
1
Min. Max. Min. Max. Unit Fig. No.
1.5 4.8 1.5 4.1 ns 1, 3
0.5 0.5 ns
[14]
Ordering Information CY74FCT163827
Speed
(ns) Ordering Code
4.1 CY74FCT163827CPACT Z56 56-Lead (240-Mil) TSSOP Commercial CY74FCT163827CPVC/PVCT O56 56-Lead (300-Mil) SSOP
4.8 CY74FCT163827APVC/PVCT O56 56-Lead (300-Mil) SSOP Commercial
Package
Name Package Type
Operating
Range
4
Package Diagrams
CY74FCT163827
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package
Z56
5
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Copyright 2000, Texas Instruments Incorporated
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