Texas Instruments CY74FCT163500CPACT, CY74FCT163500CPAC, CY74FCT163500APVCT, CY74FCT163500APVC, CY74FCT163500CPVCT Datasheet
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18-Bit Registered Transceive
r
CY74FCT163500
SCCS066 - June 1997 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
Features
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.6 ns
• Latch-up performance exceedsJEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• TypicalV
olp
(groundbounce)performanceexceedsMil
Std 883D
•V
CC
= 2.7V to 3.6V
Functional Description
The CY74FCT163500 is an 18-bit universal bus transceiver
that can be operated in transparent, latched, or clock modes
bycombining D-type latches and D-type flip-flops. Data flow in
each direction is controlled by output-enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock inputs
(
CLKAB and CLKBA) inputs. For A-to-B data flow, the device
operates in transparent mode when LEAB is HIGH. When
LEAB is LOW,theA data is latched if
CLKAB is held at a HIGH
or LOW logic level. If LEAB is LOW,theA bus data is stored in
the latch/flip-flop on the HIGH-to-LOW transition of
CLKAB.
OEAB performs the output enable function on the B port. Data
flow from B-to-A is similar to that of A-to-B and is controlled by
OEBA, LEBA, and CLKBA.
The CY74FCT163500 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce.The inputs
and outputs are capable of being driven by 5.0V busses,
allowing them to be used in mixed voltage systems as
translators. The outputs are also designed with a power off
disable feature enabling them to be used in applications
requiring live insertion.
GND
LogicBlock Diagram Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
36
35
OEAB
34
SSOP/TSSOP
Top View
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
LEAB
A
1
A
2
A
3
B
1
B
2
B
3
GND
GND
GND
V
CC
A
6
A
7
A
4
A
5
B
4
B
5
B
6
B
7
V
CC
GND
A
10
A
11
A
8
A
9
B
8
B
9
B
11
B
12
GND
A
12
V
CC
A
16
GND
A
14
V
CC
A
15
A
17
TO 17 OTHER CHANNELS
LEAB
OEBA
LEBA
CLKAB
CLKBA
OEAB
C
D
C
D
C
D
C
D
A
1
B
1
25
26
27
28
49
52
51
50
A
13
OEBA
LEBA
GND
A
18
CLKAB
53
56
55
54
B
10
GND
B
14
B
15
B
13
B
16
B
17
GND
B
18
CLKBA
CY74FCT163500
2
Maximum Ratings
[5, 6]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature ................................ −55°C to +125°C
Ambient Temperature with
Power Applied................................................. −55°C to +125°C
Supply Voltage Range..................................... 0.5V to +4.6V
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance. = HIGH-to-LO W Tr ansition.
2. A-to-B data flow is shown, B-to-A data flow is similar but uses
OEBA, LEBA, and CLKBA.
3. Output level before the indicated steady-state input conditions were established.
4. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB w ent LO W .
5. Operation beyond the limits set forth may impair the useful life of the device. Unless noted, these limits are over the operating free-air temperature range.
6. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
Pin Summary
Name Description
OEAB A-to-B Output Enable Input
OEBA B-to-A Output Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input (Active LOW)
CLKBA B-to-A Clock Input (Active LOW)
A A-to-B Data Inputs or B-to-A Three-State Outputs
B B-to-A Data Inputs or A-to-B Three-State Outputs
Function Table
[1, 2]
Inputs Outputs
OEAB LEAB CLKAB A B
L X X X Z
H H X L L
H H X H H
H L L L
H L H H
H L H X B
[3]
H L L X B
[4]
Operating Range
Range
Ambient
Temperature V
CC
Industrial −40°C to +85°C 2.7V to 3.6V
CY74FCT163500
3
Electrical Characteristics Over the Operating Range V
CC
=2.7V to 3.6V
Parameter Description Test Conditions Min. Typ.
[7]
Max. Unit
V
IH
Input HIGH Voltage All Inputs 2.0 5.5 V
V
IL
Input LOW Voltage 0.8 V
V
H
Input Hysteresis
[8]
100 mV
V
IK
Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V
I
IH
Input HIGH Current VCC=Max., VI=5.5V ±1 µA
I
IL
Input LOW Current VCC=Max., VI=GND. ±1 µA
I
OZH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., V
OUT
=5.5V ±1 µA
I
OZL
High Impedance Output Current
(Three-State Output pins)
VCC=Max., V
OUT
=GND ±1 µA
I
ODL
Output LOW Current
[9]
VCC=3.3V, VIN=V
IH
or VIL, V
OUT
=1.5V
45 180 mA
I
ODH
Output HIGH Current
[9]
VCC=3.3V, VIN=V
IH
or VIL, V
OUT
=1.5V
–45 –180 mA
V
OH
Output HIGH Voltage VCC=Min., IOH= –0.1 mA VCC–0.2 V
VCC=3.0V, IOH= –8 mA 2.4 3.0 V
VCC=3.0V, IOH= –24 mA 2.0 3.0 V
V
OL
Output LOW Voltage VCC=Min., IOL= 0.1mA 0.2 V
VCC=Min., IOL= 24 mA 0.3 0.5
I
OS
Short Circuit Current
[9]
VCC=Max., V
OUT
=GND –60 –135 –240 mA
I
OFF
Power-Off Disable VCC=0V, V
OUT
≤4.5V ±100 µA
Capacitance
[8]
(TA = +25˚C, f = 1.0 MHz)
Parameter Description Test Conditions Typ.
[7]
Max. Unit
C
IN
Input Capacitance VIN = 0V 4.5 6.0 pF
C
OUT
Output Capacitance V
OUT
= 0V 5.5 8.0 pF
Notes:
7. Typical values are at V
CC
=3.3V, TA = +25˚C ambient.
8. This parameter is specified but not tested.
9. Not morethan one output shouldbe shorted at a time.Duration of short should notexceed one second. The use of high-speed testapparatus and/or sample
and holdtechniques are preferablein order tominimize internal chip heating and more accurately reflectoperational values. Otherwiseprolonged shorting of
a high output mayraise the chip temperature well abovenormal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
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