Datasheet CY74FCT163H374CPVC, CY74FCT163H374CPAC, CY74FCT163374CPVCT, CY74FCT163374CPVC, CY74FCT163374CPACT Datasheet (Texas Instruments)

4
4

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

CY74FCT16337

CY74FCT163H37

SCCS050 - March 1997 - Revised March 2000

Features

• Low power, pin-compatible replacement for LCX and
LPT families

• 5V tolerant inputs and outputs

• 24 mA balanced drive outputs

• Power-off disable outputs permits live insertion

• Edge-rate control circuitry for reduced noise

• FCT-C speed at 5.2 ns

• Latch-up performance exceedsJEDEC standard no. 17

• Typical output skew < 250 ps

• Industrial temperature range of –40˚C to +85˚C

• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)

• TypicalV
Std 883D

•V

= 2.7V to 3.6V

CC

• ESD (HBM) > 2000V

CY74FCT163H374

• Bus hold on data inputs

• Eliminates the need for external pull-up or pull-down
resistors

• Devices with bus hold are not recommended for trans­lating rail-to-rail CMOS signals to 3.3V logic levels

(groundbounce) performanceexceeds Mil

olp

16-Bit Registers

Functional Description

These devices are 16-bit D-type registers designed for use as
buffered registers in high-speed, low power bus applications.
These devices can be used as twoindependent 8-bit registers
or as a single 16-bit register by connecting the output Enable
(

OE)andClock (CLK) inputs.The outputs are 24-mAbalanced
output driverswith current limiting resistors to reduce the need
for external terminating resistors, and provide for minimal
undershoot and reduced ground bounce. Flow-through pinout
and small shrink packaging aid in simplifying board layout.

The CY74FCT163H374 has “bus hold” on the data inputs,
whichretainstheinput’slast state wheneverthe source driving
the input goes to high impedance. This eliminatesthe need for
pull-up/down resistors and prevents floating inputs.

The CY74FCT163374 is designed with inputs and outputs
capable of being driven by 5.0V buses, allowing its use in
mixed voltage systems as a translator. The outputs are also
designed with a power off disable feature enabling its use in
applications requiring live insertion.

Logic Block Diagrams CY74FCT163374, CY74FCT163H374 Pin Configuration

SSOP/TSSOP

Top View

1

OE

1

CLK

1D1

D

C

1O1

2

OE

2

CLK

2D1

TO 7 OTHER CHANNELS

Lite Drive is a trademark of Cypress Semiconductor Corporation.

D

C

TO 7 OTHER CHANNELS

2O1

OE

1

1O1
1O2

GND

1O3
1O4

V

1O5
1O6

GND

1O7
1O8
2O1
2O2

GND

2O3
2O4

V

2O5
2O6

GND

2O7
2O8

OE

2

1
2
3
4
5
6

CC

7
8
9
10
11
12

13
14

15
16
17
18

CC

19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

CLK

1
1D1
1D2

GND

1D3
1D4

V

CC
1D5
1D6

GND

1D7
1D8
2D1
2D2

GND

2D3
2D4

V

CC
2D5
2D6

GND

2D7
2D8

CLK

2

Copyright © 2000, Texas Instruments Incorporated

CY74FCT163374

CY74FCT163H374

Function Table

[1]

Inputs Outputs

FunctionD CLK OE O

X L H Z High-Z
X H H Z
L L L Load

H L H

Register

L H Z
H H Z

Pin Description

Name Description

D Data Inputs
CLK Clock Inputs
OE Three-State Output Enable Inputs (Active LOW)

[2]

Maximum Ratings

(Above which the useful life may be impaired. For user
guidelines, not tested.)

Storage Temperature .....................................−55°C to +125°C

Ambient Temperature with

Power Applied..................................................−55°C to +125°C

Supply Voltage Range..................................... 0.5V to +4.6V

DC Input Voltage .................................................−0.5V to +7.0V

DC Output Voltage..............................................−0.5V to +7.0V

DC Output Current

(Maximum Sink Current/Pin)...........................−60 to +120 mA

Power Dissipation..........................................................1.0W

Operating Range

Range

Industrial −40°C to +85°C 2.7V to 3.6V

[3, 4]

Ambient

Temperature V

CC

O Three-State Outputs

Electrical Characteristics for Non Bus Hold Devices Over the Operating Range V

Parameter Description Test Conditions Min. Typ.

V

IH

V

IL

V

H

V

IK

I

IH

I

IL

I

OZH

I

OZL

I

OS

I

OFF

I

CC

∆I

CC

Notes:

1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance. = LOW-to-HIGH Transition.

2. On the CY74FCT163H374, these pins have “bus hold.”

3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.

4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V

5. Typical values are at VCC=3.3V, TA = +25˚C ambient.

6. This parameter is specified but not tested.

7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferablein order to minimize internal chip heating and more accurately reflect operational values.Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.

8. Per TTL driven input; all other inputs at V

Input HIGH Voltage All Inputs 2.0 5.5 V
Input LOW Voltage 0.8 V
Input Hysteresis

[6]

Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
Input HIGH Current VCC=Max., VI=5.5 ±1 µA

Input LOW Current VCC=Max., VI=GND ±1 µA
High Impedance Output Current

(Three-State Output pins)
High Impedance Output Current

(Three-State Output pins)
Short Circuit Current

[7]

Power-Off Disable VCC=0V, V
Quiescent Power Supply Current VIN≤0.2V,

Quiescent Power Supply Current

VCC=Max., V

VCC=Max., V

VCC=Max., V

OUT

V

IN>VCC

–0.2V

VIN=VCC–0.6V

=5.5V ±1 µA

OUT

=GND ±1 µA

OUT

=GND –60 –135 –240 mA

OUT

≤4.5V ±100 µA

VCC=Max. 0.1 10 µA

[8]

VCC=Max. 2.0 30 µA

(TTL inputs HIGH)

or ground

CC

or GND.

CC

=2.7V to 3.6V

CC

[5]

100 mV

Max. Unit

2

CY74FCT163374

CY74FCT163H374

Electrical Characteristics For Bus Hold Devices Over the Operating Range V

=2.7V to 3.6V

CC

Parameter Description Test Conditions Min. Typ.

V

IH

V

IL

V

H

V

IK

I

IH

I

IL

I

BBH

I

BBL

I

BHHO

I

BHLO

I

OZH

I

OZL

I

OS

I

OFF

I

CC

∆

ICC

Input HIGH Voltage All Inputs 2.0 V
Input LOW Voltage 0.8 V
Input Hysteresis

[6]

Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 – 1.2 V
Input HIGH Current VCC=Max., VI=V

CC

Input LOW Current ±100 µA
Bus Hold Sustain Current on Bus Hold Input

[9]

VCC=Min. VI=2.0V –50 µA

VI=0.8V +50 µA

Bus Hold Overdrive Current on Bus Hold In-

[9]

put
High Impedance Output Current

(Three-State Output pins)
High Impedance Output Current

(Three-State Output pins)
Short Circuit Current

[7]

Power-Off Disable VCC=0V, V

VCC=Max., VI=1.5V ±500 µA

VCC=Max., V

VCC=Max., V

VCC=Max., V

OUT=VCC

=GND ±1 µA

OUT

=GND –60 –135 –240 mA

OUT

≤4.5V ±100 µA

OUT

Quiescent Power Supply Current VIN<0.2V VCC=Max. +40 µA
Quiescent Power supply Current

VIN=VCC–0.6V

[8]

VCC=Max. +350 µA

(TTL inputs HIGH)

[5]

Max. Unit

CC

V

100 mV

±100 µA

±1 µA

Electrical Characteristics For Balanced Drive Devices Over the Operating Range V

CC

Parameter Description Test Conditions Min. Typ.

I

ODL

I

ODH

V

OH

Output LOW Dynamic Current

Output HIGH Dynamic Current

Output HIGH Voltage VCC=Min., IOH= –0.1 mA VCC–0.2 V

[7]

[7]

VCC=3.3V, VIN=V
or VIL, V

OUT

VCC=3.3V, VIN=V
or VIL, V

OUT

=1.5V

=1.5V

IH

IH

VCC=Min., IOH= –8 mA 2.4

45 110 mA

–45 –110 mA

[10]

VCC=3.0V, IOH= –24 mA 2.0 3.0 V

V

OL

Output LOW Voltage VCC=Min., IOL= 0.1mA 0.2 V

VCC=Min., IOL= 24 mA 0.3 0.55

Notes:

9. Pins with bus hold are described in Pin Description.

10. V

Capacitance

Parameter Description Test Conditions Typ.

C

IN

C

OUT

–0.6V at rated current.

OH=VCC

[6]

(TA = +25˚C, f = 1.0 MHz)

[5]

Input Capacitance VIN = 0V 4.5 6.0 pF
Output Capacitance V

= 0V 5.5 8.0 pF

OUT

=2.7V to 3.6V

[5]

Max. Unit

3.0 V

Max. Unit

3

CY74FCT163374

CY74FCT163H374

Power Supply Characteristics

Parameter Description Test Conditions Typ.

I

CCD

I

C

Dynamic Power Supply
Current

Total Power Supply
Current

[11]

[12]

VCC=Max., One Input Toggling,
50% Duty Cycle,
Outputs Open,

OE=GND

VCC=Max., f1=10 MHz, 50%
DutyCycle,Outputs Open, One
Bit Toggling,

OE=GND

VCC=Max., f1=2.5 MHz, 50%
Duty Cycle, Outputs Open, Six­teen Bits Toggling,

OE=GND

VIN=VCCor
V

=GND

IN

VIN=VCC or
V

=GND

IN

VIN=VCC–0.6V or
V

=GND

IN

VIN=VCC or
V

=GND

IN

VIN=VCC–0.6V or
V

=GND

IN

[5]

Max. Unit

50 75 µA/MHz

0.5 0.8 mA

0.5 0.8 mA

2.0 3.0

2.0 3.3

[13]

[13]

mA

mA

Switching Characteristics Over the Operating Range V

=3.0V to 3.6V

CC

CY74FCT163374A

CY74FCT163H374A

Parameter Description

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

SU

t

H

t

SK(O)

Notes:

11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

12. I

13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.

14. Minimum limits are specified but not tested on Propagation Delays.

15. For V

16. See “Parameter Measurement Information” in the General Information section.

17. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.

=I

C

IC=ICC+∆ICCDHNT+I

= Quiescent Current with CMOS input levels

I

CC

= Power Supply Current for a TTL HIGH input (VIN=3.4V)

∆I

CC

= Duty Cycle for TTL inputs HIGH

D

H

= Number of TTL inputs at D

N

T

I

= Dynamic Current caused by an input transition pair (HLH or LHL)

CCD

= Clock frequency for registered devices, otherwise zero

f

0

= Input signal frequency

f

1

= Number of inputs changing at f

N

1

All currents are in milliamps and all frequencies are in megahertz.

=2.7, propagation delay, output enable and output disable times should be degraded by 20%.

CC

PropagationDelayClockto
Output

Output Enable Time 1.5 6.5 1.5 5.5 ns 1, 7, 8

Output Disable Time 1.5 5.5 1.5 5.0 ns 1, 7, 8

Input Setup time 2.0 2.0 ns 1, 4
Input Hold time 1.5 - 1.5 - ns 1. 4

QUIESCENT

Output Skew

+ I

INPUTS

CCD(f0

[17]

+ I

DYNAMIC

/2 + f1N1)

H

1

Min. Max. Min. Max. Unit Fig. No.

1.5 6.5 1.5 5.2 ns 1, 3

0.5 0.5 ns —

[14,15]

CY74FCT163374C

CY74FCT163H374C

[16]

4

CY74FCT163374

CY74FCT163H374

Switching Characteristics Over the Operating Range V

CY74FCT163LD374

CY74FCT163LDH374

Parameter Description

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

SU

t

H

t

SK(O)

Note:

18. For Lite Drive devices the load capacitance is 30 pF. For all others it is 50 pF.

PropagationDelayClockto
Q Output

Output Enable Time 1.5 12.5 1.5 6.5 ns 1, 7, 8

Output Disable Time 1.5 8.0 1.5 5.5 ns 1, 7, 8

Input Setup time 2.0 2.0 ns 1, 4
Input Hold time 1.5 1.5 ns 1, 4
Output Skew

[17]

Min. Max. Min. Max. Unit Fig. No.

1.5 10 1.5 6.5 ns 1, 3

=3.0V to 3.6V

CC

[18]

0.5 0.5 ns —

[14,15]

CY74FCT163LD374A

CY74FCT163LDH374A

[18]

Ordering Information CY74FCT163374

Speed

(ns) Ordering Code

5.2 CY74FCT163374CPACT Z48 48-Lead (240-Mil) TSSOP Industrial
CY74FCT163374CPVC/PVCT O48 48-Lead (300-Mil) SSOP

6.5 CY74FCT163374APACT Z48 48-Lead (240-Mil) TSSOP Industrial

Package

Name Package Type

[16]

Operating

Range

Ordering Information CY74FCT163H374

Speed

(ns) Ordering Code

5.2 74FCT163H374CPACT Z48 48-Lead (240-Mil) TSSOP Industrial
CY74FCT163H374CPVC O48 48-Lead (300-Mil) SSOP
74FCT163H374CPVCT O48 48-Lead (300-Mil) SSOP

Package

Name Package Type

Operating

Range

5

D

Package Diagrams

CY74FCT163374

CY74FCT163H374

48-Lead Shrunk Small Outline Package O48

48-Lead Thin Shrunk Small Outline Package

Z48

6

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Copyright  2000, Texas Instruments Incorporated