Texas Instruments CY74FCT163373CPVCT, CY74FCT163373CPVC, CY74FCT163373CPACT, CY74FCT163373CPAC Datasheet
16-Bit Latch
CY74FCT163373
SCCS053 - March 1997 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
Features
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.2 ns
• Latch-up performance exceedsJEDEC standard no. 17
• Typical output skew < 250 ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical
V
olp
(groundbounce)performanceexceedsMil
Std 883D
•V
CC
= 2.7V to 3.6V
• ESD (HBM) > 2000V
Functional Description
This device is a 16-bit, D-type latch, designed for use in bus
applications requiring high speed and low power. It can either
be used as twoindependent 8-bit latches,or asa single 16-bit
latch by connecting the Output Enable (
OE) and Latch (LE)
inputs. The outputs are 24-mA balanced output drivers with
current limiting resistors to reduce the need for external
terminating resistors and provide for minimal undershoot and
reduced groundbounce. Flow-through pinout and small shrink
packaging aid in simplifying board layout.
The CY74FCT163373 is designed with inputs and outputs
capable of being driven by 5.0V buses, allowing its use in
mixed voltage systems as a translator. The outputs are also
designed with a power off disable feature enabling its use in
applications requiring live insertion.
Logic Block Diagrams CY74FCT163373
Pin
Configuration
D
C
1
OE
1
LE
1D1
1O1
TO 7 OTHERCHANNELS
D
C
2
OE
2
LE
2D1
2O1
GND
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
1
OE
34
SSOP/TSSOP
Top View
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
1O1
1O2
1O3
1O4
1D1
1D2
1D3
1D4
1
LE
GND
GND
V
CC
1O7
1O8
1O5
1O6
1D5
1D6
1D7
1D8
V
CC
GND
GND
2O3
2O4
2O1
2O2
2D1
2D2
2D3
2D4
GND
GND
V
CC
2O7
2O8
2O5
2O6
2D5
2D6
2D7
2D8
V
CC
GND
2
OE
2
LE
TO 7 OTHERCHANNELS
CY74FCT163373
2
Maximum Ratings
[2, 3]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature......................................−55°C to +125°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Supply Voltage Range..................................... 0.5V to +4.6V
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation..........................................................1.0W
Pin Description
Name Description
D Data Inputs
LE Latch Enable Inputs (Active HIGH)
OE Output Enable Inputs (Active LOW)
O Three-State Outputs
Function Table
[1]
Inputs Outputs
D LE OE O
H H L H
L H L L
X L L Q
0
X X H Z
Operating Range
Range
Ambient
Temperature V
CC
Industrial −40°C to +85°C 2.7V to 3.6V
Electrical Characteristics for Non Bus Hold Devices Over the Operating Range V
CC
=2.7V to 3.6V
Parameter Description Test Conditions Min. Typ.
[4]
Max. Unit
V
IH
Input HIGH Voltage All Inputs 2.0 5.5 V
V
IL
Input LOW Voltage 0.8 V
V
H
Input Hysteresis
[5]
100 mV
V
IK
Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
I
IH
Input HIGH Current VCC=Max., VI=5.5 ±1 µA
I
IL
Input LOW Current VCC=Max., VI=GND ±1 µA
I
OZH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., V
OUT
=5.5V ±1 µA
I
OZL
High Impedance Output Current
(Three-State Output pins)
VCC=Max., V
OUT
=GND ±1 µA
I
OS
Short Circuit Current
[6]
VCC=Max., V
OUT
=GND –60 –135 –240 mA
I
OFF
Power-Off Disable VCC=0V, V
OUT
≤4.5V ±100 µA
I
CC
Quiescent Power Supply Current VIN≤0.2V,
V
IN>VCC
–0.2V
VCC=Max. 0.1 10 µA
∆I
CC
Quiescent Power Supply Current
(TTL inputs HIGH)
VIN=VCC–0.6V
[7]
VCC=Max. 2.0 30 µA
Note:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance. Q
0
=Previous state of flip-flop.
2. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
3. With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
4. Typical values are at V
CC
=3.3V, TA = +25˚C ambient.
5. This parameter is specified but not tested.
6. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internalchip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
7. Per TTL driven input; all other inputs at V
CC
or GND.
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