Texas Instruments Chipcon Products CC2420 User Manual

CC2420

SWRS041B Page 1 of 89

2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver

Applications

 2.4 GHz IEEE 802.15.4 systems
 ZigBee systems
 Home/building automation
 Industrial Control

 Wireless sensor networks
 PC peripherals
 Consumer Electronics

Product Description

The

CC2420

is a true single-chip 2.4 GHz
IEEE 802.15.4 compliant RF transceiver
designed for low power and low voltage
wireless applications.

CC2420

includes a
digital direct sequence spread spectrum
baseband modem providing a spreading
gain of 9 dB and an effective data rate of
250 kbps.

The

CC2420

is a low-cost, highly integrated
solution for robust wireless communication
in the 2.4 GHz unlicensed ISM band. It
complies with worldwide regulations
covered by ETSI EN 300 328 and EN 300
440 class 2 (Europe), FCC CFR47 Part 15
(US) and ARIB STD-T66 (Japan).

The

CC2420

provides extensive hardware
support for packet handling, data
buffering, burst transmissions, data
encryption, data authentication, clear
channel assessment, link quality indication
and packet timing information. These

features reduce the load on the host
controller and allow

CC2420

to interface

low-cost microcontrollers.

The configuration interface and transmit /
receive FIFOs of

CC2420

are accessed via

an SPI interface. In a typical application

CC2420

will be used together with a
microcontroller and a few external passive
components.

CC2420

is based on Chipcon’s SmartRF­03 technology in 0.18 m CMOS.

Key Features

 True single-chip 2.4 GHz IEEE

802.15.4 compliant RF transceiver
with baseband modem and MAC
support

 DSSS baseband modem with 2

MChips/s and 250 kbps effective data
rate.

 Suitable for both RFD and FFD

operation

 Low current consumption (RX: 18.8

mA, TX: 17.4 mA)

 Low supply voltage (2.1 – 3.6 V) with

integrated voltage regulator

 Low supply voltage (1.6 – 2.0 V) with

external voltage regulator

 Programmable output power
 No external RF switch / filter needed
 I/Q low-IF receiver
 I/Q direct upconversion transmitter
 Very few external components
 128(RX) + 128(TX) byte data buffering
 Digital RSSI / LQI support
 Hardware MAC encryption (AES-128)
 Battery monitor
 QLP-48 package, 7x7 mm
 Complies with ETSI EN 300 328, EN

300 440 class 2, FCC CFR-47 part 15
and ARIB STD-T66

 Powerful and flexible development

tools available

CC2420

SWRS041B Page 2 of 89

Table of contents

1 Abbreviations_________________________________________________________________5
2 References ___________________________________________________________________6
3 Features _____________________________________________________________________ 7
4 Absolute Maximum Ratings_____________________________________________________8
5 Operating Conditions __________________________________________________________8
6 Electrical Specifications ________________________________________________________9

6.1 Overall___________________________________________________________________9

6.2 Transmit Section ___________________________________________________________9

6.3 Receive Section___________________________________________________________10

6.4 RSSI / Carrier Sense _______________________________________________________11

6.5 IF Section _______________________________________________________________11

6.6 Frequency Synthesizer Section _______________________________________________11

6.7 Digital Inputs/Outputs______________________________________________________12

6.8 Voltage Regulator _________________________________________________________13

6.9 Battery Monitor___________________________________________________________13

6.10 Power Supply ____________________________________________________________13

7 Pin Assignment ______________________________________________________________15
8 Circuit Description ___________________________________________________________17
9 Application Circuit ___________________________________________________________19

9.1 Input / output matching_____________________________________________________19

9.2 Bias resistor______________________________________________________________19

9.3 Crystal __________________________________________________________________19

9.4 Voltage regulator__________________________________________________________19

9.5 Power supply decoupling and filtering _________________________________________19

10 IEEE 802.15.4 Modulation Format ____________________________________________24
11 Configuration Overview _____________________________________________________25
12 Evaluation Software ________________________________________________________26
13 4-wire Serial Configuration and Data Interface__________________________________27

13.1 Pin configuration__________________________________________________________27

13.2 Register access____________________________________________________________27

13.3 Status byte_______________________________________________________________28

13.4 Command strobes _________________________________________________________29

13.5 RAM access______________________________________________________________29

13.6 FIFO access______________________________________________________________31

13.7 Multiple SPI access ________________________________________________________31

14 Microcontroller Interface and Pin Description __________________________________32

14.1 Configuration interface _____________________________________________________32

14.2 Receive mode ____________________________________________________________33

14.3 RXFIFO overflow _________________________________________________________33

14.4 Transmit mode____________________________________________________________34

14.5 General control and status pins _______________________________________________35

15 Demodulator, Symbol Synchroniser and Data Decision ___________________________35
16 Frame Format _____________________________________________________________36

16.1 Synchronisation header _____________________________________________________36

16.2 Length field______________________________________________________________37

16.3 MAC protocol data unit_____________________________________________________37

16.4 Frame check sequence ______________________________________________________38

CC2420

SWRS041B Page 3 of 89

17 RF Data Buffering__________________________________________________________39

17.1 Buffered transmit mode_____________________________________________________39

17.2 Buffered receive mode _____________________________________________________39

17.3 Unbuffered, serial mode ____________________________________________________40

18 Address Recognition ________________________________________________________41
19 Acknowledge Frames _______________________________________________________41
20 Radio control state machine__________________________________________________43
21 MAC Security Operations (Encryption and Authentication) _______________________45

21.1 Keys____________________________________________________________________45

21.2 Nonce / counter ___________________________________________________________45

21.3 Stand-alone encryption _____________________________________________________46

21.4 In-line security operations___________________________________________________46

21.5 CTR mode encryption / decryption ____________________________________________47

21.6 CBC-MAC_______________________________________________________________47

21.7 CCM ___________________________________________________________________47

21.8 Timing__________________________________________________________________48

22 Linear IF and AGC Settings__________________________________________________48
23 RSSI / Energy Detection _____________________________________________________48
24 Link Quality Indication _____________________________________________________49
25 Clear Channel Assessment ___________________________________________________50
26 Frequency and Channel Programming_________________________________________50
27 VCO and PLL Self-Calibration _______________________________________________51

27.1 VCO____________________________________________________________________51

27.2 PLL self-calibration________________________________________________________51

28 Output Power Programming _________________________________________________51
29 Voltage Regulator __________________________________________________________51
30 Battery Monitor____________________________________________________________52
31 Crystal Oscillator __________________________________________________________53
32 Input / Output Matching ____________________________________________________54
33 Transmitter Test Modes _____________________________________________________54

33.1 Unmodulated carrier _______________________________________________________54

33.2 Modulated spectrum _______________________________________________________55

34 System Considerations and Guidelines _________________________________________57

34.1 Frequency hopping and multi-channel systems___________________________________57

34.2 Data burst transmissions ____________________________________________________57

34.3 Crystal accuracy and drift ___________________________________________________57

34.4 Communication robustness __________________________________________________57

34.5 Communication security ____________________________________________________57

34.6 Low-cost systems _________________________________________________________58

34.7 Battery operated systems____________________________________________________58

34.8 BER / PER measurements___________________________________________________58

35 PCB Layout Recommendations _______________________________________________59
36 Antenna Considerations _____________________________________________________59
37 Configuration Registers _____________________________________________________61
38 Test Output Signals_________________________________________________________81
39 Package Description (QLP 48)________________________________________________83
40 Recommended layout for package (QLP 48) ____________________________________84

CC2420

SWRS041B Page 4 of 89

40.1 Package thermal properties __________________________________________________84

40.2 Soldering information ______________________________________________________84

40.3 Plastic tube specification____________________________________________________85

40.4 Carrier tape and reel specification _____________________________________________85

41 Ordering Information_______________________________________________________85
42 General Information ________________________________________________________86

42.1 Document History_________________________________________________________86

42.2 Product Status Definitions___________________________________________________87

43 Address Information________________________________________________________88
44 TI Worldwide Technical Support _____________________________________________88

CC2420

SWRS041B Page 5 of 89

1 Abbreviations

ADC - Analog to Digital Converter
AES - Advanced Encryption Standard
AGC - Automatic Gain Control
ARIB - Association of Radio Industries and Businesses
BER - Bit Error Rate
CBC-MAC - Cipher Block Chaining Message Authentication Code
CCA - Clear Channel Assessment
CCM - Counter mode + CBC-MAC
CFR - Code of Federal Regulations
CSMA-CA - Carrier Sense Multiple Access with Collision Avoidance
CTR - Counter mode (encryption)
CW - Continuous Wave
DAC - Digital to Analog Converter
DSSS - Direct Sequence Spread Spectrum
ESD - Electro Static Discharge
ESR - Equivalent Series Resistance
EVM - Error Vector Magnitude
FCC - Federal Communications Commission
FCF - Frame Control Field
FIFO - First In First Out
FFCTRL - FIFO and Frame Control
HSSD - High Speed Serial Debug
IEEE - Institute of Electrical and Electronics Engineers
IF - Intermediate Frequency
ISM - Industrial, Scientific and Medical
ITU-T - International Telecommunication Union – Telecommunication
Standardization Sector
I/O - Input / Output
I/Q - In-phase / Quadrature-phase
kbps - kilo bits per second
LNA - Low-Noise Amplifier
LO - Local Oscillator
LQI - Link Quality Indication
LSB - Least Significant Bit / Byte
MAC - Medium Access Control
MFR - MAC Footer
MHR - MAC Header
MIC - Message Integrity Code
MPDU - MAC Protocol Data Unit
MSDU - MAC Service Data Unit
NA - Not Available
NC - Not Connected
O-QPSK - Offset - Quadrature Phase Shift Keying
PA - Power Amplifier
PCB - Printed Circuit Board
PER - Packet Error Rate
PHY - Physical Layer
PHR - PHY Header
PLL - Phase Locked Loop
PSDU - PHY Service Data Unit
QLP - Quad Leadless Package
RAM - Random Access Memory
RBW - Resolution BandWidth
RF - Radio Frequency
RSSI - Receive Signal Strength Indicator
RX - Receive

CC2420

SWRS041B Page 6 of 89

SHR - Synchronisation Header
SPI - Serial Peripheral Interface
TBD - To Be Decided / To Be Defined
T/R - Transmit / Receive
TX - Transmit
VCO - Voltage Controlled Oscillator
VGA - Variable Gain Amplifier

2 References

[1] IEEE std. 802.15.4 - 2003: Wireless Medium Access Control (MAC) and

Physical Layer (PHY) specifications for Low Rate Wireless Personal Area
Networks (LR-WPANs)

http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf

[2] NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal

Information Processing Standards Publication 197, US Department of
Commerce/N.I.S.T., November 26, 2001. Available from the NIST website.

http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf

[3] R. Housley, D. Whiting, N. Ferguson, Counter with CBC-MAC (CCM),

submitted to NIST, June 3, 2002. Available from the NIST website.

http://csrc.nist.gov/CryptoToolkit/modes/proposedmodes/ProposedModesPa
ge.html

CC2420

SWRS041B Page 7 of 89

3 Features

 2400 – 2483.5 MHz RF Transceiver

 Direct Sequence Spread

Spectrum (DSSS) transceiver

 250 kbps data rate, 2 MChip/s

chip rate

 O-QPSK with half sine pulse

shaping modulation

 Very low current consumption

(RX: 18.8 mA, TX: 17.4 mA)

 High sensitivity (-95 dBm)
 High adjacent channel rejection

(30/45 dB)

 High alternate channel rejection

(53/54 dB)

 On-chip VCO, LNA and PA
 Low supply voltage (2.1 – 3.6 V)

with on-chip voltage regulator

 Programmable output power
 I/Q low-IF soft decision receiver
 I/Q direct up-conversion

transmitter

 Separate transmit and receive FIFOs

 128 byte transmit data FIFO
 128 byte receive data FIFO

 Very few external components

 Only reference crystal and a

minimised number of passives

 No external filters needed

 Easy configuration interface

 4-wire SPI interface
 Serial clock up to 10 MHz

 802.15.4 MAC hardware support:

 Automatic preamble generator
 Synchronisation word

insertion/detection

 CRC-16 computation and

checking over the MAC payload

 Clear Channel Assessment
 Energy detection / digital RSSI
 Link Quality Indication
 Full automatic MAC security

(CTR, CBC-MAC, CCM)

 802.15.4 MAC hardware security:

 Automated security operations

within the receive and transmit
FIFOs.

 CTR mode encryption / decryption
 CBC-MAC authentication
 CCM encryption / decryption and

authentication

 Stand-alone AES encryption

 Development tools available

 Fully equipped development kit
 Demonstration board reference

design with microcontroller code



Easy-to-use software for

generating the

CC2420

configu-

ration data

 Small size QLP-48 package, 7 x 7 mm
 Complies with EN 300 328, EN 300

440 class 2, FCC CFR47 part 15 and
ARIB STD-T66

CC2420

SWRS041B Page 8 of 89

4 Absolute Maximum Ratings

Parameter Min. Max. Units Condition

Supply voltage for on-chip voltage regulator,
VREG_IN pin 43.

-0.3 3.6 V

Supply voltage (VDDIO) for digital I/Os, DVDD3.3,
pin 25.

-0.3 3.6 V

Supply voltage (VDD) on AVDD_VCO, DVDD1.8,
etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35,
37, 44 and 48)

−0.3 2.0 V

Voltage on any digital I/O pin, (pin no. 21, 27-34
and 41)

-0.3 VDDIO+0.3, max 3.6 V

Voltage on any other pin, (pin no. 6, 7, 8, 11, 12,
13, 16, 36, 38, 39, 40, 45, 46 and 47)

-0.3 VDD+0.3, max 2.0 V

Input RF level 10 dBm

Storage temperature range −50 150

C

Reflow solder temperature 260

C

T = 10 s

The absolute maximum ratings given
above should under no circumstances be
violated. Stress exceeding one or more of

the limiting values may cause permanent
damage to the device.

Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.

5 Operating Conditions

Parameter Min. Typ. Max. Units Condition

Supply voltage for on-chip voltage regulator,
VREG_IN pin 43.

2.1 3.6 V

Supply voltage (VDDIO) for digital I/Os, DVDD3.3,
pin 25 .

1.6 3.6 V The digital I/O voltage (DVDD3.3 pin)

must match the external interfacing
circuit (e.g. microcontroller).

Supply voltage (VDD) on AVDD_VCO, DVDD1.8,
etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35,
37, 44 and 48)

1.6 1.8 2.0 V The typical application uses regulated

1.8 V supply generated by the on-chip
voltage regulator.

Operating ambient temperature range, TA −40 85

C

CC2420

SWRS041B Page 9 of 89

6 Electrical Specifications

Measured on CC2420 EM with transmission line balun, TA = 25 C, DVDD3.3 and VREG_IN = 3.3 V, internal
voltage regulator used if nothing else stated.

6.1 Overall

Parameter Min. Typ. Max. Unit Condition / Note

RF Frequency Range 2400 2483.5 MHz Programmable in 1 MHz steps, 5

MHz steps for compliance with [1]

6.2 Transmit Section

Parameter Min. Typ. Max. Unit Condition / Note

Transmit bit rate 250

250 kbps As defined by [1]

Transmit chip rate

2000 2000 kChips/s As defined by [1]

Nominal output power -3 0 dBm

Delivered to a single ended 50 
load through a balun.

[1] requires minimum –3 dBm

Programmable output power range

24 dB The output power is

programmable in 8 steps from
approximately –24 to 0 dBm.

Harmonics

2

nd

harmonic

3

rd

harmonic

-44

-64

dBm

dBm

Measured conducted with 1 MHz
resolution bandwidth on spectrum
analyser. At max output power
delivered to a single ended 50 
load through a balun. See page

54.

Spurious emission

30 - 1000 MHz
1– 12.75 GHz

1.8 – 1.9 GHz

5.15 – 5.3 GHz

-56

-44

-56

-51

dBm
dBm
dBm
dBm

Maximum output power.

Complies with EN 300 328, EN
300 440, FCC CFR47 Part 15
and ARIB STD-T-66

Error Vector Magnitude (EVM) 11 % Measured as defined by [1]

[1] requires max. 35 %

Optimum load impedance 95

+ j187



Differential impedance as seen
from the RF-port (RF_P and
RF_N) towards the antenna. For
matching details see the Input /
Output Matching section on page

54.

CC2420

SWRS041B Page 10 of 89

6.3 Receive Section

Parameter Min. Typ. Max. Unit Condition / Note

Receiver Sensitivity

-90

-95

dBm

PER = 1%, as specified by [1]

Measured in a 50 single-ended
load through a balun.

[1] requires –85 dBm

Saturation (maximum input level) 0 10 dBm PER = 1%, as specified by [1]

Measured in a 50 single–ended
load through a balun.

[1] requires –20 dBm

Adjacent channel rejection

+ 5 MHz channel spacing

45

dB

Wanted signal @ -82 dBm,
adjacent modulated channel at
+5 MHz, PER = 1 %, as specified
by [1].

[1] requires 0 dB

Adjacent channel rejection

- 5 MHz channel spacing

30

dB

Wanted signal @ -82 dBm,
adjacent modulated channel at

-5 MHz, PER = 1 %, as specified
by [1].

[1] requires 0 dB

Alternate channel rejection

+ 10 MHz channel spacing

54

dB

Wanted signal @ -82 dBm,
adjacent modulated channel at
+10 MHz, PER = 1 %, as
specified by [1]

[1] requires 30 dB

Alternate channel rejection

- 10 MHz channel spacing

53

dB

Wanted signal @ -82 dBm,
adjacent modulated channel at

-10 MHz, PER = 1 %, as
specified by [1]

[1] requires 30 dB

Channel rejection

≥ + 15 MHz

≤ - 15 MHz

62

62

dB

dB

Wanted signal @ -82 dBm.
Undesired signal is an IEEE

802.15.4 modulated channel,
stepped through all channels
from 2405 to 2480 MHz. Signal
level for PER = 1%.

Co-channel rejection

-3

dB

Wanted signal @ -82 dBm.
Undesired signal is an IEEE

802.15.4 modulated at the same
frequency as the desired signal.
Signal level for PER = 1%.

Blocking / Desensitisation

+/- 5 MHz from band edge
+/- 20 MHz from band edge
+/- 30 MHz from band edge
+/- 50 MHz from band edge

-28

-28

-27

-28

dBm
dBm
dBm
dBm

Wanted signal 3 dB above the
sensitivity level, CW jammer,
PER = 1%. Complies with EN
300 440 class 2.

Spurious emission

30 – 1000 MHz
1 – 12.75 GHz

-73

-58

dBm
dBm

Conducted measurement in a 50
 single ended load. Measured
according to EN 300 328, EN 300
440 class 2, FCC CFR47, Part 15
and ARIB STD-T-66

CC2420

SWRS041B Page 11 of 89

Parameter Min. Typ. Max. Unit Condition / Note

Frequency error tolerance -300 300 kHz Difference between centre

frequency of the received RF
signal and local oscillator
frequency

[1] requires 200 kHz

Symbol rate error tolerance 120 ppm Difference between incoming

symbol rate and the internally
generated symbol rate

[1] requires 80 ppm

Data latency 3

s

Processing delay in receiver.
Time from complete transmission
of SFD until complete reception
of SFD, i.e. from SFD goes active
on transmitter until active on
receiver.

6.4 RSSI / Carrier Sense

Parameter Min. Typ. Max. Unit Condition / Note

Carrier sense level

− 77 dBm Programmable in

RSSI.CCA_THR

RSSI dynamic range

100 dB The range is approximately from

–100 dBm to 0 dBm

RSSI accuracy

 6

dB See page 48 for details

RSSI linearity

 3

dB

RSSI average time 128

s

8 symbol periods, as specified by
[1]

6.5 IF Section

Parameter Min. Typ. Max. Unit Condition / Note

Intermediate frequency (IF) 2 MHz

6.6 Frequency Synthesizer Section

Parameter Min. Typ. Max. Unit Condition / Note

Crystal oscillator frequency

16 MHz See page 53 for details.

Crystal frequency accuracy
requirement

- 40

40 ppm Including aging and temperature

dependency, as specified by [1]

Crystal operation

Parallel

C381 and C391 are loading

capacitors, see page 53

CC2420

SWRS041B Page 12 of 89

Parameter Min. Typ. Max. Unit Condition / Note

Crystal load capacitance

12 16 20 pF 16 pF recommended

Crystal ESR

60



Crystal oscillator start-up time 1.0 ms

16 pF load

Phase noise

−109

−117

−117

−117

dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz

Unmodulated carrier

At ±1 MHz offset from carrier
At ±2 MHz offset from carrier
At ±3 MHz offset from carrier
At ±5 MHz offset from carrier

PLL loop bandwidth 100 kHz

PLL lock time

192

s

The startup time from the crystal
oscillator is running and RX / TX
turnaround time

6.7 Digital Inputs/Outputs

Parameter Min. Typ. Max. Unit Condition / Note

General

Signal levels are referred to the
voltage level at pin DVDD3.3

Logic "0" input voltage

0 0.3*

DVDD

V

Logic "1" input voltage

0.7*
DVDD

DVDD V

Logic "0" output voltage 0

0.4 V Output current −8 mA,

3.3 V supply voltage

Logic "1" output voltage 2.5

VDD V Output current 8 mA,

3.3 V supply voltage

Logic "0" input current

NA −1

A

Input signal equals GND

Logic "1" input current

NA 1

A

Input signal equals VDD

FIFO setup time 20 ns TX unbuffered mode, minimum

time FIFO must be ready before
the positive edge of FIFOP

FIFO hold time

10 ns TX unbuffered mode, minimum

time FIFO must be held after the
positive edge of FIFOP

Serial interface pins (SCLK, SI, SO
and CSn) timing specification

See Table 4 on page 28

CC2420

SWRS041B Page 13 of 89

6.8 Voltage Regulator

Parameter Min. Typ. Max. Unit Condition / Note

General

Note that the internal voltage
regulator can only supply
CC2420 and no external circuitry.

Input Voltage

2.1 3.0 3.6 V On the VREG_IN pin

Output Voltage

1.7 1.8 1.9 V On the VREG_OUT pin

Quiescent current

13 20 29

A

No current drawn from the
VREG_OUT pin. Min and max
numbers include 2.1 through 3.6
V input voltage

Start-up time

0.3 0.6 ms

6.9 Battery Monitor

Parameter Min. Typ. Max. Unit Condition / Note

Current consumption

6 30 90

A

When enabled

Start-up time

100

s

Voltage regulator already enabled

Settling time

2

s

New toggle voltage programmed

Step size

50 mV

Hysteresis

10 mV

Absolute accuracy

-80 80 mV May be software calibrated for
known reference voltage

Relative accuracy

-50 50 mV

6.10 Power Supply

Parameter Min. Typ. Max. Unit Condition / Note

Current consumption in different
modes (see Figure 25, page 44)

Voltage regulator off (OFF)
Power Down mode (PD)
Idle mode (IDLE)

0.02
20
426

1

A
A
A

Current drawn from VREG_IN,
through voltage regulator

Voltage regulator off
Voltage regulator on
Including crystal oscillator and
voltage regulator

Current Consumption,
receive mode

18.8 mA

CC2420

SWRS041B Page 14 of 89

Parameter Min. Typ. Max. Unit Condition / Note

Current Consumption,
transmit mode:

P = -25 dBm
P = -15 dBm
P = -10 dBm
P = −5 dBm
P = 0 dBm

8.5

9.9
11
14

17.4

mA
mA
mA
mA
mA

The output power is delivered
differentially to a 50  singled
ended load through a balun, see
also page 54.

CC2420

SWRS041B Page 15 of 89

7 Pin Assignment

VREG_OUT

AVDD_CHP

QLP48

7x7

1

2

3

4

5

6

7

8

9

10

11

12

35

34

33

32

31

30

29

28

27

26

25

36

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

CC2420

R_BIAS

AVDD_IF1

VREG_IN

VREG_EN

XOSC16_Q1

XOSC16_Q2

ATEST2

ATEST1

NC

RF_P

RF_N

AVDD_PRE

AVDD_RF1

TXRX_SWITCH

AVDD_VCO

VCO_GUARD

AVDD_SW

GND

GND

NC

NC

DSUB_CORE

DSUB_PADS

AVDD_ADC

DVDD_ADC

DGUARD

AVDD_IF2

DGND_GUARD

AVDD_RF2

DGND

NC

CSn

FIFO

FIFOP

CCA

SFD

DVDD1.8

SCLK

DVDD_RAM

SI

SO

DVDD3.3

NC

AVDD_XOSC16

NC

AGND

Exposed die

attach pad

RESETn

Figure 1.

CC2420

Pinout – Top View

Pin Pin Name Pin type Pin Description

-

AGND

Ground (analog) Exposed die attach pad. Must be connected to solid ground

plane

1

VCO_GUARD

Power (analog) Connection of guard ring for VCO (to AVDD) shielding

2

AVDD_VCO

Power (analog) 1.8 V Power supply for VCO

3

AVDD_PRE

Power (analog) 1.8 V Power supply for Prescaler

4

AVDD_RF1

Power (analog) 1.8 V Power supply for RF front-end

5

GND

Ground (analog) Grounded pin for RF shielding

6

RF_P

RF I/O Positive RF input/output signal to LNA/from PA in

receive/transmit mode

7

TXRX_SWITCH

Power (analog) Common supply connection for integrated RF front-end. Must

be connected to RF_P and RF_N externally through a DC
path

8

RF_N

RF I/O Negative RF input/output signal to LNA/from PA in

receive/transmit mode

9

GND

Ground (analog) Grounded pin for RF shielding

10

AVDD_SW

Power (analog) 1.8 V Power supply for LNA / PA switch

11

NC

- Not Connected

12

NC

- Not Connected

13

NC

- Not Connected

14

AVDD_RF2

Power (analog) 1.8 V Power supply for receive and transmit mixers

15

AVDD_IF2

Power (analog) 1.8 V Power supply for transmit / receive IF chain

CC2420

SWRS041B Page 16 of 89

Pin Pin Name Pin type Pin Description

16

NC

- Not Connected

17

AVDD_ADC

Power (analog) 1.8 V Power supply for analog parts of ADCs and DACs

18

DVDD_ADC

Power (digital) 1.8 V Power supply for digital parts of receive ADCs

19

DGND_GUARD

Ground (digital) Ground connection for digital noise isolation

20

DGUARD

Power (digital) 1.8 V Power supply connection for digital noise isolation

21

RESETn

Digital Input Asynchronous, active low digital reset

22

DGND

Ground (digital) Ground connection for digital core and pads

23

DSUB_PADS

Ground (digital) Substrate connection for digital pads

24

DSUB_CORE

Ground (digital) Substrate connection for digital modules

25

DVDD3.3

Power (digital) 3.3 V Power supply for digital I/Os

26

DVDD1.8

Power (digital) 1.8 V Power supply for digital core

27

SFD

Digital output SFD (Start of Frame Delimiter) / digital mux output

28

CCA

Digital output CCA (Clear Channel Assessment) / digital mux output

29

FIFOP

Digital output Active when number of bytes in FIFO exceeds threshold /

serial RF clock output in test mode

30

FIFO

Digital I/O Active when data in FIFO /

serial RF data input / output in test mode

31

CSn

Digital input SPI Chip select, active low

32

SCLK

Digital input SPI Clock input, up to 10 MHz

33

SI

Digital input SPI Slave Input. Sampled on the positive edge of SCLK

34

SO

Digital output
(tristate)

SPI Slave Output. Updated on the negative edge of SCLK.
Tristate when CSn high.

35

DVDD_RAM

Power (digital) 1.8 V Power supply for digital RAM

36

NC

- Not Connected

37

AVDD_XOSC16

Power (analog) 1.8 V crystal oscillator power supply

38

XOSC16_Q2

Analog I/O 16 MHz Crystal oscillator pin 2

39

XOSC16_Q1

Analog I/O 16 MHz Crystal oscillator pin 1 or external clock input

40

NC

- Not Connected

41

VREG_EN

Digital input Voltage regulator enable, active high, held at VREG_IN

voltage level when active. Note that VREG_EN is relative
VREG_IN, not DVDD3.3.

42

VREG_OUT

Power output Voltage regulator 1.8 V power supply output

43

VREG_IN

Power (analog) Voltage regulator 2.1 to 3.6 V power supply input

44

AVDD_IF1

Power (analog) 1.8 V Power supply for transmit / receive IF chain

45

R_BIAS

Analog output

External precision resistor, 43 k,  1 %

46

ATEST2

Analog I/O Analog test I/O for prototype and production testing

47

ATEST1

Analog I/O Analog test I/O for prototype and production testing

48

AVDD_CHP

Power (analog) 1.8 V Power supply for phase detector and charge pump

NOTES:

The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the
chip.

CC2420

SWRS041B Page 17 of 89

8 Circuit Description

Serial

microcontroller

interface

LNA

DIGITAL

DEMODULATOR

- Digital RSSI

- Gain Control

- Image Suppression

- Channel Filtering

- Demodulation

- Frame
synchronization

DIGITAL

MODULATOR

- Data spreading

- Modulation

On-chip

BIAS

DIGITAL

INTERFACE

WITH FIFO
BUFFERS,

CRC AND

ENCRYPTION

CONTROL LOGIC



AUTOMATIC GAIN CONTROL

TX POWER CONTROL

TX/RX CONTROL

XOSC

16 MHz

R

ADC

ADC

DAC

DAC

0

90

FREQ

SYNTH

SmartRF



CC2420

Power

Control

PA

Serial

voltage

regulator

Digital and

Analog test

interface

Figure 2.

CC2420

simplified block diagram

A simplified block diagram of

CC2420

is

shown in Figure 2.

CC2420

features a low-IF receiver. The
received RF signal is amplified by the low­noise amplifier (LNA) and down-converted
in quadrature (I and Q) to the intermediate
frequency (IF). At IF (2 MHz), the complex
I/Q signal is filtered and amplified, and
then digitized by the ADCs. Automatic
gain control, final channel filtering, de­spreading, symbol correlation and byte
synchronisation are performed digitally.

When the SFD pin goes active, this
indicates that a start of frame delimiter has
been detected.

CC2420

buffers the
received data in a 128 byte receive FIFO.
The user may read the FIFO through an
SPI interface. CRC is verified in hardware.
RSSI and correlation values are appended
to the frame. CCA is available on a pin in
receive mode. Serial (unbuffered) data
modes are also available for test
purposes.

The

CC2420

transmitter is based on direct
up-conversion. The data is buffered in a
128 byte transmit FIFO (separate from the
receive FIFO). The preamble and start of
frame delimiter are generated by
hardware. Each symbol (4 bits) is spread
using the IEEE 802.15.4 spreading
sequence to 32 chips and output to the
digital-to-analog converters (DACs).

An analog low pass filter passes the signal
to the quadrature (I and Q) upconversion
mixers. The RF signal is amplified in the
power amplifier (PA) and fed to the
antenna.

The internal T/R switch circuitry makes the
antenna interface and matching easy. The
RF connection is differential. A balun may
be used for single-ended antennas. The
biasing of the PA and LNA is done by
connecting TXRX_SWITCH to RF_P and
RF_N through an external DC path.

The frequency synthesizer includes a
completely on-chip LC VCO and a 90
degrees phase splitter for generating the I

CC2420

SWRS041B Page 18 of 89

and Q LO signals to the down-conversion
mixers in receive mode and up-conversion
mixers in transmit mode. The VCO
operates in the frequency range 4800 –
4966 MHz, and the frequency is divided by
two when split in I and Q.

A crystal must be connected to
XOSC16_Q1 and XOSC16_Q2 and
provides the reference frequency for the
synthesizer. A digital lock signal is
available from the PLL.

The digital baseband includes support for
frame handling, address recognition, data
buffering and MAC security.

The 4-wire SPI serial interface is used for
configuration and data buffering.

An on-chip voltage regulator delivers the
regulated 1.8 V supply voltage. The
voltage regulator may be enabled /
disabled through a separate pin.

A battery monitor may optionally be used
to monitor the unregulated power supply
voltage. The battery monitor is
configurable through the SPI interface.

CC2420

SWRS041B Page 19 of 89

9 Application Circuit

Few external components are required for
the operation of

CC2420

. A typical
application circuit is shown in Figure 4.
The external components shown are
described in Table 1 and typical values
are given in Table 2. Note that most
decoupling capacitors are not shown on
the application circuits. For the complete
reference design please refer to Texas
Instrument’s web site: http://www.ti.com

.

9.1 Input / output matching

The RF input/output is high impedance
and differential. The optimum differential
load for the RF port is 95+j187 .

When using an unbalanced antenna such
as a monopole, a balun should be used in
order to optimise performance. The balun
can be implemented using low-cost
discrete inductors and capacitors only or
in combination with transmission lines.

Figure 3 shows the balun implemented in
a two-layer reference design. It consists of
a half wave transmission line, C81, L61,
L71 and L81. The circuit will present the
optimum RF termination to

CC2420

with a
50  load on the antenna connection. This
circuit has improved EVM performance,
sensitivity and harmonic suppression
compared to the design in Figure 4.
Please refer to the input/output matching
section on page 54 for more details.

The balun in Figure 4 consists of C61,
C62, C71, C81, L61, L62 and L81, and will
present the optimum RF termination to

CC2420

with a 50  load on the antenna
connection. A low pass filter may be
added to add margin to the FCC
requirement on second harmonic level.

If a balanced antenna such as a folded
dipole is used, the balun can be omitted. If
the antenna also provides a DC path from
the TXRX_SWITCH pin to the RF pins,
inductors are not needed for DC bias.

Figure 5 shows a suggested application
circuit using a differential antenna. The
antenna type is a standard folded dipole.
The dipole has a virtual ground point;
hence bias is provided without
degradation in antenna performance.

9.2 Bias resistor

The bias resistor R451 is used to set an
accurate bias current.

9.3 Crystal

An external crystal with two loading
capacitors (C381 and C391) is used for
the crystal oscillator. See page 53 for
details.

9.4 Voltage regulator

The on chip voltage regulator supplies all

1.8 V power supply inputs. C42 is required
for stability of the regulator. A series
resistor may be used to comply with the
ESR requirement.

9.5 Power supply decoupling and
filtering

Proper power supply decoupling must be
used for optimum performance. The
placement and size of the decoupling
capacitors and the power supply filtering
are very important to achieve the best
performance in an application. Texas
Instruments provides a compact reference
design that should be followed very
closely..

CC2420

SWRS041B Page 20 of 89

Ref Description

C42 Voltage regulator load capacitance

C61 Balun and match

C62 DC block to antenna and match

C71 Front-end bias decoupling and match

C81 Balun and match

C381 16MHz crystal load capacitor, see page 53

C391 16MHz crystal load capacitor, see page 53

L61 DC bias and match

L62 DC bias and match

L71 DC bias and match

L81 Balun and match

R451 Precision resistor for current reference generator

XTAL 16MHz crystal, see page 53

Table 1. Overview of external components

35

34

33

32

31

30

29

28

27

26

25

36

13

14

1516171819

202122

23

24

4847464544434241403938

37

1

2

3

4

5

6

7

8

9

10

11

12

QLP48

7x7

CC2420

RF

Transceiver

DSUB_CORE

DSUB_PADS

AVDD_ADC

DVDD_ADC

DGUARD

AVDD_IF2

DGND_GUARD

AVDD_RF2

DGND

NC

NC

RESETn

RF_P

RF_N

AVDD_PRE

AVDD_RF1

TXRX_SWITCH

AVDD_VCO

VCO_GUARD

AVDD_SW

GND

GND

NC

NC

VREG_OUT

AVDD_CHP

R_BIAS

AVDD_IF1

VREG_IN

VREG_EN

XOSC16_Q1

XOSC16_Q2

ATEST2

ATEST1

NC

AVDD_XOSC16

CSn

FIFO

FIFOP

CCA

SFD

DVDD1.8

SCLK

DVDD_RAM

SI

SO

DVDD3.3

NC

XTAL

Digital Interf ace

3.3 V
Power
supply



Antenna

(50 Ohm)

L61

C81 L81

L71

R451

C42

C391 C381

Figure 3. Typical application circuit with transmission line balun for single-ended

operation

CC2420

SWRS041B Page 21 of 89

35

34

33

32

31

30

29

28

27

26

25

36

13

14

15

16

17

1819202122

23

24

48

474645444342414039

38

37

1

2

3

4

5

6

7

8

9

10

11

12

QLP48

7x7

CC2420

RF

Transceiver

DSUB_CORE

DSUB_PADS

AVDD_ADC

DVDD_ADC

DGUARD

AVDD_IF2

DGND_GUARD

AVDD_RF2

DGND

NC

NC

RESETn

RF_P

RF_N

AVDD_PRE

AVDD_RF1

TXRX_SWITCH

AVDD_VCO

VCO_GUARD

AVDD_SW

GND

GND

NC

NC

VREG_OUT

AVDD_CHP

R_BIAS

AVDD_IF1

VREG_IN

VREG_EN

XOSC16_Q1

XOSC16_Q2

ATEST2

ATEST1

NC

AVDD_XOSC16

CSn

FIFO

FIFOP

CCA

SFD

DVDD1.8

SCLK

DVDD_RAM

SI

SO

DVDD3.3

NC

XTAL

C391 C381

C61

C71

C62

Antenna

(50 Ohm)

L81

C81

L62

Digital Interface

R451

3.3 V
Power
supply

L61

C42

Figure 4. Typical application circuit with discrete balun for single-ended operation

CC2420

SWRS041B Page 22 of 89

35

34

33

32

31

30

29

28

27

26

25

36

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

1

2

3

4

5

6

7

8

9

10

11

12

QLP48

7x7

CC2420

RF

Transceiver

DSUB_CORE

DSUB_PADS

AVDD_ADC

DVDD_ADC

DGUARD

AVDD_IF2

DGND_GUARD

AVDD_RF2

DGND

NC

NC

RESETn

RF_P

RF_N

AVDD_PRE

AVDD_RF1

TXRX_SWITCH

AVDD_VCO

VCO_GUARD

AVDD_SW

GND

GND

NC

NC

VREG_OUT

AVDD_CHP

R_BIAS

AVDD_IF1

VREG_IN

VREG_EN

XOSC16_Q1

XOSC16_Q2

ATEST2

ATEST1

NC

AVDD_XOSC16

CSn

FIFO

FIFOP

CCA

SFD

DVDD1.8

SCLK

DVDD_RAM

SI

SO

DVDD3.3

NC

XTAL

C391 C381

Digital Interface

R451

3.3 V
Power
supply

L61

C42

Folded

dipole

antenna

L71

Figure 5. Suggested application circuit with differential antenna (folded dipole)

CC2420

SWRS041B Page 23 of 89

Item Single ended output,

transmission line balun

Single ended output,
discrete balun

Differential antenna

C42

10 µF, 0.5 < ESR < 5 10 µF, 0.5 < ESR < 5 10 µF, 0.5 < ESR < 5

C61 Not used 0.5 pF, +/- 0.25pF, NP0, 0402 Not used

C62 Not used 5.6 pF, +/- 0.25pF, NP0, 0402 Not used

C71 Not used 5.6 pF, 10%, X5R, 0402 Not used

C81 5.6 pF, +/- 0.25pF, NP0, 0402 0.5 pF, +/- 0.25pF, NP0, 0402 Not used

C381 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402

C391 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402

L61 8.2 nH, 5%,

Monolithic/multilayer, 0402

7.5 nH, 5%,
Monolithic/multilayer, 0402

27 nH, 5%, Monolithic/multilayer,
0402

L62 Not used 5.6 nH, 5%,

Monolithic/multilayer, 0402

Not used

L71 22 nH, 5%,

Monolithic/multilayer, 0402

Not used 12 nH, 5%, Monolithic/multilayer,

0402

L81 1.8 nH, +/- 0.3nH,

Monolithic/multilayer, 0402

7.5 nH, 5%,
Monolithic/multilayer, 0402

Not used

R451

43 k, 1%, 0402 43 k, 1%, 0402 43 k, 1%, 0402

XTAL 16 MHz crystal, 16 pF load

(C

L

),

ESR < 60 

16 MHz crystal, 16 pF load
(CL),
ESR < 60 

16 MHz crystal, 16 pF load (C

L

),

ESR < 60 

Table 2. Bill of materials for the application circuits

CC2420

SWRS041B Page 24 of 89

10 IEEE 802.15.4 Modulation Format

This section is meant as an introduction to
the 2.4 GHz direct sequence spread
spectrum (DSSS) RF modulation format
defined in IEEE 802.15.4. For a complete
description, please refer to [1].

The modulation and spreading functions
are illustrated at block level in Figure 6 [1].
Each byte is divided into two symbols, 4
bits each. The least significant symbol is
transmitted first. For multi-byte fields, the

least significant byte is transmitted first,
except for security related fields where the
most significant byte it transmitted first.

Each symbol is mapped to one out of 16
pseudo-random sequences, 32 chips
each. The symbol to chip mapping is
shown in Table 3. The chip sequence is
then transmitted at 2 MChips/s, with the
least significant chip (C

0

) transmitted first

for each symbol.

Bit-to-

Symbol

Symbol-

to-Chip

O-QPSK

Modulator

Transmitted

bit-stream
(LSB first)

Modulated

Signal

Figure 6. Modulation and spreading functions [1]

Symbol Chip sequence (C0, C1, C2, … , C31)

0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0

1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0

2 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0

3 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1

4 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1

5 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0

6 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1

7 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1

8 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1

9 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1

10 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1

11 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0

12 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0

13 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1

14 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0

15 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0

Table 3. IEEE 802.15.4 symbol-to-chip mapping [1]

The modulation format is Offset –
Quadrature Phase Shift Keying (O-QPSK)
with half-sine chip shaping. This is
equivalent to MSK modulation. Each chip

is shaped as a half-sine, transmitted
alternately in the I and Q channels with
one half chip period offset. This is
illustrated for the zero-symbol in Figure 7.

CC2420

SWRS041B Page 25 of 89

1

01

0

1101

I-phase

Q-phase

1

00

1

1001

0

00

1100

1

0

11

0010

1

T

C

2T

C

Figure 7. I / Q Phases when transmitting a zero-symbol chip sequence, TC = 0.5 µs

11 Configuration Overview

CC2420

can be configured to achieve the
best performance for different
applications. Through the programmable
configuration registers the following key
parameters can be programmed:

 Receive / transmit mode
 RF channel selection
 RF output power

 Power-down / power-up mode
 Crystal oscillator power-up / power

down

 Clear Channel Assessment mode
 Packet handling hardware support
 Encryption / Authentication modes

CC2420

SWRS041B Page 26 of 89

12 Evaluation Software

Texas Instruments (TI) provides users of

CC2420

with a software program,
SmartRF

®

Studio (Windows interface)
which may be used for radio performance
and functionality evaluation. SmartRF®

Studio can be downloaded from TI’s web
page: http://www.ti.com

. Figure 8 shows

the user interface of the

CC2420

configuration software.

Figure 8. SmartRF Studio user interface

CC2420

SWRS041B Page 27 of 89

13 4-wire Serial Configuration and Data Interface

CC2420

is configured via a simple 4-wire

SPI-compatible interface (pins SI, SO,
SCLK and CSn) where

CC2420

is the slave.
This interface is also used to read and
write buffered data (see page 39). All
address and data transfer on the SPI
interface is done most significant bit first.

13.1 Pin configuration

The digital inputs SCLK, SI and CSn are
high-impedance inputs (no internal pull­up) and should have external pull-ups if
not driven. SO is high-impedance when
CSn is high. An external pull-up should be
used at SO to prevent floating input at
microcontroller. Unused I/O pins on the
MCU can be set to outputs with a fixed ‘0’
level to avoid leakage currents.

13.2 Register access

There are 33 16-bit configuration and
status registers, 15 command strobe
registers, and two 8-bit registers to access
the separate transmit and receive FIFOs.
Each of the 50 registers is addressed by a
6-bit address. The RAM/Register bit (bit 7)
must be cleared for register access. The
Read/Write bit (bit 6) selects a read or a
write operation and makes up the 8-bit
address field together with the 6-bit
address.

In each register read or write cycle, 24 bits
are sent on the SI-line. The CSn pin (Chip
Select, active low) must be kept low during
this transfer. The bit to be sent first is the

RAM/Register bit (set to 0 for register
access), followed by the R/W bit (0 for
write, 1 for read). The following 6 bits are

the address-bits (A5:0). A5 is the most

significant bit of the address and is sent
first. The 16 data-bits are then transferred
(D15:0), also MSB first. See Figure 9 for
an illustration.

The configuration registers can also be
read by the microcontroller via the same
configuration interface. The R/W bit must
be set high to initiate the data read-back.

CC2420

then returns the data from the

addressed register on the 16 clock cycles
following the register address. The SO pin
is used as the data output and must be
configured as an input by the
microcontroller.

The timing for the programming is also
shown in Figure 9 with reference to Table

4. The clocking of the data on SI into the

CC2420

is done on the positive edge of

SCLK. When the last bit, D0, of the 16
data-bits has been written, the data word
is loaded in the internal configuration
register.

Multiple registers may be written without
releasing CSn, as described in the Multiple
SPI access section on page 31.

The register data will be retained during
power down mode, but not when the
power-supply is turned off (e.g. by
disabling the voltage regulator using the
VREG_EN pin). The registers can be
programmed in any order.