Texas Instruments CDCVF2509PWR, CDCVF2509PW Datasheet

CDCVF2509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS637 – DECEMBER 1999

D

Designed to Meet and Exceed PC133
SDRAM Registered DIMM Specification
Rev. 1.1

D

Spread Spectrum Clock Compatible

D

Operating Frequency 50 MHz to 175 MHz

D

Static Phase Error Distribution at 66MHz to
166 MHz is ±125 ps

D

Jitter (cyc – cyc) at 66 MHz to 166 MHz is
|70| ps

D

Advanced Deep Sub-Micron Process
Results in More Than 40% Lower Power
Consumption Versus Current Generation
PC133 Devices

D

Available in Plastic 24-Pin TSSOP

D

Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications

D

Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs

D

Separate Output Enable for Each Output
Bank

D

External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input

D

25-Ω On-Chip Series Damping Resistors

D

No External RC Network Required

D

Operates at 3.3 V

AGND

V

CC

1Y0
1Y1

1Y2
GND
GND

1Y3

1Y4

V

CC

1G

FBOUT

PW PACKAGE

(TOP VIEW)

1

24

2

23

3

22

4

21

5

20

6

19

7

18

8

17

9

16

10

15

11

14

12

13

CLK
AV

CC

V

CC

2Y0
2Y1
GND
GND
2Y2
2Y3
V

CC

2G
FBIN

description

The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver . It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDCVF2509 operates at 3.3 V V
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew , low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled
or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in
phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDCVF2509 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry , the CDCVF2509 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDCVF2509 is characterized for operation from 0°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1999, Texas Instruments Incorporated

CC

. It also

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1

CDCVF2509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS637 – DECEMBER 1999

description (continued)

For application information refer to application reports

CDC509/516/2509/2510/2516
Spectrum Clocking (SSC)

(literature number SLMA003) and

(literature number SCAA039).

FUNCTION TABLE

INPUTS

1G 2G CLK

X X L L L L
L LHLLH

L HHLHH
H LHHLH

H H H H H H

functional block diagram

11

1G

High Speed Distribution Design Techniques for

Using CDC2509A/2510A PLL with Spread

OUTPUTS

1Y

(0:4)2Y(0:3)

FBOUT

3

1Y0

4

1Y1

CLK

FBIN

AV

2G

CC

14

24

13

23

PLL

21

20

17

16

12

5

8

9

1Y2

1Y3

1Y4

2Y0

2Y1

2Y2

2Y3

FBOUT

2

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TYPE

DESCRIPTION

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 85°C CDCVF2509PWR

Terminal Functions

TERMINAL

NAME NO.

Clock input. CLK provides the clock signal to be distributed by the CDCVF2509 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must

CLK 24 I

FBIN 13 I

1G 11 I

2G 14 I

FBOUT 12 O

1Y (0:4) 3, 4, 5, 8, 9 O

2Y (0:3) 21, 20, 17, 16 O

AV

CC

AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry.

V

CC

GND 6, 7, 18, 19 Ground Ground

23 Power

2, 10, 15, 22 Power Power supply

have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally
zero phase error between CLK and FBIN.

Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same
frequency as CLK.

Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK.
When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an
integrated 25-Ω series-damping resistor .

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the
1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each
output has an integrated 25-Ω series-damping resistor.

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the
2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each
output has an integrated 25-Ω series-damping resistor.

Analog power supply . AVCC provides the power reference for the analog circuitry. In addition, A VCC can
be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and
CLK is buffered directly to the device outputs.

SMALL OUTLINE

(PW)

CDCVF2509

SCAS637 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CDCVF2509

‡

PACKAGE

R

A

A

PW

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS637 – DECEMBER 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, AVCC (see Note 1) AVCC < VCC +0.7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range, VCC –0.5 V to 4.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V
Voltage range applied to any output in the high or low state,

VO (see Notes 2 and 3) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Output clamp current, I
Continuous output current, I

Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at TA = 55°C (in still air) (see Note 4) 0.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. AVCC must not exceed VCC+ 0.7 V

†

JECEC high-K board has better thermal performance due to multiple internal copper planes.

‡

This is the inverse of the traditional junction-to-ambient thermal resistance (R

2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. This value is limited to 4.6 V maximum.

4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the

Book

, literature number SCBD002.

BOARD

†

TYPE

JEDEC low-K 114.5 °C/W 920 mW 8.7 mW/°C 520 mW 390 mW

JEDEC high-K 62.1°C/W 1690 mW 16.1 mW/°C 960 mW 720 mW

(see Note 2) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(V

= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

O

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Package Thermal Considerations

DISSIPATION RATING TABLE

T

θJA

≤ 25°C DERATING FACTOR

POWER RATNG ABOVE TA = 25°C

application note in the

).

θJA

ABT Advanced BiCMOS T echnology Data

POWER RATINGAPOWER RATING

T

= 70°C T

= 85°C

†

recommended operating conditions (see Note 5)

MIN MAX UNIT

VCC, AVCCSupply voltage 3 3.6 V
V

IH

V

IL

V

I

I

OH

I

OL

T

A

NOTE 5: Unused inputs must be held high or low to prevent them from floating.

High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –12 mA
Low-level output current 12 mA
Operating free-air temperature 0 85 °C

CC

V

timing requirements over recommended ranges of supply voltage and operating free-air
temperature

MIN MAX UNIT

f

clk

†

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency , fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew ,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.

Clock frequency 50 175 MHz
Input clock duty cycle 40% 60%
Stabilization time

†

1 ms

4

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