TEXAS INSTRUMENTS CDCV857 Technical data

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CDCV857

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

D

Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM

DGG PACKAGE

(TOP VIEW)

Applications

D

Spread Spectrum Clock Compatible

D

Operating Frequency: 60 to 200 MHz

D

Low Jitter (cyc–cyc): ±75 ps

D

Distributes One Differential Clock Input to
Ten Differential Outputs

D

Three-State Outputs When the Input
Differential Clocks Are <20 MHz

D

Operates From Dual 2.5-V Supplies

D

48-Pin TSSOP Package

D

Consumes < 200-µA Quiescent Current

D

External Feedback PIN (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks

description

The CDCV857 is a high-performance, low-skew,
low-jitter zero delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs (Y[0:9], Y[0:9])
and one differential pair of feedback clock output
(FBOUT, FBOUT
controlled by the clock inputs (CLK, CLK), the

). The clock outputs are

GND

Y0
Y0

V

DDQ

Y1

Y1
GND
GND

Y2

Y2

V

DDQ

V

DDQ

CLK
CLK

V

DDQ

AV

DD

AGND

GND

Y3

Y3

V

DDQ

Y4

Y4
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

GND
Y5
Y5
V
Y6
Y6
GND
GND
Y7
Y7
V
PWRDWN
FBIN
FBIN
V
FBOUT
FBOUT
GND
Y8
Y8
V
Y9
Y9
GND

feedback clocks (FBIN, FBIN), and the analog
power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When
PWRDWN is low , all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power
mode). The device also enters this low power mode when the input frequency falls below a suggested detection
frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low
frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and
enables the outputs.

DDQ

DDQ

DDQ

DDQ

When A V

is strapped low, the PLL is turned of f and bypassed for test purposes. The CDCV857 is also able

DD

to track spread spectrum clocking for reduced EMI.
Since the CDCV857 is based on PLL circuitry , it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up. The CDCV857 is characterized for operation from 0°C
to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

CDCV857

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

FUNCTION TABLE
(Select Functions)

INPUTS OUTPUTS PLL

AV

DD

GND H L H L H L H Bypassed/Off
GND H H L H L H L Bypassed/Off

X L L H Z Z Z Z Off
X L H L Z Z Z Z Off

2.5 V (nom) H L H L H L H On

2.5 V (nom) H H L H L H L On

2.5 V (nom) X <20 MHz <20 MHz Z Z Z Z Off

functional block diagram

PWRDWN

AV

DD

CK

CK
FBIN
FBIN

PWRDWN CLK CLK Y[0:9] Y[0:9] FBOUT FBOUT

37

16

13
14

36
35

Powerdown

and Test

Logic

PLL

3

Y0

2

Y0

5

Y1

6

Y1

10

Y2

9

Y2

20

Y3

19

Y3

22

Y4

23

Y4

46

Y5

47

Y5

44

Y6

43

Y6

39

Y7

40

Y7

29

Y8

30

Y8

27

Y9

26

Y9

32

FBOUT

33

FBOUT

2

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Terminal Functions

I/O

DESCRIPTION

TERMINAL

NAME NO.

AGND 17 Ground for 2.5-V analog supply
AV

DD

CLK, CLK 13, 14 I Differential clock input
FBIN, FBIN 35, 36 I Feedback differential clock input
FBOUT, FBOUT 32, 33 O Feedback dif ferential clock output
GND 1, 7, 8, 18,

PWRDWN 37 I Output enable for Y and Y
V

DDQ

Y[0:9] 3, 5, 10,

Y[0:9] 2, 6, 9, 19,

16 2.5-V Analog supply

24, 25, 31,

41, 42, 48

4, 11, 12,

15, 21, 28,

34, 38, 45

20, 22, 27,
29, 39, 44,

46

23, 26, 30,

40, 43, 47

Ground

2.5-V Supply

O Buffered output copies of input clock, CLK

O Buffered output copies of input clock, CLK

CDCV857

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

I

Output voltage range, V
Input clamp current, IIK (VI < 0 or V
Output clamp current, IOK (VO < 0 or VO > V
Continuous output current, IO (VO = 0 to V
Continuous current to GND or V

AVDD 0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

,

DDQ

(see Notes 1 and 2) –0.5 V to V

(see Notes 1 and 2) –0.5 V to V

O

> V

I

±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

DDQ

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

DDQ
DDQ

0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This value is limited to 3.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CDCV857

Low level input voltage, V

V

High level input voltage, V

V

Differential input signal voltage, V

(see Note 6)

V

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

recommended operating conditions (see Note 4)

MIN TYP MAX UNIT

Supply voltage, V

p

p

DC input signal voltage (see Note 5) –0.3 V

p

Output differential cross-voltage, VOX (see Note 7) V
Input differential pair cross-voltage, VIX (see Note 7) V
High-level output current, I
Low-level output current, I
Input slew rate, SR 1 4 V/ns
Operating free-air temperature, T

NOTES: 4. Unused inputs must be held high or low to prevent them from floating.

5. DC input signal voltage specifies the allowable dc execution of differential input.

6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level.

7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be
crossing.

DDQ,

AV

IL

IH

OH

OL

DD

2.3 2.7 V
CLK, CLK, FBIN, FBIN V
PWRDWN –0.3 0.7
CLK, CLK, FBIN, FBIN V
PWRDWN 1.7 V

ID

A

DC CLK, FBIN 0.36 V
AC

CLK, FBIN 0.7 V

/2 + 0.18

DDQ

/2 – 0.2 V

DDQ

/2 – 0.2 V

DDQ

0 85 °C

DDQ

/2 V

DDQ

DDQ
DDQ

/2 – 0.18

DDQ

DDQ
DDQ

+ 0.3

DDQ

+ 0.6

+ 0.6
/2 + 0.2 V
/2 + 0.2 V

–12 mA

12 mA

V

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDCV857

VOHHigh-level output voltage

V

VOLLow-level output voltage

V

Differential outputs are terminated with
IDDDynamic current on V

mA

AIDDSupply current on AV

mA

f

60

200

MH

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

V

IK

I

OH

I

OL

V

O

V

OX

I

I

I

OZ

I

DDPD

C

I

C

O

†

All typical values are at respective nominal V

‡

The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input
signal voltage and VCP is the complementary input signal voltage.

§

Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.

Input voltage All inputs V

p

p

High-level output current V
Low-level output current V
Output voltage swing
Output differential

cross-voltage
Input current V
High-impedance-state

output current
Power down current on

V

DDQ

pp

Input capacitance VCC = 2.5 V VI = VCC or GND 2 2.5 3 pF
Output capacitance VCC = 2.5 V VO = VCC or GND 2.5 3 3.5 pF

+ AV

w

DD

DDQ

DD

= 2.3 V, II = –18 mA –1.2 V

DDQ

V

= min to max, IOH = –1 mA V

DDQ

V

= 2.3 V, IOH = –12 mA 1.7

DDQ

V

= min to max, IOL = 1 mA 0.1

DDQ

V

= 2.3 V, IOL = 12 mA 0.6

DDQ

= 2.3 V, VO = 1 V –18 –32 mA

DDQ

= 2.3 V, VO = 1.2 V 26 35 mA

DDQ

120 Ω

DDQ

V

DDQ

CLK and CLK = 0 MHz; PWRDWN = Low;
Σ of IDD and AI

all outputs loaded
as shown in
Figure 3

fO = 200 MHz 10 12
fO = 167 MHz

DDQ

p

V
= 2.7 V, VI = 0 V to 2.7 V ±10 µA
= 2.7 V, VO= V

DD

fO = 200 MHz 275 330
fO = 167 MHz 250 300

.

or GND ±10 µA

DDQ

DDQ

/2 – 0.2 V

DDQ

– 0.1

1.1 V

†

/2 V

DDQ

100 200 µA

8 10

DDQ

DDQ

MAX UNIT

– 0.4

/2 + 0.2

V

timing requirements over recomme nd ed ran ge s of supply voltage and operating free-air
temperature

MIN MAX UNIT

CK

¶

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency , fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew ,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.

Operating clock frequency
Application clock frequency
Input clock duty cycle 40% 60%
Stabilization timeW (PLL mode) 10 µs

Stabilization timeW (Bypass mode) 30 ns

z

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5

CDCV857

t

w

Jitter (period), See Figure 6

t

w

Jitter (cycle-to-cycle), See Figure 3

ps

t

w

Half-period jitter, See Figure 7

ps

t

w

y(j),

ps

t

Static phase offset, See Figure 4(a)

ps

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

switching characteristics

PARAMETER TEST CONDITIONS MIN

}

t

PLH

}

t

PHL

jit(per)

jit(cc)

jit(hper)

t

slr(i)

t

slr(o)

d(Ø)

(Ø)

W

tsk

(o)

tr, tf Output rise and fall times (20% – 80%) Load: 120 Ω/14 pF 650 900 ps

†

All typical values are at a respective nominal V

‡

Refers to transition of noninverting output.

§

This parameter is assured by design but can not be 100% production tested.

¶

All differential output pins are terminated with 120 Ω/14 pF.

Low to high level propagation delay time Test mode/CLK to any output 4.5 ns
High-to low level propagation delay time Test mode/CLK to any output 4.5 ns

p

p

Input clock slew rate, See Figure 8 1 4 V/ns
Output clock slew rate, See Figure 8 1 2 V/ns

Dynamic phase offset (this includes jitter), See
Figure 4(b)

p

Output skew, See Figure 5 75 ps

.

DDQ

66 MHz –90 90 ps
100/133/167/200 MHz –75 75 ps
66 MHz –180 180
100/133/167/200 MHz –75 75
66 MHz –160 160
100/133/167/200 MHz –100 100

66 MHz –180 180

SSC off

SSC on

66/100/133/167 MHz –100 100
200 MHz –150 50

100/133 MHz –130 130
167/200 MHz –90 90
66 MHz –230 230
100/133 MHz –170 170
167/200 MHz –100 100

TYP

{

MAX UNIT

p

p

p

p

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

PARAMETER MEASUREMENT INFORMATION

V

DD

V

(CK)

R = 60 Ω

CDCV857

CDCV857

GND

V

(CK)

R = 60 Ω

VDD/2

Figure 1. IBIS Model Output Load (used for slew rate measurement)

VDD/2

CDCV857

Z = 60 Ω

Z = 60 Ω

C = 14 pF

R = 10 Ω

C = 14 pF

–VDD/2

Z = 50 ΩR = 10 Ω

Z = 50 Ω

SCOPE

V

(TT)

V

(TT)

R = 50 Ω

R = 50 Ω

–VDD/2

NOTE: V

Yx, FBOUT

Yx, FBOUT

(TT)

= GND

–VDD/2

Figure 2. Output Load Test Circuit

t

c(n)

t

jit(cc)

= t

c(n)

– t

c(n+1)

t

c(n+1)

Figure 3. Cycle-to-Cycle Jitter

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

CDCV857

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

PARAMETER MEASUREMENT INFORMATION

CK

CK

FBIN

FBIN

CK

CK

FBIN

FBIN

t

( ) n

t

( )

(N is a large number of samples)

(a) Static Phase Offset

t

( )

t

( )d

t

( )d

(b)

Dynamic Phase Offset

n = N

∑

=

t

1

( ) n

N

t

( )d

t

( ) n+1

t

( )

t

( )d

Figure 4. Phase Offset

Yx

Yx

Yx, FBOUT

Yx, FBOUT

t

sk(o)

Figure 5. Output Skew

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Yx, FBOUT

Yx, FBOUT

, FBOUT

Yx

Yx, FBOUT

, FBOUT

Yx

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

PARAMETER MEASUREMENT INFORMATION

t

c(n)

1

f

o

t

= tcn –

jit(per)

Figure 6. Period Jitter

1

f

o

CDCV857

Yx, FBOUT

Clock Inputs
and Outputs

t

(hper_n)

t

jit(hper)

= t

t

1

f

o

(hper_n) –

(hper_n+1)

2xf

Figure 7. Half-Period Jitter

80%

20%

t

slrr(i)

, t

slrr(o)

t

slrf(i)

Figure 8. Input and Output Slew Rates

1

o

80%

VID, V

OD

20%

, t

slrf(o)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

CDCV857

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

MECHANICAL DATA

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,50

48

1

1,20 MAX

0,27
0,17

25

24

A

0,15
0,05

0,08

M

8,30

6,20

7,90

6,00

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75
0,50

DIM

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

PINS **

A MAX

A MIN

48

12,60

12,40

56

14,10

13,90

64

17,10

16,90

4040078/F 12/97

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

4-Mar-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

CDCV857DGG ACTIVE TSSOP DGG 48 40 Pb-Free

CDCV857DGGR ACTIVE TSSOP DGG 48 2000 Pb-Free

CDCV857DGGRG4 PREVIEW TSSOP DGG 48 2000 None Call TI Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

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Addendum-Page 1

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