TEXAS INSTRUMENTS CDCV857 Technical data

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CDCV857

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

D

Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM

DGG PACKAGE

(TOP VIEW)

Applications

D

Spread Spectrum Clock Compatible

D

Operating Frequency: 60 to 200 MHz

D

Low Jitter (cyc–cyc): ±75 ps

D

Distributes One Differential Clock Input to
Ten Differential Outputs

D

Three-State Outputs When the Input
Differential Clocks Are <20 MHz

D

Operates From Dual 2.5-V Supplies

D

48-Pin TSSOP Package

D

Consumes < 200-µA Quiescent Current

D

External Feedback PIN (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks

description

The CDCV857 is a high-performance, low-skew,
low-jitter zero delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs (Y[0:9], Y[0:9])
and one differential pair of feedback clock output
(FBOUT, FBOUT
controlled by the clock inputs (CLK, CLK), the

). The clock outputs are

GND

Y0
Y0

V

DDQ

Y1

Y1
GND
GND

Y2

Y2

V

DDQ

V

DDQ

CLK
CLK

V

DDQ

AV

DD

AGND

GND

Y3

Y3

V

DDQ

Y4

Y4
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

GND
Y5
Y5
V
Y6
Y6
GND
GND
Y7
Y7
V
PWRDWN
FBIN
FBIN
V
FBOUT
FBOUT
GND
Y8
Y8
V
Y9
Y9
GND

feedback clocks (FBIN, FBIN), and the analog
power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When
PWRDWN is low , all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power
mode). The device also enters this low power mode when the input frequency falls below a suggested detection
frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low
frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and
enables the outputs.

DDQ

DDQ

DDQ

DDQ

When A V

is strapped low, the PLL is turned of f and bypassed for test purposes. The CDCV857 is also able

DD

to track spread spectrum clocking for reduced EMI.
Since the CDCV857 is based on PLL circuitry , it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up. The CDCV857 is characterized for operation from 0°C
to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

CDCV857

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

FUNCTION TABLE
(Select Functions)

INPUTS OUTPUTS PLL

AV

DD

GND H L H L H L H Bypassed/Off
GND H H L H L H L Bypassed/Off

X L L H Z Z Z Z Off
X L H L Z Z Z Z Off

2.5 V (nom) H L H L H L H On

2.5 V (nom) H H L H L H L On

2.5 V (nom) X <20 MHz <20 MHz Z Z Z Z Off

functional block diagram

PWRDWN

AV

DD

CK

CK
FBIN
FBIN

PWRDWN CLK CLK Y[0:9] Y[0:9] FBOUT FBOUT

37

16

13
14

36
35

Powerdown

and Test

Logic

PLL

3

Y0

2

Y0

5

Y1

6

Y1

10

Y2

9

Y2

20

Y3

19

Y3

22

Y4

23

Y4

46

Y5

47

Y5

44

Y6

43

Y6

39

Y7

40

Y7

29

Y8

30

Y8

27

Y9

26

Y9

32

FBOUT

33

FBOUT

2

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Terminal Functions

I/O

DESCRIPTION

TERMINAL

NAME NO.

AGND 17 Ground for 2.5-V analog supply
AV

DD

CLK, CLK 13, 14 I Differential clock input
FBIN, FBIN 35, 36 I Feedback differential clock input
FBOUT, FBOUT 32, 33 O Feedback dif ferential clock output
GND 1, 7, 8, 18,

PWRDWN 37 I Output enable for Y and Y
V

DDQ

Y[0:9] 3, 5, 10,

Y[0:9] 2, 6, 9, 19,

16 2.5-V Analog supply

24, 25, 31,

41, 42, 48

4, 11, 12,

15, 21, 28,

34, 38, 45

20, 22, 27,
29, 39, 44,

46

23, 26, 30,

40, 43, 47

Ground

2.5-V Supply

O Buffered output copies of input clock, CLK

O Buffered output copies of input clock, CLK

CDCV857

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

I

Output voltage range, V
Input clamp current, IIK (VI < 0 or V
Output clamp current, IOK (VO < 0 or VO > V
Continuous output current, IO (VO = 0 to V
Continuous current to GND or V

AVDD 0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

,

DDQ

(see Notes 1 and 2) –0.5 V to V

(see Notes 1 and 2) –0.5 V to V

O

> V

I

±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

DDQ

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDQ

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

DDQ
DDQ

0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This value is limited to 3.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

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3

CDCV857

Low level input voltage, V

V

High level input voltage, V

V

Differential input signal voltage, V

(see Note 6)

V

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000

recommended operating conditions (see Note 4)

MIN TYP MAX UNIT

Supply voltage, V

p

p

DC input signal voltage (see Note 5) –0.3 V

p

Output differential cross-voltage, VOX (see Note 7) V
Input differential pair cross-voltage, VIX (see Note 7) V
High-level output current, I
Low-level output current, I
Input slew rate, SR 1 4 V/ns
Operating free-air temperature, T

NOTES: 4. Unused inputs must be held high or low to prevent them from floating.

5. DC input signal voltage specifies the allowable dc execution of differential input.

6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level.

7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be
crossing.

DDQ,

AV

IL

IH

OH

OL

DD

2.3 2.7 V
CLK, CLK, FBIN, FBIN V
PWRDWN –0.3 0.7
CLK, CLK, FBIN, FBIN V
PWRDWN 1.7 V

ID

A

DC CLK, FBIN 0.36 V
AC

CLK, FBIN 0.7 V

/2 + 0.18

DDQ

/2 – 0.2 V

DDQ

/2 – 0.2 V

DDQ

0 85 °C

DDQ

/2 V

DDQ

DDQ
DDQ

/2 – 0.18

DDQ

DDQ
DDQ

+ 0.3

DDQ

+ 0.6

+ 0.6
/2 + 0.2 V
/2 + 0.2 V

–12 mA

12 mA

V

4

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