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CDCV304
140-MHz PCI-X CLOCK BUFFER
SCAS643B – SEPTEMBER 2000 REVISED JUL Y 2002
D
General-Purpose and PCI-X 1:4 Clock
Buffer
D
Operating Frequency: 0 MHz to 140 MHz
D
Low Output Skew: <100 ps
D
Distributes One Clock Input to One Bank of
Four Outputs
D
Output Enable Control That Drives Outputs
CLKIN
OE
1Y0
GND
TSSOP
PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
Low When OE Is Low
D
Operates From Single 3.3-V Supply
D
8-Pin TSSOP Package
description
The CDCV304 is a high-performance, low-skew, general-purpose and PCI-X clock buf fer. It distributes one input
clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications.
The CDCV304 operates at 3.3 V.
The CDCV304 is characterized for operation from –40°C to 85°C for automotive and industrial applications.
FUNCTION TABLE
INPUTS
CLKIN OE 1Y (0:3)
L
H
L
H
L
L
H
H
OUTPUT
L
L
L
H
1Y3
1Y2
V
DD
1Y1
3.3V
functional block diagram
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OE
CLKIN
2
1
Logic
Control
3
1Y0
5
1Y1
7
1Y2
8
1Y3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
1
CDCV304
140-MHz PCI-X CLOCK BUFFER
SCAS643B – SEPTEMBER 2000 REVISED JULY 2002
Terminal Functions
TERMINAL
NAME NO.
1Y[0–3] 3, 5, 7, 8 O Buffered output clocks
CLKIN 1 I Input reference frequency
GND 4 Power Ground
OE 2 I Outputs enable control
VDD3.3V 6 Power 3.3-V supply
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous total output current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
(see Notes 1 and 2) –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Notes 1 and 2) –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0 or VI > VDD) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VDD) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VDD) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 3): PW package 230.5°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Input voltage, V
High-level output current, I
Low-level output current, I
Operating free-air temperature, T
DD
IH
IL
I
OH
OL
A
3 3.3 3.6 V
0.7×V
DD
0.3×V
0 V
–40 85 °C
V
DD
DD
–24 mA
V
V
24 mA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN NOM MAX UNIT
f
clk
2
Clock frequency 0 140 MHz
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IOHHigh-level output current
IOLLow-level output current
CLK high time, See Figure 4
CLK low time, See Figure 4
CDCV304
140-MHz PCI-X CLOCK BUFFER
SCAS643B – SEPTEMBER 2000 REVISED JULY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
V
OH
V
OL
I
I
I
DD
C
i
C
o
†
All typical values are at respective nominal VDD and 25°C.
Input voltage VDD = 3 V, II = –18 mA –1.2 V
VDD = min to max, IOH = –1 mA VDD–0.2
High-level output voltage
Low-level output voltage
p
p
Input current VI = VO or V
Dynamic current, See Figure 5 f = 67 MHz 37 mA
Input capacitance VDD = 3.3 V, VI = 0 V or V
Output capacitance VDD = 3.3 V, VI = 0 V or V
VDD = 3 V, IOH = –24 mA
VDD = 3 V, IOH = –12 mA 2.4
VDD = min to max, IOL = 1 mA 0.2
VDD = 3 V, IOL = 24 mA
VDD = 3 V, IOL = 12 mA 0.55
VDD = 3 V, VO = 1 V –50
VDD = 3.3 V, VO = 1.65 V –55
VDD = 3 V, VO = 2 V 60
VDD = 3.3 V, VO = 1.65 V 70
DD
DD
DD
2
0.8
±5 µA
3 pF
3.2 pF
V
V
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 10 pF, VDD = 3.3 V ± 0.3 V (see Note 6 and Figures 1 and 2)
PARAMETER TEST CONDITIONS MIN
t
PLH
t
PHL
t
sk(o)
t
sk(p)
t
sk(pr)
t
sk(pp)
high
low
t
r
t
f
†
All typical values are at respective nominal VDD.
‡
This symbol is according to PCI-X terminology.
NOTE 4: The t
High-to-low propagation delay
Low-to-high propagation delay
Output skew (see Note 4) 50 100 ps
Pulse skew VIH = VDD, VIL = 0 V 150 ps
Process skew 0.2 0.3 ns
Part-to-part skew 0.25 0.4 ns
Output rise slew rate
Output fall slew rate
specification is only valid for equal loading of all outputs.
sk(o)
‡
‡
1.8 2.5 3 ns
1.8 2.4 3 ns
66 MHz 6
140 MHz 3
66 MHz 6
140 MHz 3
0.2VDD to 0.6V
0.6VDD to 0.2V
DD
DD
1.5 2.7 4 V/ns
1.5 2.7 4 V/ns
TYP
†
MAX UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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