Datasheet CDCR61APWR Datasheet (Texas Instruments)

CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
400-MHz Differential Clock Source for Direct Rambus Memory Systems for an 800-MHz Data Transfer Rate
D
Operates From Two (3.3-V and 1.80-V) Power Supplies With 180 mW (Typ) at 400 MHz Total
D
Packaged in a Thin Shrink Small-Outline Package (PW)
D
External Crystal Required for Input
description
The Direct Rambus clock generator – lite (DRCG-Lite) is an independent crystal clock generator. It performs clock multiplication using PLL, sourced by an internal crystal oscillator. It provides one dif ferential, high-speed Rambus channel compatible output pair. Also, one single-ended output is available to deliver 1/2 of the crystal frequency. The Rambus channel operates at up to 400 MHz with an option to select 300 MHz as well. The desired crystal is a 18.75-MHz crystal in a series resonance fundamental application.
The CDCR61A is characterized for operation over free-air temperatures of 0°C to 85°C.
functional block diagram
/2
OSC
PLL
BUSCLK
LCLK
2
S0
XTAL
XOUT
XIN
S1 S2
DIV
V
DDP
BUSCLK FREQUENCY SETTINGS
S0
M (PLL MULTIPLIER)
0 16
1 or Open 64/3
FUNCTION TABLE
V
DDP
S1 S2 MODE CLK CLKB LCLK
ON 0 0 Normal CLK CLKB XIN divided by 2 ON 1 1 Normal CLK CLKB XIN divided by 2 ON 0 1 Test Divided by 2 Divided by 2 XIN divided by 2 ON 1 0 Test Divided by 4 Divided by 4 XIN divided by 2 0 V 0 0 Test XIN XIN (invert) XIN divided by 2 0 V 1 1 Test XIN XIN (invert) XIN divided by 2 0 V 0 1 Test XIN divided by 2 XIN (invert) divided by 2 XIN divided by 2 0 V 1 0 Test XIN divided by 4 XIN (invert) divided by 4 XIN divided by 2
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Direct Rambus and Rambus are trademarks of Rambus Inc.
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10
9
V
DDP
GNDP
XOUT
XIN
V
DDL
LCLK
GNDL
S1
S0 V
DD
GND CLK CLKB GND V
DD
S2
PW PACKAGE
(TOP VIEW)
CDCR61A DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
CLK 13 O Output clock, connect to Rambus channel CLKB 12 O Output clock (complement), connect to Rambus channel GNDP, GNDL,
GND
2, 7,
11, 14
Ground
LCLK 6 O LVCMOS output, 1/2 of crystal frequency S0, S1, S2 16, 8, 9 I LVTTL level logic select terminal for function selection V
DD
10, 15 Power supply, 3.3 V
V
DDP
1 Power supply for PLL, 3.3 V (0 V for Test mode)
V
DDL
5 Power supply for LCLK, 1.8 V XIN 4 I Reference crystal input XOUT 3 O Reference crystal feedback
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VDD or V
DDP
(see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, V
DDL
(see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range,V
I
, at any input terminal –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO, at any output terminal (CLK, CLKB) –0.5 V to V
DD
+ 0.5 V. . . . . . . . . . . . . . . . . . . .
Output voltage range, VO, at any output terminal (LCLK) –0.5 V to V
DDL
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . .
ESD rating (MIL-STD 883C, Method 3015) > 2 kV, Machine Model >200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation see Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
PACKAGE
TA 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PW 1400 mW 11 mW/°C 740 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
DD
3 3.3 3.6 V
LCLK supply voltage, V
DDL
1.7 1.8 2.1 V
p
S0 0.35×V
DD
Low-level input voltage, V
IL
S1, S2 0.35×V
DD
V
p
S0 0.65×V
DD
High-level input voltage, V
IH
S1, S2 0.65×V
DD
V
p
p
S0 10 55 100
Internal pullup resistance
S1, S2 90 145 250
k
p
CLK, CLKB 16
Low-level output current, I
OL
LCLK 10
mA
p
CLK, CLKB –16
High-level output current, I
OH
LCLK –10
mA
Input frequency at crystal input 14.0625 18.75 MHz
S0, S1, S2 2.5
p
I
nput capacitance
(CMOS), C
I
XIN, XOUT 20
pF
Operating free-air temperature, T
A
0 85 °C
Capacitance measured at f = 1 MHz, dc bias = 0.9 V , and VAC < 100 mV
timing requirements
MIN MAX UNIT
Clock cycle time, t
(cycle)
2.5 3.7 ns Input slew rate, SR 0.5 4 V/ns State transition latency (V
DDX
or S0 to CLKs – normal mode), t
(STL)
3 ms
crystal specifications
MIN MAX UNIT
Frequency 14.0625 18.75 MHz Frequency tolerance (at 25°C ±3°C) –15 15 ppm Equivalent resistance (CL = 10 pF) 100 Temperature drift (–10°C to 75°C) 10 ppm Drive level 0.01 1500 µW Motional inductance 20.7 25.3 mH Insulation resistance 500 M Spurious attenuation ratio (at frequency ±500 kHz) 3 dB Overtone spurious 8 dB
CDCR61A DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS
MIN TYP‡MAX UNIT
V
O(X)
Differential crossing-point output voltage See Figures 1 and 7 1.25 1.85 V
V
O(PP)
Peak-to-peak output voltage swing, single ended
VOH – VOL, See Figure 1 0.4 0.7 V
V
IK
Input clamp voltage VDD = 3 V, II = –18 mA –1.2 V
R
I
Input resistance XIN, XOUT VDD = 3.3 V, VI = V
O
>50 k
XOUT VDD = 3.3 V, VO = 2 V 27 mA
I
IH
High-level input current
S0
VDD = 3.6 V, VI = V
DD
10
S1, S2 VDD = 3.6 V, VI = V
DD
10
µ
A
XOUT VDD = 3.3 V, VO = 0 V –5.7 mA
I
IL
Low-level input current
S0
VDD = 3.6 V, VI = 0 V –30 –100
S1, S2 VDD = 3.6 V, VI = 0 V –10 –50
µ
A
See Figure 1 2.1
p
CLK, CLKB
VDD = min to max, IOH = –1 mA
VDD–
0.1 V
VOHHigh-level output voltage
VDD = 3 V, IOH = –16 mA 2.2
V
LCLK V
DDL
= min to max, IOH = – 10 mA
V
DDL
0.45 V
V
DDL
See Figure 1 1
p
CLK, CLKB
VDD = min to max, IOL = 1 mA 0.1
VOLLow-level output voltage
VDD = 3 V, IOL = 16 mA 0.5
V
LCLK V
DDL
= min to max, IOL = 10 mA 0 0.45
VDD = 3.135 V , VO = 1 V –32 –52
CLK, CLKB
VDD = 3.3 V, VO = 1.65 V –51
p
VDD = 3.465 V , VO = 3.135 V –14.5 –21
IOHHigh-level output current
V
DDL
= 1.7 V, VO = 0.5 V –11 –26
mA
LCLK
V
DDL
= 1.8 V, VO = 0.9 V –28
V
DDL
= 2.1 V, VO = 1.6 V –24.5 –35
VDD = 3.135 V , VO = 1.95 V 43 61.5
CLK, CLKB
VDD = 3.3 V, VO = 1.65 V 65
p
VDD = 3.465 V , VO = 0.4 V 25.5 36
IOLLow-level output current
V
DDL
= 1.7 V, VO = 1.2 V 11 27
mA
LCLK
V
DDL
= 1.8 V, VO = 0.9 V 30
V
DDL
= 2.1 V, VO = 0.5 V 28 38
r
OH
High-level dynamic output resistance
§
IO – 14.5 mA to ∆IO – 16.5 mA 12 25 40
r
OL
Low-level dynamic output resistance
§
IO + 14.5 mA to ∆IO + 16.5 mA 12 17 40
p
p
CLK, CLKB 3
p
COOutput capacitance
LCLK 3
pF
VDD refers to any of the following; VDD, V
DDL
, and V
DDP
All typical values are at VDD = 3.3 V, V
DDL
= 1.8 V, TA = 25°C.
§
rO = ∆VO/IO. This is defined at the output terminals, not at the measurement point of Figure 1.
CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS
MIN TYP‡MAX UNIT
I
DD
Static supply current Outputs high or low (V
DDP
= 0 V) 6.5 mA
I
DDL
Static supply current (LVCMOS) Outputs high or low (V
DDP
= 0 V) 50 µA
pp
300 MHz 39 mA
I
DD(NORMAL)
Supply current in normal state
400 MHz 50 mA
I
DDL(NORMAL)
Supply current in normal state (LVCMOS)
400 MHz 8 mA
VDD refers to any of the following; VDD, V
DDL
, and V
DDP
All typical values are at VDD = 3.3 V, V
DDL
= 1.8 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
MAX UNIT
t
(cycle)
Clock cycle time (CLK, CLKB) 2.5 3.7 ns Total jitter over 1, 2, 3, 4, 5, or 6
300 MHz
140
p
t
cj
j ,,,,,
clock cycles
400 MHz
See Figure 3
100
ps
300 MHz
400
p
tjLLong-term jitter
400 MHz
See Figure 4
300
ps
t
DC
Output duty cycle over 10,000 cycles See Figure 5 45% 55%
p
300 MHz
70
p
t
DC,ERR
Output cycle-to-cycle duty cycle error
400 MHz
See Figure 6
55
ps
tr, t
f
Output rise and fall times (measured at 20%-80% of output voltage)
#
CLK, CLKB See Figure 9, 160 400 ps
t
Difference between rise and fall times on a single device (20%–80%) |tf – tr|
#
See Figure 9, 100 ps
t
c(LCLK)
Clock cycle time (LCLK) 106.6 142.2 ns
t
(cj)
LCLK cycle jitter
§
See Figure 11 –0.2 0.2 ns
t
(cj10)
LCLK 10-cycle jitter
§¶
See Figure 11 –1.3 t
(cj)
1.3 t
(cj)
ns
t
DC
Output duty cycle LCLK 40% 60%
tr, t
f
Output rise and fall times (measured at 20%-80% of output voltage)
LCLK See Figure 9 1 ns
p
f
mod
= 50 kHz –3
PLL loop bandwidth
f
mod
= 8 MHz –20
dB
All typical values are at VDD = 3.3 V, TA = 25°C.
Output short-term jitter specification is peak-to-peak (see Figure 9).
§
LCLK cycle jitter and 10-cycle jitter are defined as the difference between the measured period and the nominal period.
LCLK 10-cycle jitter specification is based on the measured value of LCLK cycle jitter.
#
VDD= 3.3 V
CDCR61A DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
39 Ω, ±5%
68 , ±5%
68 , ±5%
3 pF See Note A
100 pF
39 Ω, ±5%
3 pF
See Note A
RT = 28
RT = 28
(CLK) Measurement
Node (CLKB)
NOTE A: These capacitors represent parasitic capacitance. No discrete capacitors are used on the test
board during device characterization.
Figure 1. Test Load and Voltage Definitions (V
O(STOP)
, V
O(X)
, VO, VOH, VOL)
CLK
CLKB
t
c1
t
c2
Cycle-to-cycle jitter = | tc1 – tc2| over 10000 consecutive cycles
Figure 2. Cycle-to-Cycle Jitter
CLK
CLKB
t
c(i)
t
c(i)
= nominal expected time
Cycle-to-cycle jitter = | t
c(i)
– t
c(i+1)
| over 10000 consecutive cycles
t
c(i+1)
Figure 3. Short-Term Cycle-to-Cycle Jitter over 2, 3, 4, or 6 Cycles
CLK
CLKB
t
(cycle)
tjL = | t
(cycle), max
– t
(cycle), min
| over 10000 consecutive cycles
Figure 4. Long-Term Jitter
CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CLK
CLKB
t
pW+
t
(cycle)
Duty cycle (tDC) = (t
pW+/t(cycle)
)
Figure 5. Output Duty Cycle
CLK
CLKB
t
pW+(i)
t
(cycle)
Duty cycle error (t
DC,ERR
) = t
pW+(i)
– t
pW+(i+1)
t
pW+(i+1)
t
(cycle)
Figure 6. Duty Cycle Error (Cycle-to-Cycle)
CLK
CLKB
V
O(X)+
V
O(X), nom
V
O(X)–
Figure 7. Crossing-Point Voltage
LCLK
10 pF
1.8 V
120
120
80%
t
f
t
r
20%
V
OL
V
OH
Figure 8. LCLK Test Load Circuit and Voltage Waveform for CLK/CLKB and LCLK
CDCR61A DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
ООООООО
VDD, V
DDP
, or
S0
CLK/CLKB
t
(STL)
Figure 9. PLL Frequency Transition Timing
LCLK
t
(cj)
t
(cj10)
Figure 10. LCLK Jitter
CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE
SCAS626 – FEBRUARY 2000
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE P ACKAGE
4040064/E 08/96
14 PIN SHOWN
Seating Plane
1,20 MAX
1
A
7
14
0,19
4,50 4,30
8
6,20
6,60
0,30
0,75 0,50
0,25
Gage Plane
0,15 NOM
0,65
M
0,10
0°–8°
0,10
PINS **
A MIN
A MAX
DIM
2,90
3,10
8
4,90
5,10
14
6,60
6,404,90
5,10
16
7,70
20
7,90
24
9,60
9,80
28
0,15 0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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