Texas Instruments CDCR61APWR Datasheet

CDCR61A

DIRECT RAMBUS CLOCK GENERATOR – LITE

SCAS626 – FEBRUARY 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

400-MHz Differential Clock Source for
Direct Rambus Memory Systems for an
800-MHz Data Transfer Rate

D

Operates From Two (3.3-V and 1.80-V)
Power Supplies With 180 mW (Typ) at 400
MHz Total

D

Packaged in a Thin Shrink Small-Outline
Package (PW)

D

External Crystal Required for Input

description

The Direct Rambus clock generator – lite (DRCG-Lite) is an independent crystal clock generator. It performs
clock multiplication using PLL, sourced by an internal crystal oscillator. It provides one dif ferential, high-speed
Rambus channel compatible output pair. Also, one single-ended output is available to deliver 1/2 of the crystal
frequency. The Rambus channel operates at up to 400 MHz with an option to select 300 MHz as well. The
desired crystal is a 18.75-MHz crystal in a series resonance fundamental application.

The CDCR61A is characterized for operation over free-air temperatures of 0°C to 85°C.

functional block diagram

/2

OSC

PLL

BUSCLK

LCLK

2

S0

XTAL

XOUT

XIN

S1 S2

DIV

V

DDP

BUSCLK FREQUENCY SETTINGS

S0

M (PLL MULTIPLIER)

0 16

1 or Open 64/3

FUNCTION TABLE

V

DDP

S1 S2 MODE CLK CLKB LCLK

ON 0 0 Normal CLK CLKB XIN divided by 2
ON 1 1 Normal CLK CLKB XIN divided by 2
ON 0 1 Test Divided by 2 Divided by 2 XIN divided by 2
ON 1 0 Test Divided by 4 Divided by 4 XIN divided by 2
0 V 0 0 Test XIN XIN (invert) XIN divided by 2
0 V 1 1 Test XIN XIN (invert) XIN divided by 2
0 V 0 1 Test XIN divided by 2 XIN (invert) divided by 2 XIN divided by 2
0 V 1 0 Test XIN divided by 4 XIN (invert) divided by 4 XIN divided by 2

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Direct Rambus and Rambus are trademarks of Rambus Inc.

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

V

DDP

GNDP

XOUT

XIN

V

DDL

LCLK

GNDL

S1

S0
V

DD

GND
CLK
CLKB
GND
V

DD

S2

PW PACKAGE

(TOP VIEW)

CDCR61A
DIRECT RAMBUS CLOCK GENERATOR – LITE

SCAS626 – FEBRUARY 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

CLK 13 O Output clock, connect to Rambus channel
CLKB 12 O Output clock (complement), connect to Rambus channel
GNDP, GNDL,

GND

2, 7,

11, 14

Ground

LCLK 6 O LVCMOS output, 1/2 of crystal frequency
S0, S1, S2 16, 8, 9 I LVTTL level logic select terminal for function selection
V

DD

10, 15 Power supply, 3.3 V

V

DDP

1 Power supply for PLL, 3.3 V (0 V for Test mode)

V

DDL

5 Power supply for LCLK, 1.8 V
XIN 4 I Reference crystal input
XOUT 3 O Reference crystal feedback

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, VDD or V

DDP

(see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range, V

DDL

(see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range,V

I

, at any input terminal –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO, at any output terminal (CLK, CLKB) –0.5 V to V

DD

+ 0.5 V. . . . . . . . . . . . . . . . . . . .

Output voltage range, VO, at any output terminal (LCLK) –0.5 V to V

DDL

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . .

ESD rating (MIL-STD 883C, Method 3015) > 2 kV, Machine Model >200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation see Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

0°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to the GND terminals.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

‡

TA = 85°C

POWER RATING

PW 1400 mW 11 mW/°C 740 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.

CDCR61A

DIRECT RAMBUS CLOCK GENERATOR – LITE

SCAS626 – FEBRUARY 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

DD

3 3.3 3.6 V

LCLK supply voltage, V

DDL

1.7 1.8 2.1 V

p

S0 0.35×V

DD

Low-level input voltage, V

IL

S1, S2 0.35×V

DD

V

p

S0 0.65×V

DD

High-level input voltage, V

IH

S1, S2 0.65×V

DD

V

p

p

S0 10 55 100

Internal pullup resistance

S1, S2 90 145 250

kΩ

p

CLK, CLKB 16

Low-level output current, I

OL

LCLK 10

mA

p

CLK, CLKB –16

High-level output current, I

OH

LCLK –10

mA

Input frequency at crystal input 14.0625 18.75 MHz

S0, S1, S2 2.5

p

I

nput capacitance

(CMOS), C

I

†

XIN, XOUT 20

pF

Operating free-air temperature, T

A

0 85 °C

†

Capacitance measured at f = 1 MHz, dc bias = 0.9 V , and VAC < 100 mV

timing requirements

MIN MAX UNIT

Clock cycle time, t

(cycle)

2.5 3.7 ns
Input slew rate, SR 0.5 4 V/ns
State transition latency (V

DDX

or S0 to CLKs – normal mode), t

(STL)

3 ms

crystal specifications

MIN MAX UNIT

Frequency 14.0625 18.75 MHz
Frequency tolerance (at 25°C ±3°C) –15 15 ppm
Equivalent resistance (CL = 10 pF) 100 Ω
Temperature drift (–10°C to 75°C) 10 ppm
Drive level 0.01 1500 µW
Motional inductance 20.7 25.3 mH
Insulation resistance 500 MΩ
Spurious attenuation ratio (at frequency ±500 kHz) 3 dB
Overtone spurious 8 dB