Texas Instruments CDCM7005 User Manual

CDCM7005 (QFN Package)
Evaluation Module Manual

HPA/High Speed Communications

User’s Guide

2005 Clock Drivers

SCAU015

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Copyright  2005, Texas Instruments Incorporated

EVM IMPORTANT NOTICE

Texas Instruments (TI) provides the enclosed product(s) under the following conditions:

This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
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Post Office Box 655303
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Copyright  2004, Texas Instruments Incorporated

EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the supply voltage range of 3 V and 3.6 V.

Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.

Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than
45°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.

Mailing Address:

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Post Office Box 655303
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Copyright  2004, Texas Instruments Incorporated

About This Manual

This manual explains how to use the CDCM7005 evaluation module (EVM)
and provides guidelines to build the customer’s own systems. The manual
includes schematics, layout, bill of materials, and a software description.

How to Use This Manual

Related Documentation From Texas Instruments

Preface

Read This First

This document contains the following chapters:

- Chapter 1—Introduction

- Chapter 2—Quick Start

- Chapter 3—EVM Hardware

- Chapter 4—Serial Peripheral Interface (SPI) Software

- Chapter 5—Schematics, Board Layout, and Parts List

Related Documentation From Texas Instruments

- CDCM7005 Data Sheet, SCAS793, Texas Instruments

FCC Warning

This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.

If You Need Assistance. . .

If you need assitance with this device, please email

[e-mail]

iii

Contents

Contents

1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 CDCM7005 Functional Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Quick Start 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 EVM Hardware 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Board View and Connector Location 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Hardware Configuration 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Power Supply (P1, P2) 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Onboard Switches and Indicators (SW1−SW2, D1−D4) 3-2. . . . . . . . . . . . . . . . . . .

3.2.3 Programming Interfaces (J30, J31) 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.4 Loop Filter (J32−J34) 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.5 High-Speed Outputs and Inputs (J1−J4, J6−J11, J13, J14, J22, and J23) 3-3. . .

3.2.6 VCXO Inputs and Outputs (J16−J18) 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.7 AC-Coupling at PRI_REF (C1, R4, R6) and SEC_REF (C5, R13, R15) 3-4. . . . .

4 Serial Peripheral Interface (SPI) Software 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Functional Description 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Software Installation 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Application Level Circuit Diagram 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Application Circuit Diagram 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.1 Passive Loop Filter 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.2

6 Parts List, Board Layouts, and Schematics 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Parts List 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Board Layout 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Schematic 6-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Active Loop Filter Using OPA341 5-3. . . . . . . . . . . . . . . . . . . . . . . . . .

v

Contents

Figures

3−1 Board View 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 Screen View 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 CDCM7005 With a Passive Loop Filter Configuration 5-2. . . . . . . . . . . . . . . . . . . . . . . . .

5−2 CDCM7005 With an External Active Loop Filter Using OPA341 5-3. . . . . . . . . . . . . . . . . . . . .

6−1 Component View and Silkscreen (Top Side) 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−2 Component View and Silkscreen (Bottom Side) 6-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−3 Top Layer View 6-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−4 Bottom Layer View 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−5 Ground Plane View 6-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−6 Power Layer View 6-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

3−1 Filter Configurations 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

Chapter 1

Introduction

The CDCM7005 is a high-performance, low phase noise and low skew clock
synchronizer that synchronizes an on-board voltage controlled crystal
oscillator (VC(X)O) frequency to an external reference clock. The device
operates up to 2.2 GHz. The PLL loop bandwidth and damping factor can be
adjusted to meet different system requirements by selecting the external
VC(X)O, loop filter components, frequency for PFD, and charge pump current.
Each of the five differential LVPECL and five LVCMOS pair outputs can be
programmed by a serial peripheral interface (SPI). The SPI allows individual
control of the frequency and enable/disable state of each output. As the
system requires external components like a loop filter and VC(X)O, this EVM
provides an easy method to evaluate and modify the performance and
parameters of the clock system in conjunction with the specific customer
application. Loop bandwidth can be selected as low as 10 Hz or less, allowing
the device to clean the system’s clock jitter.

In non PLL mode, the CDCM7005 can be used as a simple LVPECL or
LVCMOS buffer with divider options.

Topic Page

1.1 CDCM7005 Functional Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction

1-1

CDCM7005 Functional Block Diagram

1.1 CDCM7005 Functional Block Diagram

REF_SEL

PRI_REF

SEC_REF

CTRL_LE

CTRL_DATA

CTRL_CLK

RESET or
HOLD

VCXO_IN

VCXO_IN

VBB

freq. detect

Clock

> 2 MHz

AVCC

Progr. Delay

Progr. Delay

PECL

to

LVCMOS

FB_MUX

VCC

Selected REF Signal

Manual &
Automatic

CLK Select

LVCMOS

PD

REF_MUX

SPI LOGIC

Reference

Clock

freq. detect

> 2 MHz

Feedback

÷ 1

÷ 2

÷ 3

÷ 4

PECL
INPUT

÷ 6

/8

÷ 8

÷ 16

÷ 4

÷ 8

P16−Div

o

90

o

90

P Divider

Bias Generator

VCC − 1.3 V

VCC_CP

STATUS_REF /
PRI_SEC_CLK

STATUS_VCXO
/ I_REF_CP

PLL_LOCK

LOCK

Progr. Divider

M

N

10

M 2

Progr. Divider

12

N 2

PFD

HOLD

Charge

Pump

Current

Reference

LV

CMOS

LV

Y0_MUX

Y1_MUXY2_MUXY3_MUXY4_MUX

PECL

LV

CMOS

LV

CMOS

LV

PECL

LV

CMOS

LV

CMOS

LV

PECL

LV

CMOS

LV

CMOS

LV

PECL

LV

CMOS

LV

CMOS

LV

PECL

LV

CMOS

CP_OUT

Y0A

Y0B

Y1A

Y1B

Y2A

Y2B

Y3A

Y3B

Y4A

Y4B

1-2

GND

Chapter 2

Quick Start

In order to setup the EVM quickly and to take some measurements at default
settings, the following actions are required:

- Supply 3.3 V to P1, LED D4 will be on.

- Apply a single-ended reference clock to the reference clock input

PRI_REF (pin A1) or SEC_REF (pin B1). For default setting, the reference
clock must be 1/8
PRI_REF is selected. If REF_SEL is set to 0, then SEC_REF is selected.
This selection can be realized via J26 (header 1 and 2 is high; header 2
and 3 is low).

- Connect Y0/Y0B (or Y1/Y1B) to oscilloscope in order to check an output

signal. Ensure the oscilloscope has 50 Ω to ground termination.

th

of the VC(X)O frequency. If REF_SEL is set to 1, then

After power up, D1 is on if there is a valid reference clock and D2 is on if there
is a valid VC(X)O clock for the CDCM7005. If D3 turns on, then the reference
clock and the VC(X)O clocks are phase locked.

Quick Start

2-1

Chapter 3

EVM Hardware

This chapter discusses the EVM hardware.

Topic Page

3.1 Board View and Connector Location 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Hardware Configuration 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EVM Hardware

3-1

Board View and Connector Location

3.1 Board View and Connector Location

Figure 3−1. Board View

3.2 Hardware Configuration

This section describes the board configuration using on-board jumpers and
solder bridges.

3.2.1 Power Supply (P1, P2)

- Supply 3.3 V ±10% on P1 and P2 using a stabilized external power supply.

J WARNING: Never supply more than 3.6 V on P1.

3.2.2 Onboard Switches and Indicators (SW1−SW2, D1−D4)

- Push SW1 to enter the power-down mode of the CDCM7005 device. Then

all current sources are switched off, all outputs are switched into 3-state,
and all dividers (M, N, and P) are reset to default.

- Push SW2 to enter the reset mode of the device. The charge pump (CP)

is switched to 3-state and all counters (N, M, P) are rest to zero (the initial
divider settings are maintained in SPI.

- The three status outputs of the CDCM7005 are fed to LED indicators. D1

on indicates a valid reference input clock signal. D2 is on if the VC(X)O
input clock is valid and D3 turns on if the PLL has been locked.

- D4 indicates power supply

Note:

3-2

In case of a low input impedance of the VC(X)O control voltage input, there
is a possibility D3 may not turn on to indicate locking.

3.2.3 Programming Interfaces (J30, J31)

The SPI of the device is used for writing to the control register of the device.
It consists of three control lines CTRL_CLK, CTRL_DATA, and CTRL_LE.
There are four 30-bit wide RAM registers, which can be addressed by the two
LSBs of a transferred word. Every transmitted word must have 32 bits, starting
with MSB. After supplying power or activating the power-down mode, the
registers are loaded with the device default values internally (see the
CDCM7005 data sheet, SCAS793). However, if specific register settings are
required for any applications, there are two ways to program the device
externally:

- Connect the parallel port cable to the PC and EVM parallel port. This

needs control S/W (see Chapter 4).

3.2.4 Loop Filter (J32−J34)

The loop filter is one of the key elements determining the loop bandwidth of
the PLL. The loop filter converts the charge pump current into the control
voltage for the voltage controlled oscillator. The phase difference between the
input clocks of the phase frequency detector determines the width of the
charge pump output current pulses. These high frequency pulses are
transformed into a voltage to control the oscillator.

Hardware Configuration

Basically, three types of loop filters are implemented on the EVM.

- Passive loop filter

- External active loop filter using an external low-noise OPA.

Filter types can be selected by soldering bridges J32−J34, see Table 3−1.
Control voltage of the VC(X)O can be measured at J9 or TP1. If an external
OPA is used, it needs to be switched on by connecting J34. For example,
passive filter operation is provided when pads 1 and 3 of J33 are solder bridged
and pads 1 and 3 of J32 are solder bridged.

Default setting: Passive Loop Filter

Table 3−1. Filter Configurations

Bridge Passive Filter Active With An External OPA

J33 1−3 1−2

J34 Open Closed

J32 1−3 1−2

3.2.5 High-Speed Outputs and Inputs (J1−J4, J6−J11, J13, J14, J22, and J23)

The CDCM7005 drives five differential LVPECL outputs. All PECL outputs are
ac-coupled and terminated with 150 Ω to GND. This is in contrast to typical
LVPECL termination, which requires V
reason is to simplify the power supply scheme. The device output’s trace
impedance is 50 Ω and traces are matched in length. All outputs have options
for pullup and pulldown resistors.

− 2 V as termination voltage. The

CC

EVM Hardware

3-3

Hardware Configuration

When the CDCM7005 is powered up, it defaults to five LVPECL outputs.
However, this EVM is configured as follows:

- Y0 − Y2 = LVPECL

- Y3, Y4 = LVCMOS (in addition Y4 has an option for a custom filter)

The reference input clock signal has to be applied to J1 or J6. The reference
input clock signal can be sensed on J4. In this case, close the bridge J5 (the
oscilloscope’s 50 Ω may be used to terminate the 50-Ω trace). The reference
input clock sense line is matched to the LVPECL outputs line to avoid any
additional delay offset. The input is ac-coupled (C4).

3.2.6 VC(X)O Inputs and Outputs (J16−J18)

The CDCM7005 requires an external VC(X)O in order to complete the PLL
loop. The VC(X)O adjusts the frequency and phase depending on the control
voltage level coming from the loop filter and provide the input clock to the
LVPECL block.

Another option would be to use an external source via J16 and J18.

3.2.7 AC-Coupling at PRI_REF (C1, R4, R6) and SEC_REF (C5, R13, R15)

An ac-coupling is provided at PRI_REF and SEC_REF to ease the use of the
CDCM7005 with different signaling levels (LVCMOS, LVPECL, LVDS,...).
However, the ac-coupling will increase the PLL stabilization time after power
up due to transient effects. It also increases the switching time between
PRI_REF and SEC_REF in case of automatic reference clock switching.
Therefore, the ac-coupling must be removed for optimized system
performance (C1 and C5 has to be replaced with an 0-Ω resistor and R4, R6,
R13, and R15 have to be removed).

3-4

Chapter 4

Serial Peripheral Interface (SPI) Software

This chapter discusses the serial peripheral interface software.

Topic Page

4.1 Functional Description 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Software Installation 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Peripheral Interface (SPI) Software

4-1

Functional Description

4.1 Functional Description

Programming software here as described is intended for programming the in­ternal control register of the CDCM7005. The software runs under Win­dows98, NT, 2000, and XP. A quick installation is required prior to use. See the
Software Installation section.

There are several cases where programming is mandatory.

As a rule of thumb here are some examples:

- Use of active loop filter

- Change of divider ratio or disable of certain LVPECL/LVCMOS outputs

- Select between LVPECL or LVCMOS output

- Change of phase offset, (Delay M/N), or selection of 90’ or 180’ phase shift

- Change of charge pump output current.

- Widening the lock detect window

Figure 4−1. Screen View

4.2 Software Installation

Follow the steps below in order to install the SPI control software:

1) Run program setup.exe in the Installer folder

2) Reboot your computer

3) Run the Software from Start −> Programs −> CDCM7005_EVM −>
CDCM7005_EVM

4-2

Chapter 5

Application Circuit Diagram

This chapter discusses the application circuit diagram.

Topic Page

5.1 Application Circuit Diagram 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Application Circuit Diagram

5-1

Application Circuit Diagram

5.1 Application Circuit Diagram

The following applications sections the two loop filter configurations are
discussed.

5.1.1 Passive Loop Filter

The passive loop filter is a second order filter (two poles, one zero). The zero
is required for the overall loop stability. R1, C1, and C2 generate the dominant
pole of the system. A second pole is introduced by R2 and C3.

Figure 5−1. CDCM7005 With a Passive Loop Filter Configuration

SPI

V

CC

130 Ω

R
82 Ω

V

CC

130 Ω

PECL_OUT_B

PECL_OUT

R
82 Ω

CDCM7005

PRI_REF

SEC_REF

CTRL_LE
CTRL_DATA
CTRL_CLK

STATUS_VC(X)O

VC(X)O_IN

VC(X)O_IN_B

VC(X)O

491.52 MHz

CP_OUT

STATUS_REF

PLL_LOCK

YnA

YnB

150 Ω

V_CTRL

R

R
150 Ω

Low-Pass Filter

R2

160 Ω

C3
100 nF

R1

4.7 kΩ

C1
22 µF

10 nF10 nF

10 nF

C2
100 nF

5-2

Application Circuit Diagram

5.1.2 External Active Loop Filter Using OPA341

Figure 5−2. CDCM7005 With a External Active Loop Filter Using OPA341

SPI

V

CC

130 Ω

R
82 Ω

V

CC

130 Ω

R
82 Ω

PECL_OUT_B

PECL_OUT

CDCM7005

PRI_REF

SEC_REF

CTRL_LE
CTRL_DATA
CTRL_CLK

VC(X)O_IN

VC(X)O_IN

VC(X)O

491.52 MHz

CP_OUT

STATUS_REF

STATUS_VC(X)O

PLL_LOCK

YnA

YnB

150 Ω

Low-Pass Filter

R3

4.7 kΩ

R1

C1
100 nF

C3
100 nF

R2

InN

OPA341

InP

10 kΩ

Vcc

C2

10 µF

Out

V_CTRL

Vcc

R5
10 kΩ

180 Ω

R6
10 kΩ

C1
100 nF

10 nF

10 nF

R

R
150 Ω

Application Circuit Diagram

5-3

Chapter 6

Parts List, Board Layout, and Schematics

This chapter contains the parts list, board layout, and schematics for the
CDCM7005 EVM.

Topic Page

6.1 Parts List 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Board Layout 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Schematics 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parts List, Board Layout, and Schematics

6-1

Parts List

6.1 Parts List

Item QTY Reference

Designator

1 24 C1−C9, C12,

C13, C15, C17,
C26, C40, C41,
C46, C47, C53,
C54, C56−C58,

C66

2 2 C72, C10 smd_cap_0402 100 nF Panasonic

3 7 C11, C32,

C62−C64, C68,

C73

4 2 C14, C16 smd_cap_0402 0 Ω Panasonic

5 1 C18 smd_cap_0402 1000 pF Panasonic

6 1 C19 smd_cap_0603 1 µF Panasonic

7 2 C20, C22 smd_cap_0402 0.1 µF Panasonic

8 1 C21 smd_cap_0402 10 nF Panasonic

9 1 C23 smd_cap_0402 NU 1.1 pF NU Rohm

10 1 C24 smd_cap_0402 22 pF Panasonic

11 1 C25 smd_cap_0402 NU 1 pF NU Rohm

12 7 C27−C29, C75,

C76, C79, C80

13 1 C30 smd_cap_1210 22 µF Murata

14 1 C31 smd_cap_0402 22 nF Panasonic

15 3 C33−C35 smd_cap_0402 10 nF Panasonic

16 4 C36, C42, C48,

C49
C49 smd_cap_1210_pol 22 µF Panasonic

17 5 C37, C43, C50,

C55, C65

18 3 C38, C44, C51 smd_cap_0402 100 nF Yageo

19 3 C39, C45, C52 smd_cap_0402 33 nF AVX 0402YD333KAT2A
20 4 C59−C61, C67 smd_cap_0402 2.2 nF AVX 0402YC223KAT2A
21 3 C69−C71 smd_cap_0402 10 pF Panasonic

Footprint Part Part Number

smd_cap_0402 10 nF Panasonic

ECJ−0EB1E103K

ECJ−0EB1E104K

smd_cap_0402 100 pF Panasonic

ECJ−0EB1E101K

ERJ−2GE0R00X

ECJ−0EB1E102K

ECJ−1VF1C105Z

ECJ−0EB1A104K

ECJ−0EB1E103K

MCH155A1R1CK

ECJ−0EC1H220J

MCH155A1R1CK

smd_cap_0805 0.1 µF Panasonic

ECP−U1C104MA5

GRM32ER71A226KE20L

ECJ−0EB1E104K

ECJ−0EF1H103Z

smd_cap_1210_pol 22 µF Panasonic

ECS−T1CC226R

ECS−T1CC226R

smd_cap_1210_pol 10 µF Panasonic

ECS−H1CC106R

04022F104Z7B20D

ECD−G0E100C

6-2

Parts List

QTY Reference

Item

Designator

22 2 C74 smd_cap_1210 10 µF Murata

C77 smd_cap_1210 10 µF Murata

23 1 C78 smd_cap_0805 NU Panasonic

24 3 D1−D3 smd_led_1206 Amber Lite−On LTST−C150AKT
25 1 D4 smd_led_1206 GREEN Lite−On

26 1 FLT1 ts−38s TS−38S Toyocom Filter
27 7 J1−J4, J6−J8 sma_alt SMA Johnson Comp

28 1 J5 jumper2 HEADER 2

29 9 J9−J11, J13,

J14, J16, J18,

J22, J23

30 4 J12, J25, J26,

J27

31 2 J17, J15 smd_bridge_0402 SMD3P_BRIDGE Panasonic

32 1 J19 jumper2 HDR2 Header 2 pos, 0.1 ctr
33 2 J21, J20 smd_bridge_0402 SMD3P_BRIDGE Panasonic

34 3 J24, J28, J29 jumper2 HDR2 Header 2 pos, 0.1 ctr
35 1 J30 dcon25m PARALLEL

36 1 J31 jumper4 HDR4 Header 4 pos, 0.1 ctr
37 2 J33, J32 JUMPER3_SMD_WVIA_CD

38 1 J34 jumper2 HDR2 Header 3 pos, 0.1 ctr
39 1 L1 smd_cap_0603 75 Ω at100 MHz Murata

40 1 L2 smd_cap_0603 470 nH Murata

41 2 L4, L3 smd_cap_0603 180 nH Panasonic

42 3 L5−L7 smd_cap_0603 75 Ω at 100 MHz Murata

43 1 L8 smd_cap_0805 2.2 nH J W Miller Magnetics

44 1 P1 banana_jack PWR_IN SPC Technologies 845R
45 1 P2 banana_jack GND SPC Technologies 845B
46 18 R1, R2, R7, R9,

R10, R11, R16,
R18−R20, R22,
R24, R26, R27,
R30, R35, R48,

R50

47 2 R3, R12 smd_res_0402 NU Panasonic

Footprint Part Part Number

GRM32DR61E106KA12L

GRM32DR61E106KA12L

ECP−U1C104MA5

LTST−C150KGKT

142−0701−841

sma_alt NU_SMA Johnson Comp

142−0701−841

hdr3_100ctr HDR3 Header 3 pos, 0.1 ctr

ERJ−2GE0R00X

ERJ−2GE0R00X

SPC Technology

PORT

HDR 3_cdc7005 Use 0 W to short pins

C7005

smd_res_0402 NU 100 Ω Panasonic

DB−25P−PCB

(see assy dwg)

BLM18BA750SN1D

LQW18ANR47J00D

ELJ−FJR18JF2

BLM18BA750SN1D

PM0805−2N2M

ERJ−2RKF1000X

ERJ−2GEJ510X

Parts List, Board Layout, and Schematics

6-3

Parts List

QTY Reference

Item

Designator

48 7 R4, R6, R13, R15,

R62, R63, R65

49 6 R5, R8, R14, R17,

R21, R23

50 10 R25, R57, R59,

R60, R68−R71,

R74, R75

51 2 R28, R45 smd_res_0402 NU 0 Ω Panasonic

52 4 R29, R32, R49,

R80

53 2 R38, R31 smd_res_0402 130 Ω Panasonic

54 10 R33, R34, R41,

R42, R82,−R87

55 2 R43, R36 smd_res_0402 82 Ω Panasonic

56 2 R37, R44 smd_res_0402 NU NU
57 2 R39, R40 smd_res_0402 62 W Panasonic

58 2 R47, R46 smd_res_0402 NU 100 Panasonic

59 4 R51, R64, R66,

R67

60 1 R52 smd_res_0402 160 Ω Panasonic

61 2 R53, R72 smd_res_0402 4.7 kΩ Panasonic

62 3 R54−R56 smd_res_0402 750 Panasonic

63 1 R58 smd_res_0402 NU 12K 1% Panasonic

64 1 R61 smd_cap_0402 1.5 kΩ Panasonic

65 1 R73 smd_res_0402 180 Ω Panasonic

66 3 R78, R79, R81 smd_res_0402 22 Ω Panasonic

67 2 SW2, SW1 switch_reset SW

68 2 TP1, TP2 testpin_30dia T POINT R Test point
69 1 U2 mbga_pt8mm_64_skt CDCM7005 Texas Instruments

70 1 U3 soic14 SN74LV125 Texas Instruments

71 1 U4 soic_round_4 NU SGA−4586 NU Sirenza SGA−4586
72 1 U5 soic8 OPA341 Texas Instruments

73 1 VCXO1 VCXO_6 VCXO_6 Toyocom VCXO
74 4 MP3 STAND OFF Legs for PCB

75 4 MP2 SCREW Legs for PCB

Footprint Part Part Number

smd_res_0402 100 Ω Panasonic

ERJ−2RKF1000X

smd_res_0402 150 Ω Panasonic

ERJ−2RKF1500X

smd_res_0402 10 kΩ Panasonic

ERJ−2RKF1002X

ERJ−2GE0R00X

smd_res_0402 NU 150 Ω Panasonic

ERJ−2RKF1500X

ERJ−2GEJ131X

smd_res_0402 0 Ω Panasonic

ERJ−2GE0R00X

ERJ−2GEJ820X

ERJ−2GEJ620X

ERJ−2RKF1000X

smd_res_0402 100 kΩ Panasonic

ERJ−2RKF1003X

ERJ−2RKF1002X

ERJ−2RKF1472X

ERJ−2GEJ131X

ERJ−2RKF4121X

ERJ−2RKF1501X

ERJ−2RKF1472X

ERJ−2GEJ220X
KT11P3JM

PUSHBUTTON

CDCM7005

SN74LV125AD

OPA341UA

6-4

6.2 Board Layout

Figure 6−1. Component View and Silkscreen (Top View)

Parts List

Parts List, Board Layout, and Schematics

6-5

Parts List

Figure 6−2. Component View and Silkscreen (Bottom View)

6-6

Figure 6−3. Top Layer View

Parts List

Parts List, Board Layout, and Schematics

6-7

Parts List

Figure 6−4. Bottom Layer View

6-8

Figure 6−5. Ground Plane View

Parts List

Parts List, Board Layout, and Schematics

6-9

Parts List

Figure 6−6. Power Layer View

6.3 Schematics

6-10

The following pages contain the schematics for the CDCM7005 (QFN
package).

Parts List

C

B

A

45

1

C64

100P

1 2

GND

C63

100P

1 2

C62

100P

1 2

2.2n

C61

12

C60

2.2n

12

2.2n

VCC

C59

12

C58

12

C57

12

C56

12

12

C68

10n

10n

10n

C55

10uF

100P

1 2

GND

C67

2.2n

12

C66

10n

12

C65

10uF

12

AVCC

2

1

CDCM7005EVM_QFN−SCH

Tuesday, April 26, 2005

CDCM7005_QFN Evaluation Module

B

Title

Size Document Number R e v

D a te: Sheetof

2

3

C40

10n

12

C39

33n

12

C38

100n

12

C37

10uF

12

C36

22uF

12

VCC_CP

4

5

L5

1 2

75 OHM @ 100MHZ

GND

C46

10n

12

C45

33n

12

C44

100n

12

C43

10uF

12

C42

22uF

12

AVCC

L6

1 2

75 OHM @ 100MHZ

GND

VCC

L7

P1

12

12

12

12

12

1 2

75 OHM @ 100MHZ

12

PWR_IN

1

1

C53

10n

C52

33n

C51

100n

C50

10uF

C49

22uF

GND

C48

22uF

12

D4

GREEN

R61

12

PW R_IN

GND

1.5K

1

1

P2

GND

3

4

5

D D

C

B

Parts List, Board Layout, and Schematics

A A

6-11

Parts List

C

B

A

GND

1

SW1

SW2

GND

1

2

J28

PWRDWN

12

C34

R5910K

1 2

2

Y1

PW R_ DW N

Y1B

Y2

3

7

1

4

U2

/PD

Y2A

Y1A3Y1B

GND

1

2

J29

GND

12

C3510n

10n

R60

10K

1 2

RESET RST

J27

Y2B

Y3

Y3B

8

12

11

14

Y2B

Y3B

Y3A

R58

Y4

Y4A16Y4B

D3Amber

NU 12K 1%

1 2

3
2
1

STAT_VCXO/I_REF_CP

Y4B

17

GND

1 2
12

R 56 750

STAT_VCXO

GND

D2Amber

1 2

12

R 55 750

22

23

24

GND

GND

D1Amber

1 2

12

R 54 750

PLLLOCK

3
2

J25

1

C3310n

PLL_LOCK

1 2

GND

CTRL_DATA

25

26

GND

CDCM7005

PLL_LOCK

CTRL_DATA

/RESET or /HOLD

35

1

CDCM7005EVM_QFN−SCH

Tuesday, April 26, 2005

CDCM7005_QFN Evaluation Module

B

Title

Size Document Number R e v

D a te: Sheetof

2

3

6-12

STATUS_VCXO or I_REF_CP

STATUS_REF or PRI_SEC_CLK

PRI_REF

REF_SEL

REF_SEL

35

VCC_CP

22n

1 2

C31

GND

J26

VCC_CP

33

32NC34

AVCC

100P

1 2

C32

GND

AVCC

CTRL_CLK

CTRL_LE

AVCC30CP_OUT

AVCC

27

28

29

31

CTRL_CLK

CTRL_LE

CP_OUT

B

A A

4

5

AVCC39AVCC38SEC_REF37PRI_REF

VCXO_IN43VCXO_INB42VBB

4

5

D D

Y0A46Y0B

36

40

47

Y0B

Y0

C

AVCC

VCXO_IN

VCXO_INB

VBB

SEC_REF

123

12

R 57 10K

VCC

Parts List

C

B

A

15Tuesday, April 26, 2005

1

1

CDCM7005EVM_QFN−SCH

CDCM7005_QFN Evaluation Module

B

D a te: Sheetof

Title

Size Document Number R e v

C80

.1uF

1 2

R75

2

−

OPA341

R71 10K

10K

12

GND

2

1

GND

8

U5

R73

12

12

4.7K

R72

C78

1 2

NU

12

10uF

C77

CP_OUT

180

C79

2
1

J33

3

12

.1uF

GND

3

R74

10K

12

J34

C75

C74

74
5

1 2

.1uF

1 2

GND

10uF

12

3

+

6

VCC

VCC

L8

1
2

2.2nH

2

3

pin 1 & 2 on J32, J33, J34

4

Passive Filter (Default Setting): short pin 1 & 3 on J3 2, J33

Active Filter w/ External Op Amp: short

5

D D

R70

10K

1 2

V_CTRL

V_CTRL

C76

.1uF

1 2

GND

22uF

C30

4.7K

R53

2
1

J32

3

R51

100K

1 2

12

.1uF

C27

C

GND

1
2

J24

R52

160

1 2

V CHECK

1 2

1 2

GND

C29

.1uF

1 2

C28

.1uF

1 2

B

A A

4

5

Parts List, Board Layout, and Schematics

6-13

Parts List

C

B

A

VCXO_INB

SEC_REF

HEADER 2

J5

100

100

R15

R13

1 2

1 2

VCC

GND

R4

1 2

VCC

PRI_REF

2
1

100

100

R6

1 2

GND

1

NU 0 ohm

1 2

VBB

R28

12

12

R 31 130

VCC

0 ohm

C14

1 2
12

0 ohm

R34

12

0 ohm

R33

12

3

TP2

3

R90

VCC

R20

12

NU 100

R19

C8 10n

TP1

NU_SMA

GND

1 2

3

Y2_SMA

0 ohm

1 2

NU 100

12

1 2

0 ohm

R86

1 2

12

C

V_CTRL

V_CTRL

GND

GND

J10

NU_SMA

1 2

Y2B_SMA

R91

1 2

12

NU 100

R22

1 2

R87

1 2

12

R21

150

2

C5 10n

1 2

C4 10n

C1 10n

1 2

1 2

GND

NU 100

GND

J6

3

GND

VCC

12

NU 100

R10

Y4B

3

SEC_ REFCLK

12

R11

C6 10n

GND

Y1_SMA

R88

NU 100

R84

R12 NU

1 2

GND

SMA

GND

GND

J7

SMA

1 2

3

1 2

0 ohm

1 2

Y1B_SMA

R89

1 2

R16

12

1 2

1 2

R85

0 ohm

1 2

12

1 2

12

R14

150

GND

SMA

J8

0 ohm

NU 100

R18

12

NU 100

GND

C7 10n

0 ohm

R17

150

J9

GND

12

VCC

GND

R3 NU

PRI_CLK_SENSE

1 2

PRI_REFC LK

GND

12

J1

3

3

VCC

4

VCC

R1

12

5

SMA

3

1 2

Y0_SMA

12

R76

0 ohm

1 2

NU 100

C2 10n

1 2

0 ohm

R82

1 2

12

Y0

12

3

GND

3

1 2

GND

Y0B_SMA

J2

SMA

R77

0 ohm

1 2

R2NU 100

R7

NU 100

12

1 2

C3 10n

0 ohm

R83

1 2

12

R5

150

Y1

Y0B

Y1B

D D

J4SMA

GND

SMA

J3

R9

12

VCC

12

R8

150

Y3Y4Y2

Y2B

Y3B

100n

C10

VCC

NU_SMA

0 ohm

R24

C9 10n

0 ohm

1 2

12

R 25 10K

GND

J11

NU 100

GND

150

R23

1 2

C11

6

VCC

VCXO1

V_CTRL

1EN2

123

VCC

GND

12

VCC

GND

100P

4

5

OUT

OUTB

GND

3

J12

VCC

12

R26

GND

VCXO_6

GND

3

R27

NU 100

C 12 10n

OUTB
OUT

GND

J13

NU_SMA

1 2

3

1 2

Y3_SMA

Y3B_SMA

R92

0 ohm

1 2

R93

1 2

NU 100

NU 100

12

R30

1 2

1 2

22 ohm

R79

R78

1 2

1 2

12

R29

NU 150

J15

123

VCXO_IN_SMA

1 2

C15

VCXO_INB_EXT

12

J16

3

GND

NU_SMA

J14

0 ohm

12

R35 NU 10 0

C 13 10n

22 ohm

12

NU 150

R32

VCXO_IN

12

12

12

R45

NU 0 ohm

R43 82

R 38 130

R36 82

GND

12

R37 NU

GND

10n

NU_SMA

GND

GND

GND

GND

B

VCC

0 ohm

1 2

C16

12

0 ohm

R42

12

12

0 ohm

R41

J17

123

VCXO_INB_SMA

1 2

C17

VCXO_IN_EXT

12

J18

3

VCC

2
1

L1

** 75 ohm@100MHz

1 2

12

12

R40

** 62

12

R39

** 62

12

VBB

GND

R44 NU

GND

10n

NU_SMA

GND

J19

C19

** 1uF

C18

** 1000pF

12

12

Def ault setting

3

J20

1

C20

L2

** 470nH

Amp Bypass :

S hort pin 1&2

VCC

** .1uF

of J18 & J22

2

R46

12

** NU 100

FLT1

1

GND

C22

1 2

GND

U4

GND

C21 ** 10n

1 2

3

1 2

Y4_SMA

R95

0 ohm

1 2

12

12

12

5

OUT

IN

L3

12

C23

** NU 1.1pF

12

** .1uF

1

J21

3

3

SGA−4586

2 4

1

12

R80

NU 150

GND

J22

NU_SMA

R47

C24** 22pF

12

** TS−38S

** 180nH

2

GND

** NU 100

C25

** NU 1pF

L4

** 180nH

GND

R48

GND

A A

3

NU 100

1 2

VCC

12

R49

25Tuesday, April 26, 2005

1

CDCM7005EVM_QFN−SCH

CDCM7005_QFN Evaluation Module

B

D a te: Sheetof

Title

Size Document Number R e v

2

3

GND

GND

GND

NU_SMA

J23

0 ohm

12

NU 100

R50

C 26 10n

22 ohm

4

GND

5

GND

1 2

Y4B_SMA

R94

1 2

1 2

R81

1 2

NU 150

6-14

Parts List

C

B

A

55

1

1

CDCM7005EVM_QFN−SCH

Tuesday, April 26, 2005

CDCM7005_QFN Evaluation Module

B

Title

Size Document Number R e v

D a te: Sheetof

2

GND

U3SN74LV125

GND

VCC

R6910K

1 2

GND

GND

27

J30

1 14

2 15

3 16

4 17

5 18

6 19

7 20

8 21

9 22

10 23

11 24

12 25

13 26

PARALLEL PORT

GND

SPI_LE

SPI_CLK

SPI_DATA

123

4

J31

HDR4

R 68 10K

DATA

12

GND

134Y11

103A93Y8

14

12

4A

4OE

3OE

VCC

1A

1Y32OE

1OE

42A52Y6

1

7

2

CLK

LE

VCC

3

VCC

CTRL_LE

CTRL_DATA

CTRL_CLK

R64 100K

12

R 66 100K

12

R63

100

12

VCC

100n

C72

100P

1 2

C73

1 2

GND

12

12

R 67 100K

R65

100

12

R62

100

C 69 10p

4

1 2

1 2

C 71 10p

1 2

C 70 10p

GND

2

3

4

5

D D

C

B

A A

Parts List, Board Layout, and Schematics

5

6-15