Texas Instruments CDCM7005 Datasheet

CDCM7005

VCXO LF

VCXO

IN

VCXO

IN

CP

OUT

PRI

REF

YnA

YnB

OSC

DAC

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CDCM7005

SCAS793G –JUNE 2005–REVISED AUGUST 2017

CDCM7005 3.3-V High Performance Clock Synchronizer and Jitter Cleaner

1 Features

1

• High Performance LVPECL and LVCMOS PLL
Clock Synchronizer

• Two Reference Clock Inputs (Primary and
Secondary Clock) for Redundancy Support With
Manual or Automatic Selection

• Accepts LVCMOS Input Frequencies up to 200
MHz

• VCXO_IN Clock is Synchronized to One of the
Two Reference Clocks

• VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)

• Outputs Can Be a Combination of LVPECL and
LVCMOS (Up to Five Differential LVPECL Outputs
or up to 10 LVCMOS Outputs)

• Output Frequency is Selectable by ×1, /2, /3, /4,
/6, /8, /16 on Each Output Individually

• Efficient Jitter Cleaning From Low PLL Loop
Bandwidth

• Low Phase Noise PLL Core

• Programmable Phase Offset (PRI_REF and
SEC_REF to Outputs)

• Wide Charge Pump Current Range From
200 μA to 3 mA

• Dedicated Charge Pump Supply (VCC_CP) for
Wide Tuning Voltage Range VCOs

• Presets Charge Pump to VCC_CP/2 for Fast
Center-Frequency Setting of VC(X)O

• Analog and Digital PLL Lock Indication

• Provides VBB Bias Voltage Output for Single­Ended Input Signals (VCXO_IN)

• Frequency Hold-Over Mode Improves Fail-Safe
Operation

• Power-up Control Forces LVPECL Outputs to 3­State at VCC< 1.5 V

• SPI Controllable Device Setting

• 3.3-V Power Supply

• Packaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or
48-Pin QFN (RGZ)

• Industrial Temperature Range –40°C to 85°C

3 Description

The CDCM7005 is a high-performance, low phase
noise and low skew clock synchronizer that
synchronizes a VCXO (voltage controlled crystal
oscillator) or VCO (voltage controlled oscillator)
frequency to one of the two reference clocks. The
programmable pre-divider M and the feedback­dividers N and P give a high flexibility to the
frequency ratio of the reference clock to VC(X)O

VC(X)O_IN clock operates up to 2.2 GHz. Through
the selection of external VC(X)O and loop filter
components, the PLL loop bandwidth and damping
factor can be adjust to meet different system
requirements.

The CDCM7005 can lock to one of two reference
clock inputs (PRI_REF and SEC_REF), supports
frequency hold-over mode and fast-frequency-locking
for fail-safe and increased system redundancy. The
outputs of the CDCM7005 are user definable and can
be any combination of up to five LVPECL outputs or
up to 10 LVCMOS outputs. The built in
synchronization latches ensure that all outputs are
synchronized for low output skew.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

CDCM7005

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

VQFN (48) 7.00 mm × 7.00 mm
BGA (64) 8.00 mm × 8.00 mm

Typical Application Schematic

(1)

2 Applications

• Wireless Infrastructure

• SONET

• Data Communication

• Test Equipment

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

CDCM7005

SCAS793G –JUNE 2005–REVISED AUGUST 2017

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Description (continued)......................................... 4

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 7

7.1 Absolute Maximum Ratings...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 8

7.6 Timing Requirements.............................................. 10

7.7 Typical Characteristics............................................ 11

8 Parameter Measurement Information ................ 12

9 Detailed Description............................................ 15

9.1 Overview................................................................. 15

9.2 Functional Block Diagram....................................... 16

9.3 Feature Description................................................. 16

9.4 Device Functional Modes........................................ 24

9.5 Programming........................................................... 25

10 Application and Implementation........................ 34

10.1 Application Information.......................................... 34

10.2 Typical Application ............................................... 37

11 Power Supply Recommendations ..................... 40

12 Layout................................................................... 40

12.1 Layout Guidelines ................................................. 40

12.2 Layout Example .................................................... 41

13 Device and Documentation Support ................. 43

13.1 Receiving Notification of Documentation Updates 43

13.2 Community Resources.......................................... 43

13.3 Trademarks........................................................... 43

13.4 Electrostatic Discharge Caution............................ 43

13.5 Glossary................................................................ 43

14 Mechanical, Packaging, and Orderable

Information........................................................... 43

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (July 2015) to Revision G Page

• Removed duplicate row: PRI_SEC_CLK................................................................................................................................ 5

• Changed text from: "STATUS_REF or" to: "STATUS_REF or PRI_SEC_CLK".................................................................... 6

Changes from Revision E (February 2013) to Revision F Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision D (August 2009) to Revision E Page

• Changed PLL_LOCK pin description, replaced cycle-slip text............................................................................................... 5

• Changed the Frequency Hold-Over Mode section............................................................................................................... 22

• Changed text From: Cycle-Slip To: Frequency Offset in Figure 21 ..................................................................................... 23

• Changed Note 1 of table Word 3.......................................................................................................................................... 29

• Changed table Word 3, Cycle Slip (Bit 6) To: Frequency Offset.......................................................................................... 29

• Changed table Lock-Detect Window (Word 3) - Clip slip To: Frequency offset, and Note 2............................................... 32

Changes from Revision C (December 2007) to Revision D Page

• Added text to the CTRL_CLK pin - Unused or floating inputs must be tied to proper logic level. A 20kΩ or larger

pull−up resistor to VCC is recommended. ............................................................................................................................. 4

• Added text to the CTRL_DATA pin - Unused or floating inputs must be tied to proper logic level. A 20kΩ or larger

pull−up resistor to VCC is recommended. ............................................................................................................................. 4

• Added text to the CTRL_LE pin - Unused or floating inputs must be tied to proper logic level. A 20kΩ or larger

pull−up resistor to VCC is recommended. ............................................................................................................................. 4

• Added text to the PD pin - It is recommended to ramp up the PD with the same time as VCCand AVCCor later. The

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ramp up rate of the PD should not be faster than the ramp up rate of VCCand AVCC........................................................... 5

• Changed VCC pin text From: 3.3-V supply. There is no internal connection between VCCand AVCC. It is
recommended that AVCCuse its own supply filter. To: 3.3-V supply. VCCand AVCCshould always have the same

supply voltage. It is recommended that AVCCuse its own supply filter.................................................................................. 6

• Added text to the SPI CONTROL INTERFACE section - Unused or floating inputs must be tied to proper logic level.

A 20kΩ or larger pull−up resistor to VCC is recommended. ............................................................................................... 25

• Added text to the SPI CONTROL INTERFACE section - It is recommended to program Word 0, Word 1, Word 2

and Word 3 right after power up and PD becomes HIGH.................................................................................................... 25

• Changed From: RES To: GTME........................................................................................................................................... 29

• Changed From: RES To: PFDFC......................................................................................................................................... 29

Changes from Revision B (October 2005) to Revision C Page

• Changed N2, From: 1 To: 0.................................................................................................................................................. 30

• Changed N3, From: 1 To: 0.................................................................................................................................................. 30

• Changed N3, From: 1 To: 0.................................................................................................................................................. 30

• Changed N2, From: 1 To: 0.................................................................................................................................................. 30

Changes from Revision A (June 2005) to Revision B Page

SCAS793G –JUNE 2005–REVISED AUGUST 2017

• Added minor updates. ............................................................................................................................................................ 1

Changes from Original (June 2005) to Revision A Page

• Changed data sheet from Product Preview to Production data. ............................................................................................ 1

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3

P0022-01

CP_OUTREF_SELPRI_REF

GND GND GND GND GND GND GND

SEC_REF

GND AVCC AVCC AVCC AVCC AVCC

STATUS_

REFor

PRI_SEC_

CLK

GND GND GND GND GND VCC

STATUS_

VCXO

VCXO_IN

GND VCC VCC VCC VCC VCC VCC

Y0A GND GND GND GND GND VCC Y4B

Y0B VCC VCC VCC VCC VCCVCC Y4A

PD Y1A Y1B Y2A Y2B Y3A Y3B

RESET

or

HOLD

1 2 3 4 5 6 7 8

A

B

C

D

F

G

H

I_REF_CP

or

PLL_LOCK

VBB

VCC_CP

CTRL_LE CTRL_CLK

CTRL_

DATA

VCXO_IN

E

P0023-01

1 2 3 4 5 6 7 8 9 10 11 12

36 35 34 33 32 31 30 29 28 27 26 25

37

38

39

40

41

45

44

43

42

46

47

48

24

23

22

21

20

16

17

18

19

15

14

13

ThermalPad

mustbe

solderedtoGND

STATUS_REFor
PRI_SEC_CLK

STATUS_VCXOor
I_REF_CP

RESET
HOLD

or

PD

VCC

Y1A

Y1B

VCC

VCC

Y2A

Y2B

VCC

VCC

Y3A

Y3B

PRI_REF

REF_SEL

NC

VCC_CP

AVCC

CP_OUT

AVCC

CTRL_LE

CTRL_CLK

AVCC

CTRL_DATA

PLL_LOCK

GND

VCC

VCC

VCC

VCC

Y4B

Y4A

VCC

VCC

SEC_REF

AVCC

AVCC

VBB

VCC

VCXO_IN

VCC

VCC

Y0A

Y0B

VCC

VCXO_IN

CDCM7005

SCAS793G –JUNE 2005–REVISED AUGUST 2017

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5 Description (continued)

All device settings, like outputs signaling, divider value, and input selection are programmable by SPI (3-wire
serial peripheral interface). SPI allows individually control of the device settings.

The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C.

6 Pin Configuration and Functions

RGZ Package

48-Pin VQFN

Top View

PIN

NAME BGA QFN

C3, C4,

AVCC

C5, C6,

C7

CP_OUT A4 31 O Charge pump output

CTRL_CLK A6 28 I

CTRL_DATA A7 26 I

B2, B3,
B4, B5,
B6, B7,
B8, C2,
D2, D3,
D4, D5,
D6, E2,

F2, F3,
F4, F5,

F6

CTRL_LE A5 29 I

GND

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27, 30,
32, 38,

Thermal
pad and

pin 24

39

Pin Functions

I/O DESCRIPTION

Analog

Power

Ground Ground

3.3-V analog power supply. There is no internal connection between AVCCand
VCC. It is recommended that AVCCuse its own supply filter.

LVCMOS input, serial control clock input for SPI, with hysteresis. Unused or
floating inputs must be tied to proper logic level. A 20kΩ or larger pull−up resistor
to VCC is recommended.

LVCMOS input, serial control data input for SPI, with hysteresis. Unused or
floating inputs must be tied to proper logic level. A 20kΩ or larger pull−up resistor
to VCC is recommended.

LVCMOS input, control latch enable for serial programmable Interface (SPI), with
hysteresis. Unused or floating inputs must be tied to proper logic level. A 20kΩ or
larger pull−up resistor to VCC is recommended.

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ZVA Package

64-Pin BGA

Top View

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PIN

NAME BGA QFN

HOLD H8 14 I

I_REF_CP D8 22 O

PD H1 1 I

PLL_LOCK A8 25 I/O

PRI_REF A1 36 I

REF_SEL A2 35 I

SCAS793G –JUNE 2005–REVISED AUGUST 2017

Pin Functions (continued)

I/O DESCRIPTION

This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET
is the default function. This pin is low active and can be activated external or via
the corresponding bit in the SPI register. In case of RESET, the charge pump (CP)
is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider
settings are maintained in SPI registers). The LVPECL outputs are static low and
high respectively and the LVCMOS outputs are all low or high if inverted. RESET
is not edge triggered and should have a pulse duration of at least 5 ns.

In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is
released and with the next valid reference clock cycle the charge pump is
switched back in to normal operation (CP stays in 3-state as long as no reference
clock is valid). During HOLD, the P divider and all outputs Yx are at normal
operation. This mode allows an external control of the frequency hold-over mode.

The input has an internal 150-kΩ pullup resistor.
This LVCMOS output can be programmed (SPI) to provide either the

STATUS_VCXO information or serve as current path for the charge pump (CP).
STATUS_VCXO is the default setting.

In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO
input (frequencies above 2 MHz are interpreted as valid clock; active high).

In case of I_REF_CP, it provides the current path for the external reference
resistor (12 kΩ ±1%) to support an accurate charge pump current, optional. Do not
use any capacitor across this resistor to prevent noise coupling via this node. If
the internal 12 kΩ is selected (default setting), this pin can be left open.

LVCMOS input, asynchronous power down (PD) signal. This pin is low active and
can be activated external or by the corresponding bit in the SPI register (in case of
logic high, the SPI setting is valid). Switches the device into power-down mode.
Resets M- and N-Divider, 3-states charge pump, STATUS_REF, or
PRI_SEC_CLK pin, STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pin
and all Yx outputs. Sets the SPI register to default value; has internal 150-kΩ
pullup resistor. It is recommended to ramp up the PD with the same time as V
and AVCCor later. The ramp up rate of the PD should not be faster than the ramp
up rate of VCCand AVCC.

LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in
lock (see feature description). This output can be programmed to be digital lock
detect or analog lock detect (see feature description).

The PLL is locked (set high), if the rising edge either of PRI_REF or SEC_REF
clock and VCXO_IN clock at the phase frequency detector (PFD) are inside the
lock detect window for a predetermined number of successive clock cycles.

The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or
SEC_REF) clock and VCXO_IN clock at the PFD are outside the lock detect
window or if a certain frequency offset between reference frequency and feedback
frequency (VCXO) is detected.

Both, the lock detect window and the number of successive clock cycles are user
definable (via SPI).

LVCMOS input for the primary reference clock, with an internal 150-kΩ pullup
resistor and input hysteresis.

LVCMOS reference clock selection input. In the manual mode the REF_SEL
signal selects one of the two input clocks:
REF_SEL [1]: PRI_REF is selected;
REF_SEL [0]: SEC_REF is selected;
The input has an internal 150-kΩ pullup resistor.

CDCM7005

CC

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CDCM7005

SCAS793G –JUNE 2005–REVISED AUGUST 2017

Pin Functions (continued)

PIN

NAME BGA QFN

RESET H8 14 I

SEC_REF B1 37 I

STATUS_REF or
PRI_SEC_CLK

STATUS_VCXO D8 22 O

VBB C1 40 O

VCC

VCC_CP A3 33 Power
VCXO_IN E1 43 I VCXO LVPECL input

VCXO_IN D1 42 I Complementary VCXO LVPECL input
Y0A:Y0B

Y1A:Y1B
Y2A:Y2B
Y3A:Y3B
Y4A:Y4B

C8 23 O

D7, E3,
E4, E5,
E6, E7,
E8, F7,
G2, G3,
G4, G5,
G6, G7

F1, G1,
H2, H3,
H4, H5,
H6, H7,

G8, F8

2, 5, 6,

9, 10,
13, 15,
18, 19,
20, 21,
41, 44,

45; 48

46, 47,

3, 4,

7, 8,
11,12,
16, 17

I/O DESCRIPTION

This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET
is the default function. This pin is low active and can be activated external or via
the corresponding bit in the SPI register. In case of RESET, the charge pump (CP)
is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider
settings are maintained in SPI registers). The LVPECL outputs are static low and
high respectively and the LVCMOS outputs are all low or high if inverted. RESET
is not edge triggered and should have a pulse duration of at least 5 ns.

In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is
released and with the next valid reference clock cycle the charge pump is
switched back in to normal operation (CP stays in 3-state as long as no reference
clock is valid). During HOLD, the P divider and all outputs Yx are at normal
operation. This mode allows an external control of the frequency hold-over mode.

The input has an internal 150-kΩ pullup resistor.
LVCMOS input for the secondary reference clock, with an internal 150-kΩ pullup

resistor and input hysteresis.
This output can be programmed (SPI) to provide either the STATUS_REF or

PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is
valid. STATUS_REF is the default setting.

In case of STATUS_REF, the LVCMOS output provides the Status of the
Reference Clock. If a reference clock with a frequency above 2 MHz is provided to
PRI_REF or SEC_REF STATUS_REF will be set high.

In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary
clock [high] or the secondary clock [low] is selected.

This LVCMOS output can be programmed (SPI) to provide either the
STATUS_VCXO information or serve as current path for the charge pump (CP).
STATUS_VCXO is the default setting.

In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO
input (frequencies above 2 MHz are interpreted as valid clock; active high).

In case of I_REF_CP, it provides the current path for the external reference
resistor (12 kΩ ±1%) to support an accurate charge pump current, optional. Do not
use any capacitor across this resistor to prevent noise coupling via this node. If
the internal 12 kΩ is selected (default setting), this pin can be left open.

Bias voltage output to be used to bias unused complementary input VCXO_IN for
single ended signals. The output of VBB is VCC– 1.3 V. The output current is
limited to about 1.5 mA.

Power

O

3.3-V supply. VCCand AVCCshould always have the same supply voltage. It is
recommended that AVCCuse its own supply filter.

This is the charge pump power supply pin used to have the same supply as the
external VCO. It can be set from 2.3 V to 3.6 V.

The outputs of the CDCM7005 are user definable and can be any combination of
up to five LVPECL outputs or up to 10 LVCMOS outputs. The outputs are
selectable via SPI (Word 1, Bit 2-6). The power-up setting is all outputs are
LVPECL.

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SCAS793G –JUNE 2005–REVISED AUGUST 2017

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

VCC, A
V

CC_CP

V

I

V

O

I

OUT

I

IN

T

J

T

stg

,

Supply voltage

VCC

Input voltage
Output voltage
Output current for LVPECL/LVCMOS outputs

(0 < VO< VCC)
Input current (VI< 0, VI> VCC) ±20 mA
Maximum junction temperature 125 °C
Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All supply voltages have to be supplied at the same time.
(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(2)

(3)

(3)

7.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001

V

(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

(2)

C101

(1)

MIN MAX UNIT

–0.5 4.6 V
–0.5 VCC+ 0.5 V

–0.5 VCC+ 0.5 V

±50 mA

VALUE UNIT

(1)

±2500
±1500

V

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT

VCC, AV

CC

V

CC_CP

V

IL

V

IH

I

OH

I

OL

V

I

V

INPP

V

IC

T

A

Supply voltage

Low-level input voltage LVCMOS, see
High-level input voltage LVCMOS, see

(1)

(1)

High-level output current LVCMOS (includes all status pins) –8 mA
Low-level output current LVCMOS (includes all status pins) 8 mA
Input voltage range LVCMOS 0 3.6 V
Input amplitude LVPECL (V

VCXO_IN

– V

VCXO_IN

(2)

)
Common-mode input voltage LVPECL 1 VCC–0.3 V
Operating free-air temperature –40 85 °C

(1) VILand VIHare required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an ac-coupling to

VCC/2 is provided.

(2) V

minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum V

INPP

of 150 mV.

3 3.3 3.6

2.3 V

0.3 V

0.7 V

CC

0.5 1.3 V

CC
CC

INPP

V

V
V

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7.4 Thermal Information

CDCM7005

RGZ

(VQFN)

ZVA

(BGA)

48 PINS 64 PINS

UNIT

°C/W

°C/W

THERMAL METRIC

(1)

RGZ

AIRFLOW

(lfm)

ZVA

AIRFLOW

(m/s)

0 0 29.9 53.9

R

θJA

Junction-to-ambient thermal resistance

150 1 24.7 49.8
250 2 23.2 48.5
500 – 21.5 –

R

θJC(top)

R

θJB

Junction-to-case (top) thermal resistance 22.4 28.3 °C/W
Junction-to-board thermal resistance 14.2 38.6 °C/W

0 0 0.2 0.7

ψ

JT

Junction-to-top characterization parameter

150 1 0.2 0.7
250 2 0.2 0.8
500 – 0.3 –

ψ

JB

R

θJC(bot)

Junction-to-board characterization parameter – – °C/W
Junction-to-case (bottom) thermal resistance °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

OVERALL

f

= 245.76 MHz,

VCXO

f

= 30.72 MHz,

I

CC_LVPECL

I

CC_LVCMOS

I

CCPD

I

OZ

V

I_REF_CP

V

BB

C

O

C

I

LVCMOS

f

clk

V

IK

I

I

Supply current (ICCover frequency see

Figure 1 through Figure 4)

Power-down current

High-impedance state output current for Yx
outputs

Voltage on I_REF_CP (external current path
for accurate charge pump current)

Output reference voltage VCC= 3 V – 3.6 V; IBB= –0.2 mA VCC–1.3 V
Output capacitance for Yx VCC= 3.3 V, VO= 0 V or V
Input capacitance at PRI_REF and

SEC_REF
Input capacitance at CTRL_LE,

CTRL_CLOCK, CTRL_DATA

Output frequency, see

Figure 7

LVCMOS input clamp voltage VCC= 3 V, II= –18 mA –1.2 V
LVCMOS input current for CTRL_LE,

CTRL_CLK, CTRL_DATA

(2),(3)

, Figure 6, and

REF_IN

PFD = 240 kHz, ICP= 2 mA, all outputs are LVPECL
and Div-by-8 (load, see Figure 13)

f

= 245.76 MHz,

VCXO

f

= 30.72 MHz,

REF_IN

PFD = 240 kHz, ICP= 2 mA, All outputs are
LVCMOS and Div-by-8 (load, 10 pF)

fIN= 0 MHz, VCC= 3.6 V, AVCC= 3.6 V,
V

= 3.6 V,

CC_CP

VI= 0 V or V
VO= 0 V or VCC– 0.8 V ±40 µA
VO= 0 V or V

12 kΩ to GND at pin D8 (BGA), pin 22 (QFN) 1.21 V

VI= 0 V or VCC, VI= 0 V or V

VI= 0 V or V

Load = 5 pF to GND, 1 kΩ to VCC, 1 kΩ to GND 250 MHz

VI= 0 V or VCC, VCC= 3.6 V ±5 µA

CC

CC

CC

CC

CC

(1)

MAX UNIT

210 260 mA

120 150 mA

100 300 µA

±100 µA

2 pF

2.7

2

pF

(1) All typical values are at VCC= 3.3 V, temperature = 25°C.
(2) f

can be up to 400 MHz in the typical operating mode (25°C / 3.3-V VCC). The total power consumption limit of 700 mW for the BGA

clk

package can be violated if several LVCMOS outputs switch at high frequency (see Figure 3 and Figure 4).

(3) Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output

signal swing may no longer meet the output specification.

8

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Electrical Characteristics (continued)

CDCM7005

SCAS793G –JUNE 2005–REVISED AUGUST 2017

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

LVCMOS input current for PD, RESET,

I

IH

HOLD, REF_SEL, PRI_REF, SEC_REF,

(4)

(see

)

VI= VCC, VCC= 3.6 V 5 µA

LVCMOS input current for PD, RESET,

I

IL

V

OH

HOLD, REF_SEL, PRI_REF, SEC_REF,

(4)

(see

)

High-level output voltage for LVCMOS
outputs

VI= 0 V, VCC= 3.6 V –15 –35 µA

VCC= min to max,
IOH= –100 μA

VCC–0.1

VCC= 3 V, IOH= –6 mA 2.4
VCC= 3 V, IOH= –12 mA 2
VCC= min to max,

V

OL

Low-level output voltage for LVCMOS
outputs

IOL= 100 μA
VCC= 3 V, IOL= 6 mA 0.5
VCC= 3 V, IOL= 12 mA 0.8

I

OH

I

OL

tpho Phase offset (REF_IN to Y output)
t

sk(p)

t

pd(LH)

t

pd(HL)

t

sk(o)

High-level output current VCC= 3.3 V, VO= 1.65 V –30 mA
Low-level output current VCC= 3.3 V, VO= 1.65 V 33 mA

(5)

VREF_IN = VCC/2, Y = VCC/2,
see Figure 11, Load = 10 pF

LVCMOS pulse skew, see Figure 10 Crosspoint to VCC/2 load, see Figure 12 150 ps
Propagation delay from VCXO_IN to Yx,

see Figure 10
LVCMOS single-ended output skew, see

and Figure 10

Crosspoint to VCC/2,
Load = 10 pF, see Figure 12 (PLL bypass mode)

(6)

All outputs have the same divider ratio 55

2 2.5 3 ns

Outputs have different divider ratios 70

Duty cycle LVCMOS VCC/2 to VCC/2 49% 51%
t

slew-rate

Output rise/fall slew rate

20% to 80% of swing (load
see Figure 12)

2.4 3.5 V/ns

LVPECL

f

clk

I

I

V

OH

V

OL

Output frequency, see
LVPECL input current VI= 0 V or V

LVPECL high-level output voltage Load, See Figure 13 VCC–1.18

LVPECL low-level output voltage Load, See Figure 13 VCC–2

(3)

and Figure 5 Load, see Figure 13 0 1500 MHz

CC

|VOD| Differential output voltage See Figure 9 and load, see Figure 13 500 mV
t

pho

t

pd(LH)

t

pd(HL)

t

sk(p)

Phase offset (REF_IN to Y output)
Propagation delay time, VCXO_IN to Yx,

see Figure 10

LVPECL pulse skew, see Figure 10

(6)

VREF_IN = VCC/2 to cross point of Y, see Figure 11 –200 100 ps
Cross point-to-cross point, load

see Figure 13

340 490 640 ps

Cross point-to-cross point, load
see Figure 13

Load see Figure 13, all outputs have the same

t

sk(o)

LVPECL output skew

(6)

divider ratio
Load see Figure 13, outputs have

different divider ratios
tr/ t
C

f

I

Rise and fall time 20% to 80% of V

, see Figure 9 120 170 220 ps

OUTPP

Input capacitance at VCXO_IN, VCXO_IN 1.5 pF

LVCMOS-TO-LVPECL

t

sk(P_C)

Output skew between LVCMOS and
LVPECL outputs, see

(7)

and Figure 10

Cross point to VCC/2; load,

see Figure 12 and Figure 13

1.7 2 2.4 ns

PLL ANALOG LOCK

I

OH

I

OL

High-level output current VCC= 3.6 V, VO= 1.8 V –110 µA
Low-level output current VCC= 3.6 V, VO= 1.8 V 110 µA

(4) These inputs have an internal 150-kΩ pullup resistor.
(5) This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay M

and VCXO delay N).
(6) The t
(7) The phase of LVCMOS is lagging in reference to the phase of LVPECL.

specification is only valid for equal loading of all outputs.

sk(o)

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(1)

MAX UNIT

0.1

1.8 ns

±20 µA

VCC–0.8

1

VCC–1.5

5

10 ps

20

50

V

V

ps

V

V

ps

9

CDCM7005

SCAS793G –JUNE 2005–REVISED AUGUST 2017

Electrical Characteristics (continued)

www.ti.com

over recommended operating free-air temperature range (unless otherwise noted)

10%

5%

(1)

MAX UNIT

PARAMETER TEST CONDITIONS MIN TYP

I

OZH LOCK

I

OZL LOCK

V

IT+

V

IT–

PHASE DETECTOR

f

CPmax

CHARGE PUMP

I

CP

I

CP3St

I

CPA

I

CPM

I

VCPM

High-impedance state output current for PLL
LOCK output

High-impedance state output current for PLL
LOCK output

Positive input threshold voltage VCC= min to max VCC×0.55 V
Negative input threshold voltage VCC= min to max VCC×0.35 V

Maximum charge pump frequency Default PFD pulse width delay 100 MHz

Charge pump sink/source current range
Charge pump 3-state current 0.5 V < VCP< V

ICP absolute accuracy

Sink/source current matching 0.5 V < VCP< V
ICP vs VCP matching 0.5 V < VCP< V

(8)

(8)

(8) Lock output has an 80-kΩ pulldown resistor.
(9) Defined by SPI settings.

VO= 3.6 V (PD is set low) 45 65 µA

VO= 0 V (PD is set low) ±5 µA

(9)

VCP= 0.5 V

VCP= 0.5 V
default settings

VCP= 0.5 V
(1%) at I_REF_CP, SPI default settings

CC_CP

– 0.5 V 10 nA

CC_CP

, internal reference resistor, SPI

CC_CP

, external reference resistor 12 kΩ

CC_CP

– 0.5 V, SPI default settings 2.5%

CC_CP

– 0.5 V 5%

CC_CP

±0.2 ±3 mA

7.6 Timing Requirements

over recommended ranges of supply voltage, load and operating free air temperature

MIN NOM MAX UNIT

PRI_REF/SEC_REF_IN REQUIREMENTS

f

REF_IN

tr/ t

f

LVCMOS primary or secondary reference clock frequency
Rise and fall time of PRI_REF or SEC_REF signals from 20% to 80% of V

dutyREF Duty cycle of PRI_REF or SEC_REF at VCC/2 40% 60%

VCXO_IN, VCXO_IN REQUIREMENTS

f

VCXO_IN

tr/ t

f

VCXO clock frequency
Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz

(3)

dutyVCXO Duty cycle of VCXO clock 40% 60%

SPI/CONTROL REQUIREMENTS (see Figure 23)

f

CTRL_CLK

t

su1

t

h2

t

3

t

4

t

su5

t

su6

t

7

tr/ t

f

CTRL_CLK frequency 20 MHz
CTRL_DATA to CTRL_CLK setup time 10 ns
CTRL_DATA to CTRL_CLK hold time 10 ns
CTRL_CLK high duration 25 ns
CTRL_CLK low duration 25 ns
CTRL_LE to CTRL_CLK setup time 10 ns
CTRL_CLK to CTRL_LE setup time 10 ns
CTRL_LE pulse width 20 ns
Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of V

PD, RESET, HOLD, REF_SEL REQUIREMENTS

tr/ t

f

Rise and fall time of the PD, RESET, HOLD, REF_SEL signal from 20% to 80% of V

(1) At Reference Clock less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the

STATUS_REF signal to low. In this case, the status of the STATUS_REF is no longer relevant.
(2) f
(3) If the Feedback Clock (derives from VCXO input) is less than 2 MHz, the device stays in normal operation mode but the frequency

can be up to 250 MHz in typical operating mode (25°C / 3.3-V VCC).

REF_IN

detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This

effects the HOLD-over function as well, as the PLL_LOCK signal is no longer valid!
(4) Use a square wave for lower frequencies (< 80 MHz).

(1) (2)

0 200 MHz

CC

4 ns

0 2200 MHz

(4)

CC

CC

3 ns

4 ns

4 ns

10

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f

Out

− Output Frequency − MHz

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

50 250 450 650 850 1050 1250 1450 1650 1850

VCC= 3.3 V
TA= 25°C
Termination = 50 to VCC− 2 V

V

OD

− Differential Output V

oltage − V

G005

f − Frequency − MHz

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

50 100 150 200 250 300 350 400 450 500

LVCMOS Output Swing − V

G006

TA= 25°C
Load = 5 pF (See Figure 12)

VCC= 3 V

VCC= 3.6 V

VCC= 3.3 V

0

50

100

150

200

250

40 60 80 100 120 140 160 180 200 220 240 260 280 300

Output Frequency − MHz

Icc − Supply Current − mA

0

100

200

300

400

500

600

700

800

900

PDEV − Device Power

Consumption − mW

for 1 output

for 1 output pair

no output active

one output active div−by−1

one output pair active div−by−1

all outputs active div−by−1

all outputs active div−by−3

for div−by−3/6

VCC= 3.3 V
TA= 25°C
Load = 10 pF

0

50

100

150

200

50 100 150 200 250 300

Output Frequency− MHz

Icc − Supply Current− mA

0

100

200

300

400

500

600

700

800

PDEV − Power Device Consumption

− mW

Vcc = 3.3V

load = 5 pF

for 1 output

for 1 output pair

no output active

one output active div−by−1

one output pair active div−by−1

all outputs active div−by−1

all outputs active div−by−3

for div−by−3/6

TA= 25C

VCXO_IN Input Frequency − MHz

50

70

90

110

130

150

170

190

210

230

250

50 250 450 650 850 1050 1250 1450 1650 1850 2050

VCC= 3.3 V
TA= 25°C

I

CC

− Supply Current − mA

All Output Pairs Active (4 div-by-8 / 1 div-by-3)

All Output Pairs Active (div-by-1)

All Output Pairs Active (div-by-8)

D for div-by-2/4/8/16

One Output Pair Active (div-by-8)

D For 1 Output Pair

D For div-by-3/6

G001

No Output Active

50

150

250

350

450

550

650

750

50 250 450 650 850 1050 1250 1450 1650 1850 2050

VCXO_IN Input Frequency − MHz

VCC= 3.3 V
TA= 25°C

PDEV − Device Power Consumption − mW

All Output Pairs Active (4 div-by-8 / 1 div-by-3)

All Output Pairs Active (div-by-1)

All Output Pairs Active (div-by-8)

One Output Pair Active (div-by-8)

G002

No Output Active

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7.7 Typical Characteristics

If div-by-2/4/8/16 is activated for one or more outputs, 'Δ for div-by­2/4/8/16' has to be added to ICCof div-by-1. If div-by-3 or div-by-6 is
activated, 'Δ for div-by-2/4/8/16' and 'Δ for div-by3/6' has to be added
to ICCof div-by-1.

Figure 1. LVPECL Supply Current vs Number of Active

Outputs

CDCM7005

SCAS793G –JUNE 2005–REVISED AUGUST 2017

Figure 2. LVPECL Device Power Consumption vs Number of

Active Outputs

It is not recommended to exceed power dissipation of 700 mW for the
BGA package at TA85°C.

Figure 3. LVCMOS Supply Current and Device Power

Consumption vs Number of Active Outputs (Load = 5 pF)

Figure 5. Differential LVPECL Output Voltage vs Output

Frequency

It is not recommended to exceed power dissipation of 700 mW for the
BGA package at TA85°C.

Consumption vs Number of Active Outputs (Load = 10 pF)

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Figure 4. LVCMOS Supply Current and Device Power

Figure 6. LVCMOS Output Swing vs Frequency

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11

Yx

Yx

V

OH

V

OL

80%
20%

0V

t

r

t

f

VOD

V

OUTpp

T0058-01

f − Frequency − MHz

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

50 100 150 200 250 300 350 400 450 500

LVCMOS Output Swing − V

G007

VCC= 3 V

VCC= 3.6 V

VCC= 3.3 V

TA= 25°C
Load = 10 pF (See Figure 12)

I − Load − mA

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

−5 0 5 10 15 20 25 30 35

VCC= 3.3 V
TA= 25°C

V

BB

− Output Reference V

oltage − V

G008

CDCM7005

SCAS793G –JUNE 2005–REVISED AUGUST 2017

Typical Characteristics (continued)

Figure 7. LVCMOS Output Swing vs Frequency Figure 8. Output Reference Voltage (VBB) vs Load

8 Parameter Measurement Information

www.ti.com

Figure 9. LVPECL Differential Output Voltage and Rise/Fall Time

12

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YxA

YxA

YxB

YxA

YxB

YxB

VCXO_IN

/VCXO_IN

YxA

LVPECL

LVCMOS

YxA/B

VCXO_IN

/VCXO_IN

LVCMOS

LVCMOS

YxA/B

LVPECL

LVCM OS

tpd(LH) / tpd(HL); t

sk(p)

= | tpd(HL) − tpd(LH) |

LVPECL

LVPECL

t

sk(o)L VPECL

tsk

p_c

tpd(LH); t

sk(p)

= | tpd(HL) − tpd(LH) |

t

sk(o)L VCMOS

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Parameter Measurement Information (continued)

CDCM7005

SCAS793G –JUNE 2005–REVISED AUGUST 2017

A. Output skew, t

B. Pluse skew, t

is calculated as the greater of:
The difference between the fastest and the slowest tpd(LH)n (n = 0...4)
The difference between the fastest and the slowest tpd(HL)n (n = 0...4)

the low-to-high (tpd(LH)) propagation delays when a single switching input causes one or more outputs to switch,
t

= |tpd(HL) – tpd(LH) |. Pulse skew is sometimes refered to as pulse width distortion or duty cycle skew.

sk(p)

sk(o),

, is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL)) and

sk(p)

Figure 10. Output Skew

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13

S0078-01

V

CC

V

EE

VT =V

CC

– 2V

CDCM7005

Driver

LVPECL

Receiver

Z =50OW

50W50W

Z =50OW

Yx

Yx

S0079-01

CDCM7005

LVCMOS

1kW

1kW

10pF

Y3

T0060-01

V

IH

V

IL

V

OH

V

OL

V

OH

V

OL

REF_IN

YxB

YxA

LVCMOS

LVPECL

t

pho LVPECL

50%V

CC

t

pho LVCMOS

CDCM7005

SCAS793G –JUNE 2005–REVISED AUGUST 2017

Parameter Measurement Information (continued)

www.ti.com

Figure 11. Phase Offset

14

Figure 12. LVCMOS Output Loading During Device Test

Figure 13. LVPECL Output Loading During Device Test

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CDCM7005

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SCAS793G –JUNE 2005–REVISED AUGUST 2017

9 Detailed Description

9.1 Overview

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a
VCXO or VCO frequency to one of the two reference clocks. VC(X)O_IN clock operates up to 2.2 GHz. Through
the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be
adjust to meet different system requirements.

The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency
hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the
CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS
outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, …), so that each pair has the same
frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure
that all outputs are synchronized for low output skew.

CDCM7005 is programmable through SPI (3-wire serial peripheral interface). SPI allows individually control of
the device settings.

The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C.

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15

B0057-01

PECL

to

LVCMOS

Progr.Delay

N

PECL
INPUT

CTRL_LE

CTRL_DATA

CTRL_CLK

VCXO_IN

VCXO_IN

CP_OUT

PLL_LOCK

STATUS_VCXO/

STATUS_REF/
PRI_SEC_CLK

I_REF_CP

RESET or

HOLD

PD

BiasGenerator

V 1.3VCC–

VBB

VCC_CPVCC AVCC

GND

PRI_REF

SEC_REF

REF_SEL

RE F_MU X

LVCMOS

FB_MUX

LV

CMOS

Y0B

Y0A

LV

CMOS

LV

PECL

LV

CMOS

Y1B

Y1A

LV

CMOS

LV

PECL

LV

CMOS

Y2B

Y2A

LV

CMOS

LV

PECL

LV

CMOS

Y3B

Y3A

LV

CMOS

LV

PECL

LV

CMOS

Y4B

Y4A

LV

CMOS

LV

PECL

SPILOGIC

Manual&

Automatic

CLKSelect

Current

Reference

Reference

Clock

SelectedREFSignal

Progr.Divider

N 2

12

P Divider

÷3

÷4

÷6

/8

÷8

÷16

÷1

÷2

÷4

÷8

90

o

90

o

LOCK

Charge

Pump

PFD

Y0_MUX

HOLD

P16-Div

freq.Detect

>2Mhz

freq.Detect

>2Mhz

Progr.Delay

M

Progr.Divider

M2

10

Feedback

Clock

Y1_MUXY2_MUXY3_MUX

Y4_MUX

CDCM7005

SCAS793G –JUNE 2005–REVISED AUGUST 2017

9.2 Functional Block Diagram

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9.3 Feature Description

9.3.1 Automatic/Manual Reference Clock Switching

The CDCM7005 supports two reference clock inputs, the primary clock input, PRI_REF, and the secondary clock
input, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selected by the
dedicated SPI register bit (Word 0, Bit 30).

In the manual mode, the external REF_SEL signal selects one of the two input clocks:

REF_SEL [1] -> primary clock is selected
REF_SEL [0] -> secondary clock is selected

In the automatic mode, the primary clock is selected by default even if both clocks are available. In case the
primary clock is not available or fails, then the input switches to the secondary clock as long until the primary
clock is back. Figure 14 shows the automatic clock selection.

16

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