Texas Instruments CDCF 5801 INSTALLATION INSTRUCTIONS

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24 23 22 21 20 19 18 17 16 15 14 13
VDDREF
REFCLK
VDDP
GNDP
GND
LEADLAG
DLYCTRL
GNDPA
VDDPA
VDDPD
STOPB
PWRDNB
P0 P1 VDDO GNDO CLKOUT NC CLKOUTB GNDO VDDO MULT0 MULT1 P2
DBQ PACKAGE
(TOP VIEW)
CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT

FEATURES APPLICATIONS

Low-Jitter Clock Multiplier: × 1, × 2, × 4, × 8
Programmable Bidirectional Delay Steps of
1.3 mUI
Output Frequency Range of 25 MHz to
280 MHz
Input Frequency Range of 12.5 MHz to
240 MHz
Low Jitter Generation
Single-Ended REFCLK Input With Adjustable
Trigger Level (Works With LVTTL, HSTL, and LVPECL)
Differential/Single-Ended Output
Output Can Drive LVPECL, LVDS, and LVTTL
Three Power Operating Modes to Minimize
Power
Low Power Consumption (< 190 mW at
280 MHz/3.3 V)
Packaged in a Shrink Small-Outline Package
(DBQ)
No External Components Required for PLL
Spread Spectrum Clock Tracking Ability to
Reduce EMI (SSC)
CDCF5801
SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004
Video Graphics
Gaming Products
Datacom
Telecom
Noise Cancellation Created by FPGAs

DESCRIPTION

The CDCF5801 provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin, while strapping the LEADLAG pin to dc high or low. Further possible applications are:
Aligning the rising edge of the output clock signal to the input clock rising edge

Avoiding PLL instability in applications that require very long PLL feedback lines

Isolation of jitter and digital switching noise
Limitation of jitter in systems with good ppm frequency stability
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003–2004, Texas Instruments Incorporated
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CDCF5801
SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004
The CDCF5801 provides clock multiplication and division from a reference clock (REFCLK) signal. The device is optimized to have extremely low jitter impact from input to output. The predivider pins MULT[0:1] and post-divider pins P[0:2] provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 25 MHz to 280 MHz with clock input references (REFCLK) ranging from 12.5 MHz to 240 MHz. See Table 1 for detailed frequency support. The selection of pins MULT[0:1] and P[1:2] determines the multiplication value of 1, 2, 4, or 8. The CDCF5801 offers several power-down/ high-impedance modes, selectable by pins P0, STOPB and PWRDN. Another unique capability of the CDCF5801 is the high sensitivity and wide common-mode range of the clock-input pin REFCLK by varying the voltage on the VDDREF pin. The clock signal outputs CLKOUT and CLKOUTB can be used independently to generate single-ended clock signals. The CLKOUT/CLKOUTB outputs can also be combined to generate a differential output signal suitable for LVDS, LVPECL, or HSTL/SSTL signaling. The CDCF5801 is characterized for operation over free-air temperatures of
-40 ° C to 85 ° C.
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PWRDNB
>CLK
01 div2
00 div4
11 div8
10 div16
2
PLL
VDDREF/2
12.5-240 MHz
Control
P0
VDDP
GNDP
MULT[0:1]
Delay
Phase Aligner
DLY+ DLY-
VDDPD/2
DLYCTRL
0-240 MHz
LEADLAG
0-280 MHz
CLKOUTB
CLKOUT
25-280 MHz
div2
div4
div8
11
10
01
2
P[1:2]
GNDO
STOPB
VDDO
GNDPA
VDDPA
CDCF5801
SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004
FUNCTIONAL BLOCK DIAGRAM
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CDCF5801
SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
CLKOUT 2018 O Output CLK signal (low-noise CMOS) Complementary output CLK signal (low-noise CMOS) CLKOUTB
DLYCTRL 7 I Every rising edge on this pin delays/advances the CLKOUT/CLKOUTB signal by 1/768
GND 5 GND for VDDREF and VDDPD GNDO 17, 21 GND for the output pins (CLKOUT, CLKOUTB) GNDP 4 GND for the PLL GNDPA 8 GND for phase aligner, digital logic, and inputs P[0:2], MULT[0:1], STOPB, PWRDNB LEADLAG 6 I Controls whether the output CLK is delayed or advanced relative to REFCLK. See Table 3 . MULT0 15 I PLL multiplication factor select. See Table 1 .
MULT1
NC 19 Not connected; leave pin floating or tied to GND. P0 24 I Mode control pins (see Table 1 )
P1 23 I Post divider control (see Table 1 )
P2 13 P[1:2] = 01: div8 PWRDNB 12 I Active-low power-down state. CLKOUT/CLKOUTB goes low, See Table 2 ).
REFCLK 2 I Reference input clock STOPB 11 I Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as
VDDO 16, 22 VDD for the output pin (CLKOUT, CLKOUTB) and power down circuit VDDP 3 VDD for PLL and input buffer VDDPA 9 VDD for phase aligner, digital logic, and inputs P[0:2], MULT[0:1], and STOPB VDDPD 10 Reference voltage for inputs LEADLAG and DLYCTRL VDDREF 1 Reference voltage for REFCLK
14 MULT[0:1] = 10: × 16
I/O DESCRIPTION
CLKOUT/CLKOUTB period (1.3 mUI). (E.g., for a 90-degree delay or advancement one needs to provide 192 rising edges). See Table 3 .
MULT[0:1] = 11: × 8 MULT[0:1] = 00: × 4 MULT[0:1] = 01: × 2
0 - Normal operation 1 - High-Z outputs and other special settings
P[1:2] = 11: div2 P[1:2] = 10: div4
0 - IC in power down 1 - Normal operation
listed in Table 2 . 0 - Outputs disabled 1 - Normal operation
th
of the
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CDCF5801
SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004
Table 1. Input-to-Output Settings
INPUT-TO-OUTPUT MULTIPLI-
CATION-RATIO
8 12.5 35 100 280 1 0 1 1
4
2 25 78 50 156 1 1 0 1 0 Normal operation
1 50 156 50 156 0 0 1 0
INPUT FRE- OUTPUT FRE-
QUENCY (MHz) QUENCY (MHz)
FROM TO FROM TO MULT0 MULT1 P0 P1 P2
12.5 39 50 156 1 0 1 0 25 70 100 280 1 1 1 1
12.5 39 25 78 1 0 0 1
50 140 100 280 0 0 1 1 25 78 25 78 1 1 0 1
100 240 100 240 0 1 1 1
CLKOUT high-impedance
CLOUOTB high-impedance
CLKOUT = high
CLKOUTB = high
CLKOUT = P2
CLKOUTB = P2
(1) There is some overlapping of the input frequency ranges for multiplication ratios of 1, 2, and 4. For example, an input frequency of 30
MHz for a multiplication ratio of four falls within both the 12.5 to 39-MHz range and the 25 to 70-MHz range. For best device operation in a case such as this, always select the input frequency range nearer to the top of the table.
PREDIVIDER POST DIVIDER
X X 0 0
X X 1 0 1 Special mode of operation
X X 1 X
NOTE
(1)

PLL DIVIDER/MULITPLIER SELECTION

Table 2. Power Down Modes
STATE PWRDNB STOPB CLKOUT and CLKOUTB
Power down 0 X GNDO
Clock stop 1 0 VO, STOP
Normal 1 1 See Table 1
Table 3. Programmable Delay and Phase Alignment
DLYCTR NOTE LEADLAG CLKOUT and CLKOUTB
Each rising step size: 1/768 of the CLKOUT period (1.3 mUI) at P[1:2] = 11
edge+ 1/1536 of the CLKOUT period (0.65 mUI) at P[1:2] = 10
Each rising step size: 1/768 of the CLKOUT period (1.3 mUI) at P[1:2] = 11
edge+ 1/1536 of the CLKOUT period (0.65 mUI) at P[1:2] = 10
For every 32 edges, there are one or two edges for which the phase aligner does not update the phase. Therefore, CLKOUT phase is not updated for every 32
nd
The frequency of the DLYCTRL pin should always be equal to or less than the frequency of the LEADLAG pin.
HI
edge.
LO
Advanced by one step:
1/3072 of the CLKOUT period (0.325 mUI) at P[1:2] = 01 Delayed by one step:
1/3072 of the CLKOUT period (0.325 mUI) at P[1:2] = 01
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VDDPD
2
0.2
VDDPD
2
0.2
VDDREF
2
0.2
VDDREF
2
0.2
CDCF5801
SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature (unless otherwise noted)
(2)
V
DDx
Supply voltage range -0.5 V to 4 V Voltage range at any output terminal -0.5 V to V Voltage range at any input terminal -0.5 V to V
T
stg
Storage temperature range -65 ° C to 150 ° C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C
(1) Stresses beyond those listed under, , absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under, , recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminals.
POWER DISSIPATION RATING TABLE
PACK-
AGE
DBQ 830 mW 8.3 mW/ ° C 332 mW
(1) This is the inverse of the junction-to-ambient thermal resistance
TA≤ 25 ° C POWER DERATING FAC- TA= 85 ° C
RATING TOR
when board-mounted and with no air flow.

RECOMMENDED OPERATING CONDITIONS

VDDP, VDDPA, VDDO Supply voltage 3 3.3 3.6 V V
IH (CMOS)
V
IL (CMOS)
High-level input voltage 0.7 VDD V Low-level input voltage 0.3 VDD V
(1)
+ 0.5 V
DD
+ 0.5 V
DD
(1)
ABOVE T
= 25 ° C
POWER RATING
A
MIN NOM MAX UNIT
VIL(DLYCTRL, LEADLAG) Input signal low voltage V
VIH(DLYCTRL, LEADLAG) Input signal high voltage V
(VDDPD) Input reference voltage for DLYCNTRL and LEADLAG 1.2 VDD V I
OH
I
OL
(VDDREF) (see Application section)
High-level output current -16 mA Low-level output current 16 mA
Input reference voltage for REFCLK 1.2 VDD V
VIL(see Application section) REFCLK input low voltage V
VIH(see Application section) REFCLK input high voltage V
T
A
Operating free-air temperature -40 85 ° C

TIMING REQUIREMENTS

PARAMETER MIN MAX UNIT
F
SR Input slew rate 1 4 V/ns
Input frequency of modulation, (if driven by SSC CLKIN) 33 kHz
mod
Modulation index, nonlinear maximum 0.5% 0.6%
Input duty cycle on REFCLK 40% 60% Input frequency on REFCLK 12.5 240 MHz Output frequency on CLKOUT and CLKOUTB 25 280 MHz Allowable frequency on DLYCTRL 240 MHz
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