Texas Instruments CDCEL949PWRG4, CDCE949 Datasheet

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Y4

Y5

Crystal or

Clock Input

V

DD

GND

Vctr

V

DDOUT

S2/S1/S0or

SDA/SCL

Y1

VCXO

XO

LVCMOS

3

Y2

Y3

LV

CMOS

LV

CMOS

PLL1

withSSC

LV

CMOS

LV

CMOS

LV

CMOS

PLL2

withSSC

Y6

Y7

LV

CMOS

LV

CMOS

PLL3

withSSC

Y8

Y9

LV

CMOS

LV

CMOS

PLL4

withSSC

Xin/Clk 1 24 Xout

S0 2 23 S1/SDA
Vdd 3 22 S2/SCL
Vctr 4 21 Y1

GND 5 20 GND

Vddout 6 19 Y2

Y4 7 18 Y3

Y5 8 17 Vddout

GND 9 16 Y6

Vddout 10 15 Y7

Y8 11 14 GND

Y9 12 13 Vdd

Divider

and
Output
Control

EEPROM

Programming

and

ControlRegister

Programmable 4-PLL VCXO Clock Synthesizer with 1.8V and 3.3V I/Os

CDCE949

CDCEL949

SCAS844 – JUNE 2007

FEATURES

• Member of Programmable Clock Generator

Family
– CDCE949/CDCEL949: 4 PLLs, 9 Outputs
– CDCE937/CDCEL937: 3 PLLs, 7 Outputs
– CDCE925/CDCEL925: 2 PLLs, 5 Outputs
– CDCE913/CDCEL913: 1 PLLs, 3 Outputs

• In-System Programmability and EEPROM

– Serial Programmable Volatile Register
– Non-Volatile EEPROM to Store Customer

Settings

• Very Flexible Input Clocking Concept

– External Crystal: 8 to 32 MHz
– On-Chip VCXO: Pull-Range ± 150 ppm
– Single-Ended LVCMOS up to 160 MHz

• Selectable Output Frequency up to 230 MHz

• Very Low-Noise PLL Core

– Integrated PLL Loop Filter Components
– Very Low Period Jitter (typ 60 ps)

• Highly Flexible Clock Driver

– Three User-Definable Control Inputs

[S0/S1/S2] e.g. SSC-Selection, Frequency

Switching, Output Enable or Power Down
– Programmable SSC Modulation
– Enables 0-PPM Clock Generation
– Generates Common Clock Frequencies

Used with TI DaVinci™, OMAP™, DSPs
– Generates Highly-Accurate Clocks for

Video, Audio, USB, IEEE1394, RFID,

BlueTooth™, WLAN, Ethernet and GPS

• 1.8 V Device Power Supply

• Separate Output Supply Pins

– CDCE949: 3.3 V and 2.5 V
– CDCEL949: 1.8 V

• Wide Temperature Range –40 ° C to 85 ° C

• Packaged in TSSOP

• Development and Programming Kit for Ease

PLL Design and Programming (TI-Pro Clock)

APPLICATIONS

• D-TV, HD-TV, STB, IP-STB, DVD-Player,

DVD-Recorder, Printer

• General Purpose Frequency Synthesizing

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DaVinci, OMAP, Pro Clock are trademarks of Texas Instruments.
BlueTooth is a trademark of Bluetooth SIG, Inc.
I2C is a trademark of Philips Electronics.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2007, Texas Instruments Incorporated

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CDCE949
CDCEL949

SCAS844 – JUNE 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock
synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. Each
output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent
configurable PLLs.

The CDCx949 has separate output supply pins, V
CDC E949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.
Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external
control signal, i.e. a PWM signal.

The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth™,
Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency such as
27-MHz.

All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This
is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically
adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application.
It is preset to a factory-default configuration (see the Default Device Configuration section). It can be
reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system
programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation
including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and
choosing between low level or 3-state for the output-disable function.

The CDCx949 operates in a 1.8-V environment. It is characterized for operation from –40 ° C to 85 ° C.

, 1.8 V for the CDC EL949, and 2.5 V to 3.3 V for

DDOUT

DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

NAME NO. (TSSOP24)

Y1, Y2, ...Y9 O LVCMOS outputs
Xin/CLK 1 I Crystal oscillator input or LVCMOS clock input (selectable via SDA/SCL bus)

Xout 24 O Crystal oscillator output (leave open or pull up when not used)
V

Ctrl

V

DD

V

DDOUT

GND 5, 9, 14, 20 Ground Ground
S0 2 I User-programmable control input S0; LVCMOS inputs; internal pull-up 500 k Ω

SDA / S1 23 I/O / I pull-up 500 k Ω ; or

SCL / S2 22 I

2

21, 19, 18, 7, 8,

16, 15, 11, 12

4 I VCXO control voltage (leave open or pull up when not used)

3, 13 Power 1.8V power supply for the device

6, 10, 17 Power

I/O

CDCEL949: 1.8 V supply for all outputs
CDCE949: 3.3 V or 2.5 V supply for all outputs

SDA: Bi-directional serial data input/output (default configuration), LVCMOS; internal
S1: User-programmable control input; LVCMOS inputs; internal pull-up 500 k Ω

SCL: Serial clock input (default configuration), LVCMOS; internal pull-up 500 k Ω ; or
S2: User-programmable control input; LVCMOS inputs; internal pull-up 500 k Ω

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EEPROM

Xin/CLK

Xout

V

DD

GND

Vctr

V

DDOUT

VCXO

XO

LVCMOS

Y2

Y1

Y3

LV

CMOS

Pdiv1

10-Bit

Y4

Y5

Y6

Y7

Y8

Y9

LV

CMOS

Pdiv9

7-Bit

Pdiv8

7-Bit

M8

M9

LV

CMOS

LV

CMOS

Pdiv7

7-Bit

Pdiv6

7-Bit

M6

M7

LV

CMOS

LV

CMOS

Pdiv5

7-Bit

Pdiv4

7-Bit

M4

M5

LV

CMOS

LV

CMOS

Pdiv3

7-Bit

Pdiv2

7-Bit

M2

M3

LV

CMOS

Programming

and

SDA/SCL

Register

InputClock

M1

PLL Bypass

PLL 1

withSSC

MUX1

PLL Bypass

PLL 2

withSSC

MUX2

PLL Bypass

PLL 3

withSSC

MUX3

PLL Bypass

PLL 4

withSSC

M

U

X4

S0
S1/SDA
S2/SCL

FUNCTIONAL BLOCK DIAGRAM

CDCE949

CDCEL949

SCAS844 – JUNE 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V
V
V
I

I

I

O

T

stg

T

J

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

(2) The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.

Supply voltage range –0.5 to 2.5 V

DD

Input voltage range

I

Output voltage range

O

Input current (Vi< 0, Vi> VDD) 20 mA
Continuous output current 50 mA
Storage temperature range –65 to 150 ° C
Maximum junction temperature 125 ° C

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2)

(2)

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(1)

VALUE UNIT

–0.5 to V

–0.5 to V

+ 0.5 V

DD

+ 0.5 V

DDOUT

3

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CDCE949
CDCEL949

SCAS844 – JUNE 2007

THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE

PARAMETER

T

Thermal Resistance Junction to Ambient

JA

T

Thermal Resistance Junction to Case — 26

JC

(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

RECOMMENDED OPERATING CONDITIONS

V

V

V
V
V

V

V

IOH/I

C
T

DD

DD(OUT)

IL
IH
I(thresh)

IS

ICLK

OL

L

A

Device supply voltage 1.7 1.8 1.9 V
Output Yx supply

voltage

CDCE949 2.3 3.6

CDCEL949 1.7 1.9
Low level input voltage LVCMOS 0.3 × V
High level input voltage LVCMOS 0.7 × V
Input voltage threshold LVCMOS 0.5 × V
Input voltage range S0 0 1.9
Input voltage range S1, V

S2, SDA, SCL

= 0.5 V

Ithresh

DD

Input voltage range CLK 0 1.9 V

V

= 3.3 V ± 12 mA

DDout

Output current V

= 2.5 V ± 10 mA

DDout

V

= 1.8 V ± 8 mA

DDout

Output load LVCMOS 10 pF
Operating free-air temperature –40 85 ° C

(1)

AIRFLOW TSSOP24

(lfm) ° C/W

0 85
150 80
250 78
500 76

MIN NOM MAX UNIT

DD

DD

0 3.6

V

DD

V
V
V

V

RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS

(1)

MIN NOM MAX UNIT

f

Xtal

Crystal Input frequency range (fundamental mode) 8 27 32 MHz
ESR Effective series resistance 100 Ω
f

PR

V

(Ctrl)

C0/C
C

L

Pulling range (0 V ≤ V

Ctrl

Frequency control voltage 0 V

Pullability ratio 220

1

On-chip load capacitance at Xin and Xout 0 20 pF

≤ 1.8 V)

(2)

± 120 ± 150 ppm

DD

(1) For more information about VCXO configuration and crystal recommendation see application report SCAA085 .
(2) Pulling range depends on crystal type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ± 120 ppm

applies for crystal listed in the application report SCAA085 .

EEPROM SPECIFICATION

MIN TYP MAX UNIT

EEcyc EEcyc programming cycles of EEPROM 1000 cycles
EEret EEret data retention 10 years

V

4

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TIMING REQUIREMENTS

over recommended ranges of supply voltage, load and operating free-air temperature

CLK_IN Requirements MIN NOM MAX UNIT

f

tr/ t
duty

f
t
t
t
t
t
t
t
t
t
t

(CLK)

f

CLK

LVCMOS clock input frequency MHz

Rise and fall time CLK signal (20% to 80%) 3 ns
Duty cycle CLK at V

/ 2 40% 60%

DD

SDA/SCL TIMING REQUIREMENTS (see Figure 12 ) UNIT

(SCL)
su(START)
h(START)
w(SCLL)
w(SCLH)
h(SDA)
su(SDA)
r
f
su(STOP)
BUF

SCL clock frequency 0 100 0 400 kHz
START setup time (SCL high before SDA low) 4.7 0.6 μ s
START hold time (SCL low after SDA low) 4 0.6 μ s
SCL low-pulse duration 4.7 1.3 μ s
SCL high-pulse duration 4 0.6 μ s
SDA hold time (SDA valid after SCL low) 0 3.45 0 0.9 μ s
SDA setup time 250 100 ns
SCL/SDA input rise time 1000 300 ns
SCL/SDA input fall time 300 300 ns
STOP setup time 4.0 0.6 μ s
Bus free time between a STOP and START condition 4.7 1.3 μ s

PLL Bypass Mode 0 160
PLL Mode 8 160

CDCE949

CDCEL949

SCAS844 – JUNE 2007

STANDARD FAST

MODE MODE

MIN MAX MIN MAX

DEVICE CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

OVERALL PARAMETER

I

DD

I

DD(OUT)

I

DD(PD)

V
f

VCO

f

OUT

Supply current (see Figure 3 ) mA

Supply current (see Figure 4 and No load, all outputs on,

Figure 5 ) f

Power down current. Every circuit
powered down except SDA/SCL

Supply voltage Vdd threshold for power

(PUC)

up control circuit
VCO frequency range of PLL 80 230 MHz
LVCMOS output frequency 230 MHz

LVCMOS PARAMETER

V
I

I

I

IH

I

IL

LVCMOS input voltage VDD = 1.7 V; II = –18 mA –1.2 V

IK

LVCMOS input current VI= 0 V or VDD; V
LVCMOS input current for S0/S1/S2 VI= VDD; V
LVCMOS input current for S0/S1/S2 VI= 0 V; V
Input capacitance at Xin/Clk V

C

Input capacitance at Xout V

I

Input capacitance at S0/S1/S2 VIS= 0 V or V

(1) All typical values are at respective nominal VDD.

All outputs off, f
MHz, f

out

= 135 MHz;

VCO

= 27 MHz

fIN= 0 MHz, V

DD

= 0 V or V

ICLK

= 0 V or V

IXout

= 27

CLK

= 1.9 V 50 μ A

DD

= 1.9 V ± 5 μ A

DD

= 1.9 V 5 μ A

DD

= 1.9 V –4 μ A

DD

DD

DD

All PLLs on 38
Per PLL 9
CDCE949

V

=3.3 V

DDOUT

CDCEL949
V

=1.8 V

DDOUT

0.85 1.45 V

(1)

MAX UNIT

4

2

6
2 pF
3

mA

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CDCE949
CDCEL949

SCAS844 – JUNE 2007

DEVICE CHARACTERISTICS (Continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

CDCE949 – LVCMOS PARAMETER FOR V

V

V

t

PLH

t

PHL

tr/t

t

jit(cc)

t

jit(per)

t

sk(o)

odc Output duty cycle

LVCMOS high-level output voltage V

OH

LVCMOS low-level output voltage V

OL

,

Propagation delay PLL bypass 3.2 ns
Rise and fall time V

f

Cycle-to-cycle jitter

Peak-to-peak period jitter

Output skew

(2) (3)

(2) (3)

(4)

(5)

CDCE949 – LVCMOS PARAMETER FOR V

V

V

t

PLH

t

PHL

tr/t

t

jit(cc)

t

jit(per)

t

sk(o)

odc Output duty cycle

LVCMOS high-level output voltage V

OH

LVCMOS low-level output voltage V

OL

,

Propagation delay PLL bypass 3.4 ns
Rise and fall time V

f

Cycle-to-cycle jitter

Peak-to-peak period jitter

Output skew

(2) (3)

(2) (3)

(4)

(5)

= 3.3 V – MODE

DDOUT

V

= 3 V, IOH= –0.1 mA 2.9

DDOUT

= 3 V, IOH= –8 mA 2.4 V

DDOUT

V

= 3 V, IOH= –12 mA 2.2

DDOUT

V

= 3 V, IOL= 0.1 mA 0.1

DDOUT

= 3 V, IOL= 8 mA 0.5 V

DDOUT

V

= 3 V, IOL= 12 mA 0.8

DDOUT

= 3.3 V (20%–80%) 0.6 ns

DDOUT

1 PLL switching, Y2-to-Y3 60 90
4 PLLs switching, Y2-to-Y9 120 170
1 PLL switching, Y2-to-Y3 70 100
4 PLLs switching, Y2-to-Y9 130 180
f

= 50 MHz; Y1-to-Y3 60

OUT

f

= 50 MHz; Y2-to-Y5 or Y6-to-Y9 160

OUT

f

= 100 MHz; Pdiv = 1 45 55 %

VCO

= 2.5 V – MODE

DDOUT

V

= 2.3 V, IOH= –0.1 mA 2.2

DDOUT

= 2.3 V, IOH= –6 mA 1.7 V

DDOUT

V

= 2.3 V, IOH= –10 mA 1.6

DDOUT

V

= 2.3 V, IOL= 0.1 mA 0.1

DDOUT

= 2.3 V, IOL= 6 mA 0.5 V

DDOUT

V

= 2.3 V, IOL= 10 mA 0.7

DDOUT

= 2.5 V (20%–80%) 0.8 ns

DDOUT

1 PLL switching, Y2-to-Y3 60 90 ps
4 PLLs switching, Y2-to-Y9 120 170
1 PLL switching, Y2-to-Y3 70 100 ps
4 PLLs switching, Y2-to-Y9 130 180
f

= 50 MHz; Y1-to-Y3 60

OUT

f

= 50 MHz; Y2-to-Y5 or Y6-to-Y9 160

OUT

f

= 100 MHz; Pdiv = 1 45 55 %

VCO

(1) All typical values are at respective nominal VDD.
(2) 10000 cycles.
(3) Jitter depends on device configuration. Data is taken under the following conditions: 1-PLL: fIN= 27 MHz, Y2/3 = 27 MHz, (measured at

Y2), 4-PLL: fIN= 27 MHz, Y2/3 = 27 MHz, (manured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz, Y8/9 = 48 MHz.

(4) The t

sampled on rising edge (tr).

specification is only valid for equal loading of each bank of outputs and outputs are generated from the same divider; data

sk(o)

(5) odc depends on output rise- and fall-time (tr/tf).

(1)

MAX UNIT

ps

ps

ps

ps

6

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10pF

1kW

LVCMOS

CDCE949

CDCEL949

1kW

LVCMOS LVCMOS

CDCE949

CDCEL949

Driver

Impedance

~50 W

LineImpedance

Zo=50 W

Series

Termination

(Optional)

CDCE949

CDCEL949

SCAS844 – JUNE 2007

DEVICE CHARACTERISTICS (Continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

SAVE THIS CDCEL949 – LVCMOS PARAMETER FOR V

V

DDOUT

V

V

t

PLH

t

PHL

tr/t

t

jit(cc)

t

jit(per)

t

sk(o)

odc Output duty cycle

LVCMOS high-level output voltage V

OH

LVCMOS low-level output voltage V

OL

,

Propagation delay PLL bypass 2.6 ns
Rise and fall time V

f

Cycle-to-cycle jitter

Peak-to-peak period jitter

Output skew

(2) (3)

(2) (3)

(4)

(5)

DDOUT

V

DDOUT

V

DDOUT
DDOUT

V

DDOUT

DDOUT

1 PLL switching, Y2-to-Y3 70 120 ps
4 PLLs switching, Y2-to-Y9 120 170
1 PLL switching, Y2-to-Y3 90 140 ps
4 PLLs switching, Y2-to-Y9 130 190
f

OUT

f

OUT

f

VCO

= 50 MHz; Y1-to-Y3 60 ps
= 50 MHz; Y2-to-Y5 or Y6-to-Y9 160
= 100 MHz; Pdiv = 1 45 55 %

= 1.8 V – MODE

DDOUT

= 1.7 V, IOH= –0.1 mA 1.6
= 1.7 V, IOH= –4 mA 1.4 V
= 1.7 V, IOH= –8 mA 1.1
= 1.7 V, IOL= 0.1 mA 0.1
= 1.7 V, IOL= 4 mA 0.3 V
= 1.7 V, IOL= 8 mA 0.6

= 1.8 V (20%–80%) 0.7 ns

SDA/SCL PARAMETER

V
I

IH

V
V

V
C

SCL and SDA input clamp voltage V

IK

SCL and SDA input current VI= VDD; V
SDA/SCL input high voltage

IH

SDA/SCL input low voltage

IL

SDA low-level output voltage IOL= 3 mA, V

OL

SCL/SDA input capacitance VI= 0 V or V

I

(6)

(6)

= 1.7 V; II= –18 mA –1.2 V

DD

= 1.9 V ± 10 μ A

DD

0.7 V

DD

= 1.7 V V

DD

DD

(1) All typical values are at respective nominal VDD.
(2) 10000 cycles.
(3) Jitter depends on device configuration. Data is taken under the following conditions: 1-PLL: fIN= 27 MHz, Y2/3 = 27 MHz, (measured at

Y2), 4-PLL: fIN= 27 MHz, Y2/3 = 27 MHz, (measured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz, Y8/9 = 48 MHz.

(4) The t

sampled on rising edge (tr).

specification is only valid for equal loading of each bank of outputs and outputs are generated from same divider; data

sk(o)

(5) odc depends on output rise- and fall-time (tr/tf).
(6) SDA and SCL pins are 3.3-V tolerant.

(1)

MAX UNIT

0.3

V

DD

0.2

V

DD

3 10 pF

V
V

PARAMETER MEASUREMENT INFORMATION

Figure 1. Test Load Figure 2. Test Load for 50 Ω Board Environment

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0

10

20

30

40

50

60

70

80

90

100

10 60 110 160 210

PLL -Frequency-MHz

I

-SupplyCurrent-mA

D

D

3PLL on

V =1.8V

DD

allPLL off

1PLL on

4PLL on

2PLL on

0

5

10

15

20

25

30

35

10 30 50 70 90 110 130 150 170 190 210 230

f -OutputFrequency-MHz

OUT

I -mA

D

DOUT

alloutputsoff

9outputson

7outputson

5outputson

3outputson

1outputon

V =1.8V,
V =3.3V,
NoLoad

DD

DDOUT

10 30 50 70 90 110 130 150 170 190 210 230

f -OutputFrequency-MHz

OUT

I -mA

D

DOUT

0

2

4

6

8

10

12

alloutputsoff

9outputson

7outputson

5outputson

3outputson

1outputon

V =1.8V,
V =1.8V,
NoLoad

DD

DDOUT

CDCE949
CDCEL949

SCAS844 – JUNE 2007

TYPICAL CHARACTERISTICS

CDCE949 AND CDCEL949 SUPPLY CURRENT CDCE949 OUTPUT CURRENT

vs vs

PLL FREQUENCY OUTPUT FREQUENCY

Figure 3. Figure 4.

CDCEL949 OUTPUT CURRENT

vs

OUTPUT FREQUENCY

8

Figure 5.

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APPLICATION INFORMATION

Control Terminal Configuration

The CDCE949/CDCEL949 has three user-definable control terminals (S0, S1 and S2) which allow external
control of device settings. They can be programmed to perform any of the following functions:

• Spread-Spectrum Clocking selection: Spread-type and spread-amount selection

• Frequency selection: Switching between any of two user-defined frequencies

• Output-State selection: Output configuration and power-down control

The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.

Table 1. Control Terminal Definition

External Control-Bits PLL1 Setting PLL2 Setting PLL3 Setting PLL4 Setting Y1 Setting

Control Function

CDCE949

CDCEL949

SCAS844 – JUNE 2007

SSC Selection

PLL Frequency Selection

Output Y2/Y3 Selection

SSC Selection

PLL Frequency Selection

Output Y4/Y5 Selection

PLL Frequency Selection

SSC Selection

Output Y6/Y7 Selection

PLL Frequency Selection

SSC Selection

Table 2. PLLx Setting (can be selected for each PLL individual)

SSC Selection (Center/Down)

SSCx [3-bits] Center Down

0 0 0 0% (off) 0% (off)
0 0 1 ± 0.25% –0.25%
0 1 0 ± 0.5% –0.5%
0 1 1 ± 0.75% –0.75%
1 0 0 ± 1.0% –1.0%
1 0 1 ± 1.25% –1.25%
1 1 0 ± 1.5% –1.5%
1 1 1 ± 2.0% –2.0%

FREQUENCY SELECTION

FSx FUNCTION

0 Frequency0
1 Frequency1

OUTPUT SELECTION

YxYx FUNCTION

0 State0
1 State1

(1) Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register;
(2) Frequency0 and Frequency1 can be any frequency within the specified f
(3) State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,

3-state, low or active

(2)

(3)

(Y2 ... Y9)

range.

VCO

Output Y8/Y9 Selection

Output Y1 and Power Down Selection

(1)

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