Texas Instruments CDCE906PWRG4, CDCE906 Datasheet

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

S0/A0/CLK_SEL

S1/A1

GND CLK_IN0 CLK_IN1

GND

SDATA

SCLOCK

Y5 Y4 V

CCOUT2

GND Y3 Y2 V

CCOUT1

GND Y1 Y0

PW PACKAGE

(TOP VIEW)

TSSOP 20

Pitch 0,65 mm

6.6 x 6.6

CDCE906

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SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

FEATURES

• High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider • Programmable Output Slew-Rate Control

• User Programmable PLL Frequencies

• EEPROM Programming Without the Need to Apply High Programming Voltage • Commercial Temperature Range 0 ° C to 70 ° C

• Easy In-Circuit Programming via SMBus Data • Development and Programming Kit for Easy

Interface PLL Design and Programming

• Wide PLL Divider Ratio Allows 0-ppm Output Clock Error • Packaged in 20-Pin TSSOP

• Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (f

44.1, 48, 96 kHz)

• Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal

• Accepts Crystal Frequencies from 8 MHz up to 54 MHz

• Accepts LVCMOS or Differential Input Frequencies up to 167 MHz

• Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals

• Six LVCMOS Outputs with Output Frequencies up to 167 MHz

• LVCMOS Outputs can be Programmed for Complementary Signals

• Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output

• PLL Loop Filter Components Integrated

• Low Period Jitter (Typ 60 ps)

• Features Spread Spectrum Clocking (SSC) for

Lowering System EMI

• Programmable Center Spread SSC Modulation ( ± 0.1%, ± 0.25%, and ± 0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency

= 16, 22.05, 24, 32,

• Programmable Down Spread SSC Modulation

(1%, 1.5%, 2%, and 3%)

(SRC) for Lowering System EMI

• 3.3-V Device Power Supply

(TI Pro-Clock™)

TERMINAL ASSIGNMENT

DESCRIPTION

The CDCE906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

2 Pro-Clock is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

DESCRIPTION (CONTINUED)

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDCE906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13 ) and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different device setting is programmed via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE906 has three power supply pins, V operates from a single 3.3-V supply voltage. V V

CCOUT1

supplies the outputs Y0 and Y1 and V

supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited. The CDCE906 is characterized for operation from 0 ° C to 70 ° C.

, V

CCOUT1

CCOUT2

and V

CCOUT2

. V

CCOUT2

is the power supply for the device. It

are the power supply pins for the outputs.

supplies the outputs Y2, Y3, Y4, and Y5. Both outputs

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PLL1

2LVCMOS

Differential

Input

MUX

PLL3

PFD

Filter

VCO

PLL2

w/SSC

PFD Filter VCO

SO/AO/CLK_SEL

S1/A1

SCLOCK

OutputSwitchMatrix

CMOS

EEPROM

LOGIC

SMBUS

LOGIC

PFD

Filter

VCO

SDATA

VCO1Bypass

VCO2Bypass

VCO3Bypass

MUX

6xProgrammable7-BitDividerP0,P1,P2,P3,P4,P5,andInversionLogic

5x6ProgrammableSwitch A

PLL Bypass

GND V

CCOUT1

GND V

CCOUT2

prg. 9Bit

DividerM

prg.12Bit

DividerN

prg.9Bit DividerM

prg.12Bit

DividerN

prg.9Bit

DividerM

prg.12Bit

DividerN

Crystalor

ClockInput

CLK_IN1

FactoryPrg.

CLK_IN0

SSC

On/Off

6x6ProgrammableSwitchB

5x6 − Switch A

Input CLK

(PLL Bypass)

PLL 1

PLL 2

non SSC

PLL 2

w/ SSC

PLL 3

6x6 − Switch B7-Bit Divider

Programming

FUNCTIONAL BLOCK DIAGRAM

CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

OUTPUT SWITCH MATRIX

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CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

TERMINAL FUNCTIONS

TERMINAL

NAME

Y0 to Y5 O LVCMOS outputs

TSSOP20

NO.

11, 12, 15,

16, 19, 20

CLK_IN0 5 I

CLK_IN1 6 I/O V

CCOUT1

CCOUT2

3, 7 Power 3.3-V power supply for the device.

14 Power Power supply for outputs Y0, Y1. 18 Power Power supply for outputs Y2, Y3, Y4, Y5.

GND 4, 8, 13, 17 Ground Ground S0, A0,

CLK_SEL

1 I CLK_SEL (selects one of two LVCMOS clock inputs), dependent on the SMBus settings; LVCMOS

S1, A1 2 I SDATA 9 I/O Serial control data input/output for SMBus controller; LVCMOS input

SCLOCK 10 I Serial control clock input for SMBus controller; LVCMOS input

I/O DESCRIPTION

Dependent on SMBus settings, CLK_IN0 is the crystal oscillator input and can also be used as LVCMOS input or as positive differential signal inputs.

Dependent on SMBus settings, CLK_IN1 is serving as the crystal oscillator output or can be the second LVCMOS input or the negative differential signal input.

User programmable control input S0 (PLL bypass or power-down mode) or AO (address bit 0), or inputs; internal pullup 150 k Ω .

User programmable control input S1 (output enable/disable or all output low), A1 (address bit 1), dependent on the SMBus settings; LVCMOS inputs; internal pullup 150 k Ω

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V V V I

stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

Supply voltage range – 0.5 to 4.6 V

Input voltage range

Output voltage range

(2)

Input current (VI< 0, VI> VCC) ± 20 mA Continuous output current ± 50 mA Storage temperature range – 65 to 150 ° C Maximum junction temperature 125 ° C

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(1)

VALUE UNIT

– 0.5 to V – 0.5 to V

+ 0.5 V

PACKAGE THERMAL RESISTANCE

for TSSOP20 (PW) Package

(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

Thermal resistance junction-to-ambient

Thermal resistance junction-to-case 19.7

(1)

PARAMETER AIRFLOW (LFM) ° C/W

0 66.3 150 59.3 250 56.3 500 51.9

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SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

CCOUT1

CCOUT2

Ithresh

| Differential input voltage 0.1 V

IOH/ I IOH/ I C

(1) The minimum output voltage can be down to 1.8 V. See the application note for more information.

Device supply voltage 3 3.3 3.6 V

(1)

Output Y0,Y1 supply voltage 2.3 3.6 V

(1)

Output Y2, Y3, Y4, Y5 supply voltage 2.3 3.6 V Low level input voltage LVCMOS 0.3 V High level input voltage LVCMOS 0.7 V Input voltage threshold LVCMOS 0.5 V

Input voltage range LVCMOS 0 3.6 V

Common-mode for differential input voltage 0.2 Vcc- 0.6 V Output current (3.3 V) ± 6 mA

Output current (2.5 V) ± 4 mA

Output load LVCMOS 25 pF Operating free-air temperature 0 70 ° C

RECOMMENDED CRYSTAL SPECIFICATIONS

MIN NOM MAX UNIT

Xtal

ESR Effective series resistance C

(1) For crystal frequencies above 50 MHz the effective series resistor should not exceed 50 Ω to assure stable start-up condition. (2) Maximum Power Handling (Drive Level) see Figure 16 .

Crystal input frequency range (fundamental mode) 8 27 54 MHz

(1) (2)

Input capacitance CLK_IN0 and CLK_IN1 3 pF

15 60 Ω

CDCE906

V V V

EEPROM SPECIFICATION

MIN TYP MAX UNIT

EEcyc Programming cycles of EEPROM 100 1000 Cycles EEret Data retention 10 Years

TIMING REQUIREMENTS

over recommended ranges of supply voltage, load, and operating-free air temperature

MIN NOM MAX UNIT

CLK_IN REQUIREMENTS

CLK_IN

tr/ t

duty

REF

CLK_IN clock input frequency (LVCMOS or Differential) MHz

Rise and fall time CLK_IN signal (20% to 80%) 4 ns Duty cycle CLK_IN at V

/ 2 40% 60%

SMBus TIMING REQUIREMENTS (see Figure 11 )

SCLK

h(START)

w(SCLL)

w(SCLH)

su(START)

h(SDATA)

su(SDATA)

SCLK frequency 100 kHz START hold time 4 µ s SCLK low-pulse duration 4.7 µ s SCLK high-pulse duration 4 50 µ s START setup time 0.6 µ s SDATA hold time 0.3 µ s SDATA setup time 0.25 µ s SCLK / SDATA input rise time 1000 ns SCLK / SDATA input fall time 300 ns

PLL mode 1 167 PLL bypass mode 0 167

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CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

TIMING REQUIREMENTS (continued)

over recommended ranges of supply voltage, load, and operating-free air temperature

MIN NOM MAX UNIT

su(STOP)

BUS

POR

DEVICE CHARACTERISTICS

over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1

OVERALL PARAMETER

CCPD

PUC

VCO

OUT

LVCMOS PARAMETER

LVCMOS PARAMETER FOR V

PLH

PHL

tr0/t

tr1/t

tr2/t

tr3/t

STOP setup time 4 µ s Bus free time 4.7 µ s Time in which the device must be operational after power-on reset 500 ms

PARAMETER TEST CONDITIONS MIN TYP

Supply current

(2)

Power down current. Every circuit powered down except SMBus

All PLLs on, all outputs on, f

= 80 MHz, f

out

= 160 MHz

vco

fIN= 0 MHz, V

CLK_IN

= 3.6 V 50 µ A

= 27 MHz, 90 115 mA

Supply voltage Vccthreshold for power up control circuit

VCO frequency of internal PLL (any of three PLLs)

Normal speed-mode

(3)

High-speed mode

LVCMOS output frequency range

LVCMOS input voltage V LVCMOS input current (CLK_IN0 /

CLK_IN1) LVCMOS input current (For S1/S0) VI= VCC, V LVCMOS input current (For S1/S0) VI= 0 V, V Input capacitance at CLK_IN0 and VI= 0 V or V

CLK_IN1

ccout

LVCMOS high-level output voltage V

LVCMOS low-level output voltage V

Propagation delay ns

Rise and fall time for output slew rate 0

Rise and fall time for output slew rate 1

Rise and fall time for output slew rate 2

Rise and fall time for output slew rate 3 (Default Configuration)

(4)

= 2.5 V or 3.3 V 167 MHz

= 3 V, II= – 18 mA – 1.2 V

VI= 0 V or VCC, V

= 3.6 V 5 µ A

= 3.6 V -35 -10 µ A

= 3.3-V Mode

= 3 V, IOH= – 0.1 mA 2.9

ccout

= 3 V, IOH= – 4 mA 2.4 V

ccout

= 3 V, IOH= – 6 mA 2.1

ccout

= 3 V, IOL= 0.1 mA 0.1

ccout

= 3 V, IOL= 4 mA 0.5 V

ccout

= 3 V, IOL= 6 mA 0.85

ccout

All PLL bypass 9 VCO bypass 11

= 3.3 V (20% – 80%) 1.7 3.3 4.8 ns

ccout

= 3.3 V (20% – 80%) 1.5 2.5 3.2 ns

ccout

= 3.3 V (20% – 80%) 1.2 1.6 2.1 ns

ccout

= 3.3 V (20% – 80%) 0.4 0.6 1 ns

ccout

All PLLs 80 200 PLL2 with SSC 80 167 MHz

(3)

= 3.6 V ± 5 µ A

180 300

(1)

MAX UNIT

2.1 V

3 pF

(1) All typical values are at respective nominal VCC. (2) For calculating total supply current, add the current from Figure 2 , Figure 3 , and Figure 4 . Using high-speed mode of the VCO reduces

the current consumption significantly. See Figure 3

(3) Normal-speed mode or high-speed mode must be selected by the VCO frequency selection bit in Byte 6, Bit [7:5]. The min f

lower but impacts jitter-performance.

(4) The maximum output frequency may be exceeded, but specifications under the Recommended Operating Condition may change and

are no longer assured. Do not exceed the maximum power dissipation of the 20-pin TSSOP package (600 mW at no air flow).

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can be

VCO

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SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1

PARAMETER TEST CONDITIONS MIN TYP

jit(cc)

jit(per)

sk(o)

Cycle-to-cycle jitter

Peak-to-peak period jitter

Output skew (see

odc Output duty cycle

LVCMOS PARAMETER FOR V

PLH

PHL

tr0/t

tr1/t

tr2/t

tr3/t

jit(cc)

jit(per)

sk(o)

LVCMOS high-level output voltage V

LVCMOS low-level output voltage V

Propagation delay ns

Rise and fall time for output

slew rate 0 Rise and fall time for output

slew rate 1 Rise and fall time for output

slew rate 2 Rise and fall time for output

slew rate 3 (Default Configuration)

Cycle-to-cycle jitter

Peak-to-peak period jitter

Output skew (see

odc Output duty cycle

(5) (6)

1 PLL, 1 Output f 3 PLLs, 3 Outputs f

(5) (6)

1 PLL, 1 Output f 3 PLLs, 3 Outputs f

(7)

and Table 5 ) 1.6-ns rise/fall time at

(8)

= 2.5-V Mode

ccout

= 150 MHz, Pdiv = 3

vco

= 100 MHz, Pdiv = 1 45% 55%

vco

(9)

= 2.3 V, IOH= 0.1 mA 2.2

ccout

= 2.3 V, IOH= – 3 mA 1.7 V

ccout

= 2.3 V, IOH= – 4 mA 1.5

ccout

= 2.3 V, IOL= 0.1 mA 0.1

ccout

= 2.3 V, IOL= 3 mA 0.5 V

ccout

= 2.3 V, IOL= 4 mA 0.85

ccout

All PLL bypass 9 VCO bypass 11

= 2.5 V (20% – 80%) 2 3.9 5.6 ns

ccout

= 2.5 V (20% – 80%) 1.8 2.9 4.4 ns

ccout

= 2.5 V (20% – 80%) 1.3 2 3.2 ns

ccout

= 2.5 V (20% – 80%) 0.4 0.8 1.1 ns

ccout

(10) (11)

1 PLL, 1 Output f 3 PLLs, 3 Outputs f

(10) (11)

1 PLL, 1 Output f 3 PLLs, 3 Outputs f

(12)

and Table 5 ) 250 ps

(13)

2-ns rise/fall time at f

= 150 MHz, Pdiv = 3

VCO

= 100 MHz, Pdiv = 1 45% 55%

VCO

= 24.576 MHz 65 95

OUT

= 24.576 MHz 85 135

OUT

= 24.576 MHz 90 115

OUT

= 24.576 MHz 100 150

OUT

= 24.576 MHz 85 120

OUT

= 24.576 MHz 95 155

OUT

= 24.576 MHz 110 135

OUT

= 24.576 MHz 110 175

OUT

SMBus PARAMETER

C C

SCLK and SDATA input clamp voltage

SCLK and SDATA input current VI= 0 V or VCC, V

= 3 V, II= – 18 mA – 1.2 V

= 3.6 V ± 5 µ A

SCLK input high voltage 2.1 V SCLK input low voltage 0.8 V SDATA low-level output voltage IOL= 4 mA, V Input capacitance at SCLK VI= 0 V or V

ISCLK

Input capacitance at SDATA VI= 0 V or V

ISDATA

= 3 V 0.4 V

CC CC CC

(5) 50000 cycles. (6) Jitter depends on configuration. Jitter data is for normal tr/tf, input frequency = 27 MHz, f (7) The t (8) odc depends on output rise and fall time (tr/tf); above limits are for normal tr/tf.

specification is only valid for equal loading of all outputs.

sk(o)

= 147 MHz output.

VCO

(9) There is a limited drive capability at output supply voltage of 2.5 V. For proper termination, see application report SCAA080 . (10) 50000 cycles. (11) Jitter depends on configuration. Jitter data is for normal tr/tf, input frequency = 27 MHz, f (12) The t (13) odc depends on output rise and fall time (tr/tf); above limits are for normal tr/tf.

specification is only valid for equal loading of all outputs.

sk(o)

= 147 MHz output.

VCO

(1)

3 10 pF 3 10 pF

CDCE906

MAX UNIT

200 ps

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1 kW

10 pF

LVCMOS

CDCE906

PLL 1+PLL 2SSC+PLL3

V =3.3V, Mdiv=1,

Ndiv=2, P div=1, VCOnormal-speedmode

PLL 1+PLL 2+PLL3

PLL 1+PLL 2

f -[MHz]

VCO

210

I -[mA]

PLL 1

20017016015090

140130120

120

110

100

190180

CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

PARAMETER MEASUREMENT INFORMATION

Figure 1. Test Load

Figure 2. ICCvs Number of PLLs and VCO Frequency (VCO at Normal-Speed Mode, Byte 6 Bit [7:5])

TYPICAL CHARACTERISTICS

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PLL 1+PLL 2SSC+PLL3

V =3.3V, Mdiv=1,

Ndiv=2, P div=1, VCOhigh-speedmode

PLL 1+PLL 2+PLL3

PLL 1+PLL 2

f -[MHz]

VCO

310

-[mA]

PLL 1

300250190180

170160150

120

140

110

130

100

270260240230200 220210 290280

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180

6Outputs

5Outputs

4Outputs

3Outputs

2Outputs

1Outputs

V =3.3V, Mdiv=1,

Ndiv=2, P div=1

f -[MHz]

VCO

I -[mA]

TYPICAL CHARACTERISTICS (continued)

CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

Figure 3. ICCvs Number of PLLs and VCO Frequency (VCO at High-Speed Mode, Byte 6 Bit [7:5])

Figure 4. I

vs Number of Outputs and VCO Frequency

CCOUT

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0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

90 100 110 120 130 140 150 160 170 180 190 200 210 220

VOHatV =3.6V

CCOUT

VOHatV =2.3V

CCOUT

VOLatV =3.6V

CCOUT

VOLatV =2.3V

CCOUT

f -[MHz]

OUT

VOUT-[V]

V =3.3V, Mdiv=4,

Ndiv=15, P div=1

CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

TYPICAL CHARACTERISTICS (continued)

Figure 5. Output Swing vs Output Frequency

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CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

APPLICATION INFORMATION

SMBus Data Interface

To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. It follows the SMBus specification Version 2.0, which is based upon the principals of operation of I2C. More details of the SMBus specification can be found at http://www.smbus.org .

Through the SMBus, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the SMBus data interface initialize to their default setting upon power-up, and therefore using this interface is optional. The clock device register changes are normally made upon system initialization, if any are required.

Data Protocol

The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operations from the controller.

For Block Write/Read operations, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individually addressed bytes.

Once a byte has been sent, it will be written into the internal register and effective immediately. With the rising edge of the ACK bit, this applies to each transferred byte, independent of whether this is a Byte Write or a Block Write sequence.

If the EEPROM write cycle is initiated, the data of the internal SMBus register is written into the EEPROM. During EEPROM write, no data is allowed to be sent to the device via the SMBus until the programming sequence is completed. Data, however, can be readout during the programming sequence (byte read or block read). The programming status can be monitored by EEPIP, byte 24 bit 7.

The offset of the indexed byte is encoded in the command code, as described in Table 1 . The Block Write and Block Read protocol is outlined in Figure 9 and Figure 10 , while Figure 7 and Figure 8

outlines the corresponding Byte Write and Byte Read protocol.

Slave Receiver Address (7 bits)

A6 A5 A4 A3 A2 A1* A0* R/W

1 1 0 1 0 0 1 0

* Address bits A0 and A1 are programmable by the Configuration Inputs S0 and S1 (Byte 10 Bit [1:0] and Bit [3:2]. This allows addressing up to four devices connected to the same SMBus.

Table 1. Command Code Definition

Bit Description

(6:0) Byte Offset for Read and Write operation.

0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation

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1 7 1 1 8 1 1

S Slave Address Wr A Data Byte A P

S Start Condition

Reapeated Start Condition

Read (Bit Value = 1)

Write (Bit Value = 0) A Acknowledge (ACK = 0 and NACK = 1) P Stop Condition

PE Packet Error

Master to Slave Transmission

Slave to Master Transmission

CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

Figure 6. Generic Programming Sequence

Byte Write Programming Sequence

1 7 1 1 8 1 8 1 1 S Slave Address Wr A CommandCode A Data Byte A P

Figure 7. Byte Write Protocol

Byte Read Programming Sequence

1 7 1 1 8 1 1 7 1 1 S Slave Address Wr A CommandCode A S Slave Address Rd A

8 1 1

Data Byte A P

Figure 8. Byte Read Protocol

Block Write Programming Sequence

1 7 1 1 8 1 8 1

S Slave Address Wr A CommandCode A Byte Count N A

8 1 8 1 8 1 1

Data Byte 0 A Data Byte 1 A - - - - - Data Byte N – 1 A P

(1)

Data Byte 0 is reserved for revision code and vendor identification. However, this byte is used for internal test. Do not write into it other

than 0000 0001.

(1)

Figure 9. Block Write Protocol

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P S P

SCLK

SDATA

Bit 7 (MSB)

Bit 6 Bit 0 (LSB)

h(SDATA)

su(SDATA)

su(START)

(BUS)

h(START)

r(SM)

f(SM)

W(SCLH)

W(SCLL)

su(STOP)

IH(SM)

IL(SM)

IH(SM)

IL(SM)

SDATA

SCLK

SMB Host

CDCE906

BUS

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

Block Read Programming Sequence

1 7 1 1 8 1 1 7 1 1 S Slave Address Wr A CommandCode A Sr Slave Address Rd A

8 1 8 1 8 1 1

Byte Count N A Data Byte 0 A - - - - - Data Byte N – 1 A P

Figure 10. Block Read Protocol

CDCE906

Figure 11. Timing Diagram Serial Control Interface

SMBus Hardware Interface

The following diagram shows how the CDCE906 clock synthesizer is connected to the SMBus. Note that the current through the pullup resistors (R CDCE906 is not connected to the SMBus, then SDATA and SCLK inputs have to be connected with 10-k Ω pullup resistors to V

to avoid floating input conditions.

) must meet the SMBus specifications (min 100 µ A, max 350 µ A). If the

Figure 12. SMBus Hardware Interface

Product Folder Link(s): CDCE906

+ 29 hidden pages

Texas Instruments CDCE906PWRG4, CDCE906 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

TERMINAL ASSIGNMENT

DESCRIPTION

DESCRIPTION (CONTINUED)

ABSOLUTE MAXIMUM RATINGS

PACKAGE THERMAL RESISTANCE

RECOMMENDED OPERATING CONDITIONS

RECOMMENDED CRYSTAL SPECIFICATIONS

EEPROM SPECIFICATION

TIMING REQUIREMENTS

DEVICE CHARACTERISTICS

PARAMETER MEASUREMENT INFORMATION

TYPICAL CHARACTERISTICS

APPLICATION INFORMATION

SMBus Data Interface

Data Protocol

Slave Receiver Address (7 bits)

Byte Write Programming Sequence

Byte Read Programming Sequence

Block Read Programming Sequence

SMBus Hardware Interface