Texas Instruments CDCE 401 INSTALLATION INSTRUCTIONS

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EN

XIN

XOUT

VSS

VDD

FOUT

SDATA

1

2

3

4

5

6

8

» ´1mm 1mm

M0018-03

OSCILLATOR IC WITH ELECTRONIC CALIBRATION

CDCE401

SCAS820 – JUNE 2006

FEATURES

• Oscillator Gain Stage Implemented

• One LVCMOS Frequency Output

• Frequency Range of Oscillator Gain Stage =

20 MHz–100 MHz

• Frequency Range of LVCMOS Output = 0.625

MHz–100 MHz

• Electronic Trimming of Oscillator Using

Capacitance Arrays

• Programmable Post Dividers x, x/2, x/4, x/8,

x/16, x/32

• Nonvolatile Storage of Settings Using

EEPROM Technology

• Easy One-Wire In-Circuit Programming Allows

Programming and Trimming of Oscillator After
Manufacturing

• EEPROM Programming Without the Need to

Apply High Voltage to the Device

• Available as Die

• Small Form Factor From Less Than 1 mm × 1

mm, Allowing the Smallest Form Factor
Available for Today’s and Next-Generation
Oscillators

• Industrial Temperature Range –40°C to 85°C

• Wide VDD Range: 2.25 V up to 3.3 V

• ESD Protection Exceeds JESD22

– >2000-V Human-Body Model (A114-B)
– >200-V Machine Model (A115_A)
– >500-V Charged-Device Model (C101-B.01)

Die Terminal Assignment

(Top View = Bond Pad View)

DESCRIPTION

The CDCE401 is designed to achieve today’s demanding challenges for crystal oscillator modules. The small
form factor of the unpackaged die or the QFN package reduces the space consumption of the device to the
technical minimum level of today’s silicon technology.

The on-die trimming capacitance allows frequency trimming of the oscillator module after the manufacturing
process. Therefore, by doing a post-manufacturing programming, crystal manufacturing tolerances can be
trimmed out.

During power up or with each enabling, the CDCE401 oscillator start-up circuit switches off all oscillator
capacitors (CXI, CXO, CBASE) to maximize negative impedance during start-up. After a certain time
(1/XTAL-frequency × 2
frequency range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

17

~ 1.311 ms–6.554 ms), the capacitances are connected to tune to the trimmed

Copyright © 2006, Texas Instruments Incorporated

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EN VDD1

DRB PACKAGE

(TOP VIEW)

NC − No internal connection

2

3

4

8

7

6

5

XIN NC

XOUT SDATA

VSS FOUT

P0012-01

CDCE401

SCAS820 – JUNE 2006

An on-die EEPROM enables nonvolatile storage of the frequency setting. For the transfer of the programming
into the EEPROM, the CDCE401 takes advantage of the SDATA input. In-circuit programming of the device is
possible.

Unlike other EEPROM-based devices, it is not necessary to apply a high supply voltage to the device in order to
program it.

The CDCE401 accepts crystals from 20 MHz up to 100 MHz. For lower frequencies, the CDCE401 provides a
programmable post-divider.

The CDCE401 features a wide supply-voltage range. This makes the device ideal to use at today’s most
commonly used supply voltage of 2.5 V, and operation at supply voltages of 2.8 V, 2.85 V, and 3 V for cellular
applications can be addressed with a single device. Therefore, use of the device in multiple different application
spaces is possible, reducing inventory costs.

The CDCE401 is characterized to work in the industrial temperature range from –40°C to 85°C.

Optional: QFN Package Terminal Assignment

For evaluation purposes, the CDCE401 is also available in a QFN package. The packaged device can be
obtained together with an EVM.

Table 1. TERMINAL FUNCTIONS

TERMINAL

NAME

EN 1 1 Input LVCMOS
FOUT 5 5 Output LVCMOS Frequency output

NC 7 N/A Not connected
SDATA 6 7 Input LVCMOS
VDD 8 8 Power Voltage supply

VSS 4 4 Ground Ground
XIN 2 2 Input oscillator Crystal oscillator input
XOUT 3 3 Output oscillator Crystal oscillator output

2

NUMBER TYPE DESCRIPTION

QFN BOND PAD

Logic select pin. Enables/disables device. Has a hysteresis of 300 mV. A
2-M Ω pullup resistor is built in.

Logic select pin. This input serves as programming input. Has a
hysteresis of 300 mV. A 2-M Ω pullup resistor is built in.

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XIN

OG[1:0]

OG[1:0]

OP[2:0]

OG[1:0]

PD[2:0]

EN

FOUT

XOUT

VSS

CXOUT
C

BASE

CXOUT
C

BASE

Var
C

BASE

Var
C

BASE

C

L

C

L

CXO[7:0]

Read-Back

Mode

CXI[7:0]

Oscillator

Gain

Stage

EEPROM

and

Control

Logic

SDATA

2MW

VDD

Divider

P

Bias

M
U
X

2MW

B0027-03

LVCMOS

LVCMOS

LVCMOS

FUNCTIONAL BLOCK DIAGRAM

CDCE401

SCAS820 – JUNE 2006

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T0130-01

VDD

EnterProgramming
SequenceandWrite

Word0(TrimPPM)

EN/SDATA

Apply Application

VDDandVerify

Settings(Measure)

Perform

StateJump

Into

Program

EEPROM

HoldforMinimum

10msto Achieve

SafeProgramming

JumpFrom

State3 State1®

BackIntoNormal

Application After

200- sLowm

2.25V VDD 3.3V£ £

3.1V VDD 3.3V£ £3.1V VDD 3.3V£ £

2.25V VDD 3.3V£ £

CDCE401

SCAS820 – JUNE 2006

DETAILED DESCRIPTION

CONTROL PIN EN: Enable

The functions of the EN control pin are listed and explained in Table 2 .

Table 2. EN Control Pin Functions

EN FUNCTION

0 Disabled: all current sources are switched off, output is in the high-impedance state.
1 Enabled: output follows the XIN/XOUT oscillation.

SINGLE-PIN INTERFACE CONTROL COMMANDS

The CDCE401 can be configured and programmed via the SDATA input pin. For this purpose, a
pulse-code-shaped signal must be applied to the device as shown in the waveforms of Figure 1 to select one of
the operation modes described in the State Flow-Diagram of the Single-Pin Interface section. During the
EEPROM programming phase, the device requires a stable VDD of 3.2 V ±100 mV for secure writing of the
EEPROM cells. After each Write-to-WordX, the written data is latched, made effective, and offers look-ahead
before the actual data is stored into the EEPROM.

Table 3 summarizes all valid programming commands.

Figure 1. Typical Programming Cycle

Table 3. Single-Pin Interface Control Commands

SDATA FUNCTION

00 1100 Enter register programming mode (state 1 → state 2); bits must be sent in the specified order with the specified

11 1011 Enter register read-back mode; bits must be sent in the specified order with the specified timing. Otherwise a

00 xxxx xxxx Write-to-word0 (state 2)
10 xxxx xxxx Write-to-word1 (state 2)
01 xxxx xxxx Write-to-word2 (state 2)
11 xxxx xxxx State-machine jump: All other patterns not defined as follows cause exit to normal mode.
11 1111 1111 Jump: Exit write-to-RAM (state 2 → state 1)
11 1111 0000 Jump: Enter EEPROM programming without an EEPROM lock (state 2 → state 3)
11 0101 0101 Jump: Enter EEPROM programming with EEPROM lock (state 2 → state 4)
11 0000 0000 Jump: Exit EEPROM programming (state 3 or state 4 → state 1)

(1) Each rising edge causes a bit to be latched.
(2) Between the bits, some longer time delays can occur, but this has no effect on the data.
(3) A Write-to-WordX is expected to be 10 bits long. After the 10

look-ahead function.

timing. Otherwise, a time-out occurs.

time-out occurs.

(1) (2) (3)

(1) (2) (3)

(1) (2) (3)

th

bit, the respective word is latched, and its effect can be observed as

4

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STATE FLOW-DIAGRAM OF THE SINGLE-PIN INTERFACE

F0016-01

PowerUp:

Read

EEPROM

and

Configure

State1: IDLE

Normal

Operation

State2:

Register

Programming

Mode

State3:

Program

EEPROM

NoLocking

State4:

Program

EEPROM

WithLocking

Write

Word2

Write

Word1

Write

Word0

State5:

Register

Read-Back

Mode

Power-UpReset

Completed

SDATA =

1111111111

SDATA =

0000000011

SDATA =

0101010111

SDATA =

1111000011

SDATA =

xxxxxxxx01

SDATA =

xxxxxxxx00

SDATA =

xxxxxxxx10

SDATA =

0000000011

SDATA =

001100

SDATA =

111011

30 Clock

Applied

th

10 Bit
Written

th

10 Bit
Written

th

10 Bit
Written

th

CDCE401

SCAS820 – JUNE 2006

NOTE: In states 2, 3, 4, and 5, the signal pin EN is disregarded and has no influence on power down.

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SDATA

EN

0

t

2

DATA

0 1 1 0 0

SDATA

DELAYED

t

1

t

6

t

f

t

5

t

4

t

8

t

r

T0042-03

t

3

t

7

CDCE401

SCAS820 – JUNE 2006

ENTER REGISTER PROGRAMMING MODE

Figure 2 shows the timing behavior of data to be written into SDATA. The sequence shown is 00 1100. If the

high period is as short as t1, this is interpreted as a 0. If the high period is as long as t3, this is interpreted as
a 1. This behavior is achieved by shifting the incoming signal SDATA by time t5into signal SDATA_DELAYED.
As can be seen in Figure 2 , SDATA_DELAYED can be used to latch (or strobe) SDATA. The specification for
the timings t1– t8, tr, and tfare given in the Timing Requirements section of this document.

Figure 2. Timing Diagram for SDATA Programming

6

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