TEXAS INSTRUMENTS CDC9842 Technical data

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CDC9842

PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER

WITH 3-STATE OUTPUTS

SCAS546B – NOVEMBER 1995 – REVISED MA Y 1996

D

Provides System Clock Solution for
Pentium/82430X/82430VX and

DW PACKAGE

(TOP VIEW)

PentiumPro 82440FX Chipsets

1

D

Four Host-Clock Outputs With
Programmable Frequency (50 MHz, 60 MHz
and 66 MHz)

D

Six PCI Clock Outputs at Half-CPU
Frequency

D

One 48-MHz Universal Serial Bus (USB)
Clock Output

D

Three 14.318-MHz Reference Clock Outputs

D

All Output Clock Frequencies Derived From
a Single 14.31818-MHz Crystal Input

D

LVTTL-Compatible Inputs and Outputs

D

Internal Loop Filters for Phase-Locked
Loops Eliminate the Need for External

V

CC

X1
X2

GND

OE
HCLK0
HCLK1

V

CC

HCLK2
HCLK3

GND
SEL1
SEL0

V

CC

2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

REF0
REF1
V

CC

REF2
SBCLK
GND
PCLK0
PCLK1
V

CC

PCLK2
PCLK3
GND
PCLK4
PCLK5

Components

D

Operates at 3.3 V

D

Packaged in Plastic Small-Outline Package

CC

description

The CDC9842 is a high-performance clock synthesizer/driver that generates the system clocks necessary to
support Pentium/82430X/82430VX and PentiumPro 82440FX chipsets. Four host-clock outputs (HCLKn) are
programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs.
Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to 4 ns from
the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz (SBCLK) and
three 14.318-MHz reference clock outputs (REF0, REF1, REF2) are provided.

All output frequencies are generated from a 14.318-MHZ crystal input. A reference clock can be provided at the
X1 input instead of a crystal input.

Two phase-locked loops (PLLs) are used to generate the host clock frequency and the 48-MHz clock frequency .
On-chip loop filters and internal feedback eliminate the need for external components. The PCI-clock
frequency is derived directly from the host-clock frequency . The PLL circuit can be bypassed in the TEST mode
(i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input.

The host- and PCI-clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs
are 3 state and are enabled via OE.

Because the CDC9842 is based on PLL circuitry , it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal
at the X1 input, as well as following any changes to the OE or SELn inputs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Pentium is a trademark of Intel Corporation.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1996, Texas Instruments Incorporated

1

CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS

SCAS546B – NOVEMBER 1995 – REVISED MA Y 1996

FUNCTION TABLE

OE

L X X 14.318 MHz Hi-Z Hi-Z Hi-Z Hi-Z
H L L 14.318 MHz 50 MHz 25 MHz 14.318 MHz 48 MHz
H L H 14.318 MHz 60 MHz 30 MHz 14.318 MHz 48 MHz
H H L 14.318 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz
H H H TCLK

†

TCLK is a test-clock input at the X1 input during test mode.

SEL0 SEL1 X1 HCLKn PCLKn REFn SBCLK

†

TCLK/2 TCLK/4 TCLK TCLK/4

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

5

OE

CDC9842

PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER

WITH 3-STATE OUTPUTS

SCAS546B – NOVEMBER 1995 – REVISED MA Y 1996

X2

X1

3

OSC

2

÷2

48-MHz

PLL

CPU CLK

PLL

÷2

28

27

25

24

10

6

7

9

REF0

REF1

REF2

SBCLK

HCLK0

HCLK1

HCLK2

HCLK3

SEL0

SEL1

13

12

Select

Logic

÷2

16

18

19

21

22

15

PCLK5

PCLK4

PCLK3

PCLK2

PCLK1

PCLK0

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3