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CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MA Y 1996
D
Provides System Clock Solution for
Pentium/82430X/82430VX and
DW PACKAGE
(TOP VIEW)
PentiumPro 82440FX Chipsets
1
D
Four Host-Clock Outputs With
Programmable Frequency (50 MHz, 60 MHz
and 66 MHz)
D
Six PCI Clock Outputs at Half-CPU
Frequency
D
One 48-MHz Universal Serial Bus (USB)
Clock Output
D
Three 14.318-MHz Reference Clock Outputs
D
All Output Clock Frequencies Derived From
a Single 14.31818-MHz Crystal Input
D
LVTTL-Compatible Inputs and Outputs
D
Internal Loop Filters for Phase-Locked
Loops Eliminate the Need for External
V
CC
X1
X2
GND
OE
HCLK0
HCLK1
V
CC
HCLK2
HCLK3
GND
SEL1
SEL0
V
CC
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REF0
REF1
V
CC
REF2
SBCLK
GND
PCLK0
PCLK1
V
CC
PCLK2
PCLK3
GND
PCLK4
PCLK5
Components
D
Operates at 3.3 V
D
Packaged in Plastic Small-Outline Package
CC
description
The CDC9842 is a high-performance clock synthesizer/driver that generates the system clocks necessary to
support Pentium/82430X/82430VX and PentiumPro 82440FX chipsets. Four host-clock outputs (HCLKn) are
programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs.
Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to 4 ns from
the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz (SBCLK) and
three 14.318-MHz reference clock outputs (REF0, REF1, REF2) are provided.
All output frequencies are generated from a 14.318-MHZ crystal input. A reference clock can be provided at the
X1 input instead of a crystal input.
Two phase-locked loops (PLLs) are used to generate the host clock frequency and the 48-MHz clock frequency .
On-chip loop filters and internal feedback eliminate the need for external components. The PCI-clock
frequency is derived directly from the host-clock frequency . The PLL circuit can be bypassed in the TEST mode
(i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input.
The host- and PCI-clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs
are 3 state and are enabled via OE.
Because the CDC9842 is based on PLL circuitry , it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal
at the X1 input, as well as following any changes to the OE or SELn inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Pentium is a trademark of Intel Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MA Y 1996
FUNCTION TABLE
OE
L X X 14.318 MHz Hi-Z Hi-Z Hi-Z Hi-Z
H L L 14.318 MHz 50 MHz 25 MHz 14.318 MHz 48 MHz
H L H 14.318 MHz 60 MHz 30 MHz 14.318 MHz 48 MHz
H H L 14.318 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz
H H H TCLK
†
TCLK is a test-clock input at the X1 input during test mode.
SEL0 SEL1 X1 HCLKn PCLKn REFn SBCLK
†
TCLK/2 TCLK/4 TCLK TCLK/4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
5
OE
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MA Y 1996
X2
X1
3
OSC
2
÷2
48-MHz
PLL
CPU CLK
PLL
÷2
28
27
25
24
10
6
7
9
REF0
REF1
REF2
SBCLK
HCLK0
HCLK1
HCLK2
HCLK3
SEL0
SEL1
13
12
Select
Logic
÷2
16
18
19
21
22
15
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
PCLK0
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CDC9842
PARAMETER
TEST CONDITIONS
UNIT
I
CC
,
O
,
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MA Y 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance state or power-off state,
V
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Current into any output in the low state, IO 16 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Maximum power dissipation at T
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Book
, literature number SCBD002.
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
= 55°C (in still air) (see Note 2) 1.2 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS T echnology Data
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
T
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 3.135 3.6 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –8 mA
Low-level output current 8 mA
Operating free-air temperature 0 70 °C
CC
V
†
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
MIN TYP‡MAX
V
IK
V
OH
V
OL
I
I
I
OZ
CC
C
i
C
‡
All typical values are at VCC = 3.3 V.
§
Device in normal operating mode with no load on outputs
o
VCC = 3.135 V, II = –18 mA –1.2 V
VCC = 3.135 V, IOH = –8 mA 2.5 V
VCC = 3.135 V, IOL = 8 mA 0.4 V
VCC = 3.6 V, VI = VCC or GND ±1 µA
VCC = 3.6 V, VO = VCC or GND µA
V
= 3.6 V, I
VI = VCC or GND
VI = VCC or GND 6 pF
VO = VCC or GND 6 pF
= 0,
Outputs enabled
Outputs disabled 1 mA
§
50 mA
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
()
()
t
‡
Jitt
‡
‡
t
‡§
2
ns
t
‡§
2
ns
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MA Y 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
After SEL1, SEL0 5
Stabilization time
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and
skew parameters given in the switching characteristics table are not applicable.
†
After OE↑
After power up 5
switching characteristics (see Figures 1 and 2)
VCC = 3.135 V
PARAMETER
skew
‡
Offset
er
Duty cycle Any output 45% 55%
t
c
r
f
‡
Specifications are applicable only after the PLL stabilization time has elapsed.
§
Rise and fall times are characterized using the load circuits shown in Figure 1.
FROM
(INPUT)
HCLKn PCLKn
HCKLn
PCLKn
TO
(OUTPUT)
HCLKn
PCLKn
HCKLn ±250 ps
PCLKn ±350 ps
SEL0 = L, SEL1 = L 20 ns
SEL0 = L, SEL1 = H 16.7 ns
SEL0 = H, SEL1 = L 15 ns
SEL0 = L, SEL1 = L 40 ns
SEL0 = L, SEL1 = H 33.3 ns
SEL0 = H, SEL1 = L 30 ns
HCLKn
PCKLn
HCKLn
PCLKn
to 3.6 V,
TA = 0°C to 70°C
MIN MAX
200 ps
400 ps
1 4 ns
ms
5
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
CDC9842
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS546B – NOVEMBER 1995 – REVISED MA Y 1996
PARAMETER MEASUREMENT INFORMATION
CLOCK DRIVER CIRCUITS
From Output
Under Test
CL = 20 pF
(see Note A)
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,tf ≤2.5 ns.
C. The outputs are measured one at a time with one transition per measurement.
500 Ω
Figure 1. Load Circuit and Voltage Waveforms
CPU Clock
(HCLK)
CPU Clock
(HCLK)
skew
2.4 V
1.5 V
0.4 V
t
r
HCLK-to-HCLK Skew
t
c
Duty Cycle
t
f
VOLTAGE WAVEFORMS
V
OH
1.5 V
GND
1.5 V
V
OH
GND
PCI Clock
(PCLK)
CPU Clock
(HCLK)
PCI Clock
(PCLK)
skew
PCLK-to-PCLK Skew
PCI Clock
(PCLK)
Offset
HCLK-to-PCLK Offset
Figure 2. Waveforms for Calculation of t
1.5 V
1.5 V
Offset
skew
1.5 V
1.5 V
and Offset
V
OH
GND
V
OH
GND
V
OH
GND
V
OH
GND
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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