The CDC930 is a differential clock synthesizer/
driver that generates HCLK/HCLK, 3VMREF/
3VMREF, PCI, 3V66, 3V48, REF system clock
signals to support a computer system with a
Pentium4 microprocessor and a Direct
Rambus memory subsystem.
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided
at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the host frequencies
and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external
components. The host, PCI clock and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable
clock operation. All outputs have 3-state capability , which can be selected using control inputs SEL133, SelA
and SelB.
The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. When PWRDWN
high, the device operates in normal mode. When PWRDWN is set low, the device transitions to a power-down
mode in which HCLK is driven at 2×I
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
This is system design dependant.
Intel and Pentium4 are trademarks of Intel Corporation.
Rambus is a trademark of Rambus Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
, HCLK is not driven, and all others are set low.
REF
Copyright 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
is set to
1
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JUL Y 2000
description (continued)
The HOST bus operates at 100 MHz or 133 MHz. The MREF bus operates at 50 MHz or 66 MHz. Output
frequency selection is accomplished with corresponding setting for SEL100/133 control input. The PCI bus
frequency is fixed to 33 MHz.
Since the CDC930 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up as well as changes to SEL inputs. With use of external
reference clock, this signal must be fixed-frequency and fixed-phase prior stabilization time starts.
functional block diagram
3-State/Low
SEL100/133
SELA
SELB
23
25
26
Control
Logic
2
Latched
Test
SEL 100
/133
2*REF
14.318 MHz
(2,3)
XIN
XOUT
SPREAD
PWRDWN
MultSel0
MultSel1
I_REF
5
6
52
28
2
3
39
Xtal
Oscillator
Latched
Spread
Logic
48 MHz
PLL
CPU
PLL
2
/3
/2
/2
/2
Sync Logic and Power Down Logic
180°
Phase
Shift
2*3V48
48 MHz
(25,26)
10*PCI
33 MHz
(8,9,11,12,14,
15,17,18,20,21)
4*3V66
66 MHz
(30,31,34,35)
1*3VMREF
50/66 MHz
(55)
1*3VMREF
50/66 MHz
(54)
4*HCLK
100/133 MHz
(42,45,48,51)
4*HCLK
100/133 MHz
(41,44,47,50)
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I/O
DESCRIPTION
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JUL Y 2000
Terminal Functions
TERMINAL
NAMENO.
3V48(0)/SelA25I/ODual function 3.3 V , Type 3, 48-MHz clock output that latches the state of SelA during power up
3V48(1)/SelB26I/ODual function 3.3 V , Type 3, 48-MHz clock output that latches the state of SelB during power up
3V66[0–3]30, 31, 34, 35O3.3 V, Type 5, 66-MHz clock outputs
3VMREF55O3.3 V, Type 5, 50/66-MHz memory clock output
3VMREF54O3.3 V, Type 5, 50/66-MHz memory clock output (180° out of phase with 3VMREF)
GND1, 7, 13, 19,
24, 32, 33, 37,
40, 46, 53
HCLK[1–4]42, 45, 48, 51OType X1, host clock outputs
HCLK[1–4]41, 44, 47, 50OType X1, host complementary clock outputs
I_REF39Special Current reference pin for the host clock pairs. I_REF uses a fixed precision resistor tied to ground
PCI[0–9]8, 9, 11, 12,
14, 15, 17, 18,
20, 21
PWRDWN28IPower down for complete device with HOST at 2×I
REF0/MultSel02I/ODual function 3.3 V, Type 3, 14.318-MHz reference clock output. The state of MultSel0 is latched
REF1/MultSel13I/ODual function 3.3 V, Type 3, 14.318-MHz reference clock output. The state of MultSel1 is latched
SEL100/13323IActive low LVTTL level logic select. SEL100/133 is used for enabling 100/133 MHz. Low=100
SPREAD52ILVTTL level logic select. SPREAD pin enables/disables the spread spectrum for the
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for the through-hole packages,
which use a trace length of zero. The absolute maximum power dissipation allowed at TA = 55°C (in still air) is 1.3 W.
3. The maximum package power dissipation is calculated using a junction temperature of 1505C and a board trace length of 750 mils.
For more information, refer to the
Book
, literature number SCBD002.
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS T echnology Data
OL
DISSIPATION RATING TABLE
T
≤ 25°CDERATING FACTOR
POWER RATINGABOVE TA = 25°C
DL1558.6 mW12.468 mW/°C997.5 mW810.52 mW
‡
This is the inverse of the traditional junction-to-case thermal resistance (R
at 74°C/W.
T
= 70°CT
POWER RATING
) and uses a board-mounted device
θJA
= 85°C
POWER RATING
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
CDC930
High-level output current, I
mA
Low-level output current, I
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JUL Y 2000
recommended operating conditions (see Note 2)
MINNOM
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Input voltage, V
Reference frequency, f
Crystal frequency, f
Operating free-air temperature, T
†
All nominal values are measured at their respective nominal VDD values.
‡
Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven
externally up to f
§
This is a series fundamental crystal with fO = 14.31818 MHz.
NOTES: 4. Unused inputs must be held high or low to prevent them from floating.
DD
IH
IL
I
p
p
(XIN)
5. VIH, VIL: All input levels referenced to VDD = 3.30 V.
OH
OL
‡
(XIN)
§
(XTAL)
A
= 16 MHz. If XIN is driven externally, XOUT is floating.
HCLK/HCLK–20
3VMREF/3VMREF–15
48MHz, REFx–16
PCIx, 3V66x–15
HCLK/HCLK5µA
3VMREF/3VMREF10
48MHz, REFx10
PCIx, 3V66x10
Test mode14MHz
Normal mode13.814.31814.8MHz
3.1353.465V
2
GND –
0.3 V
0V
085°C
†
VDD +
MAXUNIT
0.3 V
0.8V
DD
V
V
mA
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IILLow-level input current
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JUL Y 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETERTEST CONDITIONSMIN TYP†MAXUNIT
V
IK
R
I
I
IH
I
OZ
I
DD(Z)
I
DD(PD)
I
DD
C
I
C
(XTAL)
†
All typical values are measured at their respective nominal VDD values.
‡
These parameters are ensured by design and lab characterization, not 100% production tested.
Control SELx, PWRDWN
CL = MAX = 5 pF, Rs = 33.2 Ω, Rp = 49.9 Ω at HCLK/HCLK
CL = MAX = 20 pF, RL = 500 Ω at 48 MHz, REF (Type 3)
CL = MAX = 30 pF, RL = 500 Ω at PCIx, 3V66, 3VMREF, 3VMREF
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JUL Y 2000
switching characteristics, VDD = MIN to MAX, TA = 0°C to 85°C
PARAMETER
v
v
v
v
t
PZL
t
PZH
t
PHZ
t
PLZ
t
PZL
t
PZH
t
PHZ
t
PLZ
t
stab
†
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for
phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present a XIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the
time from when VDD achieves its nominal operating level until the output frequency is stable and operating within specification.
‡
These parameters are ensured by design and lab characterization, not 100% production tested.
Overshoot
over
Undershoot
under
Overshoot
over
Undershoot
under
Output enable time to low
level
Output enable time to high
level
Output disable time from
high level
Output disable time from low
level
Output enable time to low
level
Output enable time to high
level
Output disable time from
high level
Output disable time from low
level
Stabilization time
‡
‡
‡
‡
†
FROM
(INPUT)TO(OUTPUT)
HCLK/
HCLK
REF, 3V48
3VMREF,
3VMREF,
3V66, PCI
TEST CONDITIONSMINTYPMAXUNIT
HCLK/HCLK 0.7 V amplitude
Other clocks, C
case
f
= 100 or 133 MHz,
(HCL)
SELA, SELB = H,
SEL100/133 L → H,
R
= 475 Ω
ref
f
= 100 or 133 MHz,
(HCL)
SELA, SELB = H,
SEL100/133 H → L,
R
= 475 Ω
ref
f
= 100 or 133 MHz,
(HCL)
SELA, SELB = H,
SEL100/133 L → H,
R
= 475 Ω
ref
f
= 100 or 133 MHz,
(HCL)
SELA, SELB = H,
SEL100/133 H → L,
R
= 475 Ω
ref
After power up3ms
= Worst
GND–0.7
VOH+200
VOL–200
VDD+0.7
100ns
100ns
10ns
10ns
10ns
10ns
10ns
10ns
HCLK/HCLK (Type X1) CL = 2 pF, RL > 500 kΩ
PARAMETER
c
t
jit(cc)
t
dc
t
sk(o)
t
r
t
f
tr, t
v
†
The average over any 1–µs period of time is greater than the minimum specified period.
‡
These parameters are ensured by design and lab characterization, not 100% production tested.
Cycle to cycle jitterf
Duty cycle
HCLK bus skewHCLKxHCLKx
Rise time‡
Fall time‡
Rise and fall time matching
f
Cross point voltages
cross
perio
‡
FROM
(INPUT)TO(OUTPUT)
0.7 V
p
‡
0.7 V
amplitude
TEST CONDITIONSMINTYPMAXUNIT
f
= 100 MHz1010.2
(HCLK)
f
= 133 MHz7.57.65
(HCLK)
= 100 or 133 MHz200ps
(HCLK
f
= 100 or 133 MHz crossing
(HCLK)
point
f
= 100 or 133 MHz crossing
(HCLK)
point
f
= 100 MHz4.41
(HCLK
f
= 133 MHz3.29
(HCLK
VO = 0.14 V to 0.56 V175700ps
VO = 0.14 V to 0.56 V175700ps
2 × (tr – tf)/(tr + tf)20%
f
= 100 or 133 MHz
(HCLK)
HCLK and HCLK
45%55%
150ps
40%
VOH
55%
VOH
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
CDC930
t
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JUL Y 2000
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued)
3VMREF/3VMREF (Type 5) CL = 30 pF, RL = 500 Ω
PARAMETER
c
t
jit(cc)
t
dc
t
sk(o)
t
(off)
t
r
t
f
†
The average over any 1–µs period of time is greater than the minimum specified period.
3VMREF/3VMREF clock
†
period
Cycle to cycle jitter
Duty cyclef
3VMREF/3VMREF output
skew
3VMREF/3VMREF clock
to PCI offset
Rise timeVO = 0.4 V to 2.4 V0.52ns
Fall timeVO = 0.4 V to 2.4 V0.52ns
FROM
(INPUT)TO(OUTPUT)
3VMREF/
3VMREF
3VMREF/
3VMREF
3VMREF/
3VMREF
PCIx
TEST CONDITIONSMINTYPMAXUNIT
f
(3VMREF/3VMREF
f
(3VMREF/3VMREF)
f
(3VMREF/3VMREF
f
= 100 or 133 MHz,
(HCLK)
VDD = 3.3 V, Measured at 1.5 V
(3VMREF/3VMREF)
f
(3VMREF/3VMREF)
f
= 100 or 133 MHz,
(HCLK)
VDD = 3.3 V, Measured at 1.5 V
f
(3VMREF/3VMREF
Measured points at 1.5 V ,
Measured at rising edges
= 50 MHz
)
= 66 MHz1515.3ns
= 66 MHz,
)
= 66 MHz45%55%
= 66 MHz,
= 66 MHz,
)
2020.4ns
250ps
250ps
3ns
3V66 (T ype 5, No SSC), CL = 30 pF, RL = 500 Ω
PARAMETER
t
c
t
jit(cc)
t
dc
t
sk(o)
t
(off)
t
r
t
f
†
The average over any 1–µs period of time is greater than the minimum specified period.
3V66 clock period
Cycle to cycle jitter
Duty cyclef
3V66 output skew3V66x3V66x
3V66 clock to PCI3V66xPCIx
Rise timeVO = 0.4 V to 2.4 V0.52ns
Fall timeVO = 0.4 V to 2.4 V0.52ns
†
FROM
(INPUT)TO(OUTPUT)
TEST CONDITIONSMINTYPMAXUNIT
f
= 66 MHz15.03ns
(3V66)
f
= 66 MHz,
(3V66)
f
= 100 or 133 MHz,
(HCLK)
VDD = 3.3 V, Measured at 1.5 V
= 66 MHz45%55%
(3V66)
f
= 66 MHz,
(3V66)
f
= 100 or 133 MHz,
(HCLK)
VDD = 3.3 V, Measured at 1.5 V
f
= 66 MHz,
(3V66)
Measured points at 1.5 V ,
Measured at rising edges
PCI (Type 5), CL = 30 pF, RL = 500 Ω
PARAMETER
t
c
t
jit(cc)
t
dc
t
sk(o)
t
r
t
f
†
The average over any 1–µs period of time is greater than the minimum specified period.
PCI clock period
Cycle to cycle jitterf
Duty cyclef
PCI output skewPCIxPCIxf
Rise timeVO = 0.4 V to 2.4 V0.52ns
Fall timeVO = 0.4 V to 2.4 V0.52ns
†
FROM
(INPUT)TO(OUTPUT)
TEST CONDITIONSMINTYPMAXUNIT
f
= 33.3 MHz30.06ns
(PCI)
= 100 or 133 MHz500ps
(HCLK)
= 33.3 MHz45%55%
(PCI)
= 33.3 MHz500ps
(PCI)
300ps
250ps
1.53.5ns
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued)
3V48 (Type 3), CL = 20 pF, RL = 500 Ω
PARAMETER
t
c
t
jit(cc)
t
dc
t
sk(o)
t
(off)
t
r
t
f
†
The average over any 1–µs period of time is greater than the minimum specified period.
3V48 clock period
Cycle to cycle jitter
Duty cyclef
3V48 output skew3V48x3V48x
3V48 clock to PCI3V48xPCIx
Rise timeVO = 0.4 V to 2.4 V14ns
Fall timeVO = 0.4 V to 2.4 V14ns
†
REF (Type 3), CL = 20 pF, RL = 500 Ω
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
t
c
t
jit(cc)
t
dc
t
r
t
f
†
The average over any 1–µs period of time is greater than the minimum specified period.
REF clock period
Cycle to cycle jitterf
Duty cyclef
Rise timeVO = 0.4 V to 2.4 V14ns
Fall timeVO = 0.4 V to 2.4 V14ns
†
FROM
(INPUT)TO(OUTPUT)
f
= 14.318 MHz69.84ns
(REF)
= 100 or 133 MHz1ps
(HCLK)
= 14.318 MHz52%62%
(REF)
TEST CONDITIONSMINTYPMAXUNIT
f
= 48 MHz15.03ns
(3V48)
f
= 48 MHz,
(3V48)
f
= 100 or 133 MHz,
(HCLK)
VDD = 3.3 V, Measured at 1.5 V
= 48 MHz45%55%
(3V48)
f
= 48 MHz,
(3V48)
f
= 100 or 133 MHz,
(HCLK)
VDD = 3.3 V, Measured at 1.5 V
f
= 48 MHz,
(3V48)
Measured points at 1.5 V ,
Measured at rising edges
1.53.5ns
CDC930
SCAS641 – JUL Y 2000
350ps
250ps
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JUL Y 2000
PARAMETER MEASUREMENT INFORMATION
Input
Output
From Output
Under Test
C
ref(T)
L
t
PLH
(see Note A)
LOAD CIRCUIT of single-ended outputs for tpd and t
From Output
Under Test
LOAD CIRCUIT of single-ended outputs for tr and t
V
V
ref(IH)
V
ref(T)
V
ref(IL)
t
r
t
w(H)
t
w(L)
RL = 500 Ω
RL = 500 Ω
C
L
(see Note A)
V
ref(T)
t
PHL
V
OH
Test
Point
3 V
0 V
V
t
OL
f
S1
(high-level
enabling)
Waveform 1
S1 at 6 V
(see Note B)
Waveform 2
S1 at GND
(see Note B)
V
ref(O)
GND
sk
Input
f
Output
Enable
Output
Output
OPEN
3 V
0 V
TESTS1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
VOLTAGE WAVEFORMS
V
ref(T)
t
PZL
t
PZH
t
w
V
ref(T)
V
Open
V
ref(OFF)
GND
ref(T)
V
ref(T)
V
ref(IH)
V
ref(T)
V
ref(IL)
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
DD
0 V
≈3 V
V
OL
V
OH
≈0 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. CL = 2 pF (HCLK, HCLK), CL = 20 pF (48MHZ, REF), CL = 30 pF (PCIx, 3VMREF , 3V66).
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 14.318 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JUL Y 2000
PARAMETER MEASUREMENT INFORMATION
PCIx, 3V48x, 3V66x
PCIx, 3V48x, 3V66x
HCLKx
HCLKx
HCLKx
HCLKx
t
sk(o)
t
sk(o
V
T_REF
t
c
V
T_REF
t
(low)
t
(low or high)
t
+
dc
)
tdc=
t
c
t
c
t
W
x 100
t
c
100
t
t
W
(high)
3V66
PCIx
t
[3V66 to PCIx]
(off)
PARAMETER3.3-V INTERFACEUNIT
V
T_REF
Input threshold reference voltage1.5V
Figure 2. Waveforms for Calculation of Output Skew, Duty Cycle, and Offset
VT_
VT_
REF
REF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JUL Y 2000
PARAMETER MEASUREMENT INFORMATION
HCLK
HCLK
V
T_REF
c(n+1)
t
c (n+1)
t
c (n)
t
=t
jit(cc)
VT_REF
t
c(n)
t
=t
jit(cc)
PARAMETER3.3-V INTERFACEUNIT
Input threshold reference voltage1.5V
c(n)–tc(n+1)
c(n)
–t
c(n+1)
t
Figure 3. Waveforms for Calculation of Cycle-Cycle Jitter
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JUL Y 2000
PARAMETER MEASUREMENT INFORMATION
PWRDWN
HOST 100 MHz
HOST
100 MHz
3VMREF
3VMREF
3V66 MHz
PCI 33MHz
0 ns
50 ns150 ns100 ns200 ns
3V48 MHz
REF 14.318 MHz
V
DD
NOTE A: Z
Figure 4. Power DOWN Timing
HCLK
MultSel0
CDC930
MultiSel1
HCLK
R
(TLA)
IREF
= Z
RS1 = 33 Ω
RS1 = 33 Ω
= 475 Ω
(TLB)
RT1 = 49.9 Ω
= 50 Ω, L
(TLA)
= L
RT1 = 49.9 Ω
= 3.5’’, CL represents probe and jig capacitance.
(TLB)
TLA
TLB
CL = 2 pF
Figure 5. Load Circuit for 0.7 V Amplitude HCLK/HCLK Bus
Clock
Clock
CL = 2 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JUL Y 2000
MECHANICAL DATA
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
48-PIN SHOWN
0.025 (0,635)
48
1
0.110 (2,79) MAX
0.012 (0,305)
0.008 (0,203)
25
0.299 (7,59)
0.291 (7,39)
24
A
0.008 (0,20) MIN
0.005 (0,13)
0.420 (10,67)
0.395 (10,03)
Seating Plane
0.004 (0,10)
M
0.006 (0,15) NOM
Gage Plane
0.010 (0,25)
0°–8°
0.040 (1,02)
0.020 (0,51)
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
0.380
(9,65)
0.370
(9,40)
4828
0.630
(16,00)
0.620
(15,75)
56
0.730
(18,54)
0.720
(18,29)
4040048/D 08/97
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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