TEXAS INSTRUMENTS CDC921 Technical data

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CDC921

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS

WITH 3-STATE OUTPUTS

SCAS623 –MA Y 27, 1999

D

Generates Clocks for Pentium III Class
Microprocessors

D

Supports a Single Pentium III
Microprocessor

D

Uses a 14.318 MHz Crystal Input to
Generate Multiple Output Frequencies

D

Includes Spread Spectrum Clocking (SSC),

0.5% Downspread for Reduced EMI
Performance

D

Power Management Control Terminals

D

Low Output Skew and Jitter for Clock
Distribution

D

Operates from Dual 2.5-V and 3.3-V
Supplies

D

Generates the Following Clocks:
– 3 CPU (2.5 V, 100/133 MHz)
– 10 PCI (3.3 V, 33.3 MHz)
– 1 CPU/2 (2.5 V, 50/66 MHz)
– 1 APIC (2.5 V, 16.67 MHz)
– 3 3V66 (3.3 V, 66 MHz)
– 2 REF (3.3 V, 14.318 MHz)
– 1 48MHz (3.3 V, 48 MHz)

D

Packaged in 48-Pin SSOP Package

D

Designed for Use with TI’s Direct Rambus
Clock Generators (CDCR81, CDCR82,
CDCR83)

description

REF0
REF1

3.3V

V

DD

XOUT

GND
PCI0
PCI1

3.3V

V

DD

PCI2
PCI3
PCI4
PCI5
GND
PCI6
PCI7

3.3V

V

DD

PCI8
PCI9

GND
3V66(0)
3V66(1)
3V66(2)

V

3.3V

DD

XIN

DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

GND

48

V

47

APIC

46

GND

45

V

44

CPU_DIV2

43

GND

42

VDD2.5V

41
40

CPU2

39

GND

38

VDD2.5V

37

CPU1

36

CPU0

35

GND

34

V

33

GND

32

PWR_DWN

31

SPREAD

30

SEL1

29

SEL0

28

V

27

48MHz

26

GND

25

SEL133/100

DD

DD

DD

DD

2.5V

2.5V

3.3V

3.3V

The CDC921 is a clock synthesizer/driver that generates CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF
system clock signals to support computer systems with a single Pentium III class microprocessor.

All output frequencies are generated from a 14.318-MHz crystal input. Instead of a crystal, a reference clock
input can be provided at the XIN input. Two phase-locked loops (PLLs) are used to generate the host
frequencies and the 48-MHz clock frequency . On-chip loop filters and internal feedback eliminate the need for
external components.

The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All
outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100

The 48MHz clock can be independently disabled via the control inputs SEL0, SEL1, and SEL133/100
state, the 48-MHz PLL is disabled and the 48MHz clock is driven to high impedance to reduce component jitter.

The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN
terminal, the device operates normally, but when a logical low-level input is applied, the device powers down
completely with the outputs in a low-level output state.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel and Pentium III are trademarks of Intel Corporation.
Direct Rambus and Rambus are trademarks of Rambus Inc.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1999, Texas Instruments Incorporated

.

. In this

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

CDC921
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS

SCAS623 –MA Y 27, 1999

description (continued)

The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding
setting for SEL133/100

Since the CDC921 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.
This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an
external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts.

INPUTS

SEL133/

100

SEL1 SEL0 CPU CPU_DIV2 3V66 PCI 48MHz REF APIC

L L L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 3-state
L L H N/A N/A N/A N/A N/A N/A N/A Reserved
L H L 100 MHz 50 MHz 66 MHz 33 MHz Hi-Z 14.318 MHz 16.67 MHz 48-MHz PLL off
L H H 100 MHz 50 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 48-MHz PLL on

H L L TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK TCLK/16 Test
H L H N/A N/A N/A N/A N/A N/A N/A Reserved

H H L 133 MHz 66 MHz 66 MHz 33 MHz Hi-Z 14.318 MHz 16.67 MHz 48-MHz PLL off
H H H 133 MHz 66 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 48-MHz PLL on

control input. The PCI bus frequency is fixed to 33 MHz.

Function Tables

SELECT FUNCTIONS

OUTPUTS

FUNCTION

ENABLE FUNCTIONS

INPUTS

PWR_DWN CPU CPU_DIV2 APIC 3V66 PCI

L L L L L L L Off Off

H On On On On On On On On

OUTPUT BUFFER SPECIFICATIONS

BUFFER NAME

CPU, CPU_DIV2, APIC 2.375 – 2.625 13.5 – 45 TYPE 1

48MHz, REF 3.135 – 3.465 20 – 60 TYPE 3

PCI, 3V66 3.135 – 3.465 12 – 55 TYPE 5

VDD RANGE

OUTPUTS INTERNAL

(V)

REF,

48MHz

IMPEDANCE

(Ω)

CRYSTAL VCOs

BUFFER TYPE

2

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I/O

DESCRIPTION

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS

WITH 3-STATE OUTPUTS

Terminal Functions

TERMINAL

NAME NO.

3V66 [0–2] 21–23 O 3.3 V, Type 5, 66-MHz clock outputs
48MHz 27 O 3.3 V, Type 3, 48-MHz clock output
APIC 46 O 2.5 V, Type 2, APIC clock output at 16.67 MHz
CPU [0–2] 36, 37, 40 O 2.5 V, Type 1, CPU clock outputs
CPU_DIV2 43 O 2.5 V, Type 1, CPU_DIV2 clock output
GND 6, 14, 20, 26,

PCI [0–9] 7, 8, 10–13,

PWR_DWN 32 I Power down for complete device with outputs forced low
REF0, REF1 1, 2 O 3.3 V, Type 3, 14.318-MHz reference clock outputs
SEL0, SEL1 29, 30 I LVTTL level logic select terminals for function selection
SEL133/100 25 I LVTTL level logic select terminal for enabling 100/133 MHz
SPREAD 31 I Disables SSC function
VDD2.5V 38, 41, 44, 47 Power for CPU, CPU_DIV2, and APIC outputs
VDD3.3V 3, 9, 17, 24,

XIN 4 I Crystal input – 14.318 MHz
XOUT 5 O Crystal output – 14.318 MHz

33, 35, 39, 42,

45, 48

O 3.3 V, Type 5, 33-MHz PCI clock outputs

15, 16, 18, 19

28, 34

Ground for PCI, 3V66, 48MHz, CPU, CPU_DIV2, APIC, REF [0–1] outputs and CORE

Power for the REF, PCI, 3V66, 48MHz outputs and CORE

CDC921

SCAS623 –MA Y 27, 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CDC921
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS

SCAS623 –MA Y 27, 1999

spread spectrum clock (SSC) implementation for CDC921

Simultaneously switching at fixed frequency generates a significant power peak at the selected frequency,
which in turn will cause EMI disturbance to the environment. The purpose of the internal frequency modulation
of the CPU–PLL allows to distribute the energy to many different frequencies which reduces the power peak.
A typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in
Figure 1.

Highest Peak

SSC

δ of f

nom

∆

Non-SSC

f

nom

Figure 1. Frequency Power Spectrum With and Without the Use of SSC

The modulated spectrum has its distribution left hand to the single frequency spectrum which indicates a
“down-spread modulation”.

The peak reduction depends on the modulation scheme and modulation profile. System performance and timing
requirements are the limiting factors for actual design implementations. The implementation was driven to keep
the average clock frequency closed to its upper specification limit. The modulation amount was set to
approximately –0.5%.

In order to allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation
signal is limited in order to minimize SSC induced tracking skew jitter. The ideal modulation profile used for
CDC921 is shown in Figure 2.

10.03

10.02

10.01
10

9.99

9.98

9.97

Period of Output Frequency – ns

51015202530354045

Period of Modulation Signal – µs

Figure 2. SSC Modulation Profile

4

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functional block diagram

CDC921

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS

WITH 3-STATE OUTPUTS

SCAS623 –MA Y 27, 1999

SEL133/100

SEL0

SEL1

XIN

XOUT

SPREAD

25

29

30

4
5

31

Control

Xtal

Oscillator

Logic

Spread

Logic

3-State

48-MHz Inactive

Test

SEL 133/100

CPU

PLL

48 MHz

PLL

/2 /2

/3

/4

/3

/4

2*REF

14.318 MHz
(1,2)

1*48MHz
48 MHz
(27)

3*CPU
100/133 MHz
(36,37,40)

1*CPU_DIV2
50/66 MHz
(43)

10*PCI
33 MHz
(7,8,10,11,12,
13,15,16,18,19)

/2

Sync Logic & Power Down Logic

1*APIC

16.67 MHz
(46)

3*AGP (3V66)
66 MHz
(21,22,23)

PWR_DWN

32

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5

CDC921

†

PACKAGE

A

A

A

Suppl

oltage, V

V

High-level output current, I

mA

Low-level output current, I

mA

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS

SCAS623 –MA Y 27, 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high-impedance state or power-off state,

V

(see Note 1) –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

Current into any output in the low state, I
Input clamp current, I
Output clamp current, I
Operating free-air temperature range, T
Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

DL 1315.7 mW 10.53 mW/°C 842.1 mW 684.2 mW

†

This is the inverse of the traditional junction-to-case thermal resistance (R
at 95°C/W.

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

2 × I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(V

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

POWER RATNG ABOVE TA = 25°C

O

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

T

≤ 25°C DERATING FACTOR

O

–0°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

DISSIPATION RATING TABLE

T

= 70°C T

POWER RATING

) and uses a board-mounted device

θJA

= 85°C

POWER RATING

recommended operating conditions (see Note 2)

MIN NOM

pp

y v

High-level input voltage, V

Low-level input voltage, V
Input voltage, V

Reference frequency, f
Crystal frequency, f
Operating free-air temperature, T

NOTE 2: Unused inputs must be held high or low to prevent them from floating.
†

All nominal values are measured at their respective nominal VDD values.

‡

Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven
externally up to f

§

This is a series fundamental crystal with fO = 14.31818 MHz.

p

p

DD

IH

IL

I

OH

OL

‡

(XTAL)

§

(XTAL)

A

= 130 MHz. If XIN is driven externally, XOUT is floating.

(XTAL)

3.3 V 3.135 3.465

2.5 V 2.375 2.625
2

GND –

0.3 V
0 V

CPUx, CPU_DIV2 –12
APIC –12
48MHz, REFx –14
PCIx, PCI_F, 3V66x –18
CPUx, CPU_DIV2 12
APIC 12
48MHz, REFx 9
PCIx, PCI_F, 3V66x 12
Test mode 130 MHz
Normal mode 13.8 14.318 14.8 MHz

0 85 °C

†

VDD +

MAX UNIT

0.3 V

0.8 V

DD

V

V

†

OL

6

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