TEXAS INSTRUMENTS CDC5806 Technical data
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VIDSEL
REF_IN
PLL1VDD
VIDCLK
PLL1VSS
PLL2VDD
AUDCLK
PLL2VSS
AUDSEL
MCSEL
ASICCLK
PLL3VDD
PLL3VSS
CPUCLK
PLL3VDD
PLL3VSS
USBCLK
PLL3VDD
PLL3VSS
MCCLK
PW PACKAGE
(TOP VIEW)
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THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS
FEATURES DESCRIPTION
• High Performance Clock Generator
• Clock Input Compatible With LVCMOS/LVTTL
• Requires a 54-MHz Input Clock to Generate
Multiple Output Frequencies
• Low Jitter for Clock Distribution
• Generates the Following Clocks:
– VIDCLK 74.175824 MHz/54 MHz
(Buffered)
– AUDCLK 16.9344 MHz/12.288 MHz
– CPUCLK 64 MHz
– ASICCLK 32 MHz
– USBCLK 48 MHz
– MCCLK 38.4 MHz/19.2 MHz/12 MHz
• Operates From Single 3.3-V Supply
• Low Peak-to-Peak Period Jitter (150 ps
Max)
• PLLs Are Powered Down, if No Valid REF_IN
Clock (< 5 MHz) is Detected or the
V
is Below 2 V
DD
• PLL Loop Filter Components Integrated
• Packaged in TSSOP (PW) 20-Pin Package
• Industrial Temperature Range -40°C to
85°C Applications
CDC5806
SCAS760A – MARCH 2004 – REVISED JULY 2004
The CDC5806 is a clock generator which synthesizes
video clocks, audio clocks, CPU clock, ASIC clock,
USB clock, and a memory card clock from a 54-MHz
system clock.
Three phase-locked loops (PLLs) are used to
generate the different frequencies from the system
clock. On-chip loop filters and internal feedback
eliminate the need for external components.
Since the CDC5806 is based on PLL circuitry, it
requires a stabilization time to achieve phase-lock of
the PLLs. The PLL stabilization time begins after the
reference clock input has a stable phase and
frequency.
The device operates from a single 3.3-V supply
voltage. The CDC5806 device is characterized for
operation from -40°C to 85°C.
APPLICATIONS
• Digital Television With a Memory Card
Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
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REF_IN
VIDSEL
AUDSEL
MCSEL
MUX
VIDCLK
AUDCLK
PLL1VSS
PLL1VDD PLL2VDD PLL3VDD
PLL2VSS PLL3VSS
MUX
CPUCLK
ASICCLK
USBCLK
MCCLK
/4
/6
/3
/5
/10
PLL 2
12.288/16.9344 MHz
PLL 3
192 MHz
PLL3VDD
PLL 1
74.175824 MHz
/16
100 kΩ
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
100 kΩ
100 kΩ
100 kΩ
100 kΩ
100 kΩ
Power
Down
Logic
CDC5806
SCAS760A – MARCH 2004 – REVISED JULY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
2
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SCAS760A – MARCH 2004 – REVISED JULY 2004
Terminal Functions
TERMINAL
NAME NO
REF_IN 2 I LVCMOS Reference frequency input
VIDSEL 1 I LVCMOS VIDSEL select input for VIDCLK. It selects between 74.175824 MHz from PLL1 and buffered
AUDSEL 9 I LVCMOS AUDSEL select input for AUDCLK. It selects between 16.9344 MHz and 12.288 MHz from
MCSEL 10 I LVCMOS MCSEL select input for MCCLK. It selects from 38.4 MHz, 19.2 MHz, and 12 MHz from PLL3,
VIDCLK 4 O LVCMOS VIDCLK output 74.175824 MHz or 54 MHz
AUDCLK 7 O LVCMOS AUDCLK output 16.9344 MHz or 12.288 MHz
CPUCLK 17 O LVCMOS CPUCLK output 64 MHz
ASICCLK 20 O LVCMOS ASICCLK output 32 MHz
USBCLK 14 O LVCMOS USBCLK output 48 MHz
MCCLK 4 O LVCMOS MCCLK output 38.4 MHz / 19.2 MHz / 12 MHz
VDD_PLL1 3 Power 3.3-V supply for PLL1 and VIDCLK
VDD_PLL2 6 Power 3.3-V supply for PLL2 and AUDCLK
VDD_PLL3 13, 16, 19 Power 3.3-V supply for PLL3 and CPUCLK, ASICCLK, USBCLK, and MCCLK
VSS_PLL1 5 Ground Ground for PLL1 and VIDCLK
VSS_PLL2 8 Ground Ground for PLL2 and AUDCLK
VSS_PLL3 12, 15, 18 Ground Ground for PLL3 and CPUCLK, ASICCLK, USBCLK, and MCCLK
TYPE DESCRIPTION
input frequency of 54 MHz, 100k||100k pull to mid-level.
PLL2, 100k||100k pull to mid level.
100k||100k pull to mid level.
CDC5806
FUNCTIONAL DESCRIPTION OF THE LOGIC
Table 1. Select Function for Video, Audio, CPU, ASIC, and USB Clocks
VIDSEL AUDSEL VIDCLK AUDCLK CPUCLK ASICCLK USBCLK Unit
L L 54 (buffered) 12.288 64 32 48 MHz
L M Reserved Reserved 64 32 48 MHz
L H 54 (buffered) 16.9344 64 32 48 MHz
M L Reserved Reserved 64 32 48 MHz
M M Reserved Reserved REFCLK/3 REFCLK/6 REFCLK/4 MHz
M H Reserved Reserved 64 32 48 MHz
H L 74.175824 12.288 64 32 48 MHz
H M Reserved Reserved 64 32 48 MHz
H H 74.175824 16.9344 64 32 48 MHz
MCSEL MCCLK MCCLK if VIDSEL = M and AUDSEL = M UNIT
H 12 MHz REFCLK/16 MHz
M 38.4 MHz REFCLK/5 MHz
L 19.2 MHz REFCLK/10 MHz
Table 2. Select Function for MC Clock
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