TEXAS INSTRUMENTS CDC5806 Technical data

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1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

VIDSEL REF_IN

PLL1VDD

VIDCLK

PLL1VSS

PLL2VDD

AUDCLK

PLL2VSS

AUDSEL

MCSEL

ASICCLK PLL3VDD PLL3VSS CPUCLK PLL3VDD PLL3VSS USBCLK PLL3VDD PLL3VSS MCCLK

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THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS

FEATURES DESCRIPTION

• High Performance Clock Generator

• Clock Input Compatible With LVCMOS/LVTTL

• Requires a 54-MHz Input Clock to Generate

Multiple Output Frequencies

• Low Jitter for Clock Distribution

• Generates the Following Clocks:

– VIDCLK 74.175824 MHz/54 MHz

(Buffered) – AUDCLK 16.9344 MHz/12.288 MHz – CPUCLK 64 MHz – ASICCLK 32 MHz – USBCLK 48 MHz – MCCLK 38.4 MHz/19.2 MHz/12 MHz

• Operates From Single 3.3-V Supply

• Low Peak-to-Peak Period Jitter (150 ps

Max)

• PLLs Are Powered Down, if No Valid REF_IN

Clock (< 5 MHz) is Detected or the V

is Below 2 V

• PLL Loop Filter Components Integrated

• Packaged in TSSOP (PW) 20-Pin Package

• Industrial Temperature Range -40°C to

85°C Applications

CDC5806

SCAS760A – MARCH 2004 – REVISED JULY 2004

The CDC5806 is a clock generator which synthesizes video clocks, audio clocks, CPU clock, ASIC clock, USB clock, and a memory card clock from a 54-MHz system clock.

Three phase-locked loops (PLLs) are used to generate the different frequencies from the system clock. On-chip loop filters and internal feedback eliminate the need for external components.

Since the CDC5806 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLLs. The PLL stabilization time begins after the reference clock input has a stable phase and frequency.

The device operates from a single 3.3-V supply voltage. The CDC5806 device is characterized for operation from -40°C to 85°C.

APPLICATIONS

• Digital Television With a Memory Card

Interface

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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REF_IN

VIDSEL

AUDSEL

MCSEL

MUX

VIDCLK

AUDCLK

PLL1VSS

PLL1VDD PLL2VDD PLL3VDD

PLL2VSS PLL3VSS

MUX

CPUCLK

ASICCLK

USBCLK

MCCLK

/10

PLL 2

12.288/16.9344 MHz

PLL 3

192 MHz

PLL3VDD

PLL 1

74.175824 MHz

/16

100 kΩ

LVCMOS

100 kΩ

Power

Down Logic

CDC5806

SCAS760A – MARCH 2004 – REVISED JULY 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

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SCAS760A – MARCH 2004 – REVISED JULY 2004

Terminal Functions

TERMINAL

NAME NO

REF_IN 2 I LVCMOS Reference frequency input VIDSEL 1 I LVCMOS VIDSEL select input for VIDCLK. It selects between 74.175824 MHz from PLL1 and buffered

AUDSEL 9 I LVCMOS AUDSEL select input for AUDCLK. It selects between 16.9344 MHz and 12.288 MHz from

MCSEL 10 I LVCMOS MCSEL select input for MCCLK. It selects from 38.4 MHz, 19.2 MHz, and 12 MHz from PLL3,

VIDCLK 4 O LVCMOS VIDCLK output 74.175824 MHz or 54 MHz AUDCLK 7 O LVCMOS AUDCLK output 16.9344 MHz or 12.288 MHz CPUCLK 17 O LVCMOS CPUCLK output 64 MHz ASICCLK 20 O LVCMOS ASICCLK output 32 MHz USBCLK 14 O LVCMOS USBCLK output 48 MHz MCCLK 4 O LVCMOS MCCLK output 38.4 MHz / 19.2 MHz / 12 MHz VDD_PLL1 3 Power 3.3-V supply for PLL1 and VIDCLK VDD_PLL2 6 Power 3.3-V supply for PLL2 and AUDCLK VDD_PLL3 13, 16, 19 Power 3.3-V supply for PLL3 and CPUCLK, ASICCLK, USBCLK, and MCCLK VSS_PLL1 5 Ground Ground for PLL1 and VIDCLK VSS_PLL2 8 Ground Ground for PLL2 and AUDCLK VSS_PLL3 12, 15, 18 Ground Ground for PLL3 and CPUCLK, ASICCLK, USBCLK, and MCCLK

TYPE DESCRIPTION

input frequency of 54 MHz, 100k||100k pull to mid-level.

PLL2, 100k||100k pull to mid level.

100k||100k pull to mid level.

CDC5806

FUNCTIONAL DESCRIPTION OF THE LOGIC

Table 1. Select Function for Video, Audio, CPU, ASIC, and USB Clocks

VIDSEL AUDSEL VIDCLK AUDCLK CPUCLK ASICCLK USBCLK Unit

L L 54 (buffered) 12.288 64 32 48 MHz L M Reserved Reserved 64 32 48 MHz

L H 54 (buffered) 16.9344 64 32 48 MHz M L Reserved Reserved 64 32 48 MHz M M Reserved Reserved REFCLK/3 REFCLK/6 REFCLK/4 MHz M H Reserved Reserved 64 32 48 MHz H L 74.175824 12.288 64 32 48 MHz H M Reserved Reserved 64 32 48 MHz H H 74.175824 16.9344 64 32 48 MHz

MCSEL MCCLK MCCLK if VIDSEL = M and AUDSEL = M UNIT

H 12 MHz REFCLK/16 MHz

M 38.4 MHz REFCLK/5 MHz

L 19.2 MHz REFCLK/10 MHz

Table 2. Select Function for MC Clock

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CDC5806

SCAS760A – MARCH 2004 – REVISED JULY 2004

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature (unless otherwise noted)

Supply voltage range, V Input voltage range, V Output voltage range, V Input current (VI< 0, VI>V Continuous output current, I Package thermal impedance,Θ Storage temperature range T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51 (no airflow condition) and JEDEC2S1P (high-k board).

(2)

) ±20 mA

(3)

: TSSOP20 package 104 C/W

stg

(1)

0.5 V to 4.6 V

0.5 V to VDD + 0.5 V

±50 mA

65°C to 150°C

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

I thresh

IL(L)

IM(M)

IH(H)

Supply voltage 3 3.3 3.6 V Operating free-air temperature -40 85 °C Low-level input voltage REF_IN 0.3 V Input voltage threshold REF_IN 0.5 V High-level input voltage REF_IN 0.7 V

Three level input low for control inputs 0.13 V Three level input mid for control inputs 0.4 V Three level input high for control inputs 0.87 V

DD DD

High-level output current LVCMOS -8 mA Low-level output current LVCMOS 8 mA Input voltage range LVCMOS 0 3.6 V Output load LVCMOS 5 10 pF

0.6 V

V V V

TIMING REQUIREMENTS

over recommended ranges of supply voltage, load, and operating free-air temperature

PARAMETER MIN NOM MAX UNIT

REF_IN REQUIREMENTS

CLK_IN

tr/ t duty

AUDSEL, VIDSEL, MCSEL REQUIREMENTS

tr/ t t

(1) If VIDSEL and AUDSEL are switched from from one state to another state at the same time, then the CPUCLK, ASICCLK, USBCLK, or

LVCMOS REF_IN clock input frequency 54 MHz Rise and fall time REF_IN signal (20% to 80%) 4 ns

Duty cycle of REF_IN (VDD/2) 40% 60%

REF

Rise and fall time (20% to 80%) 4 ns

Transitional time between AUDSEL and VIDSEL control pins

(1)

6 ns

MCCLK are affected. This is due to the selected reserved mode with VIDSEL = M and AUDSEL = M. This mode causes the PLL3 to be

bypassed and the REFCLK will be seen with the appropriate divider ratios at the correspondent outputs.

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SCAS760A – MARCH 2004 – REVISED JULY 2004

DEVICE CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OVERALL

Supply current Test load 35 45 mA

Standby current fIN= 0 MHz, V

CC(ST)

Supply voltage threshold for power up control circuit 2 V

PUC

LVCMOS

LVCMOS input voltage V

REF_IN input current VI= 0 V or V

SELECT input current VI= 0 V or V

High-level output voltage V

Low-level output voltage V

High-level output current V

Low-level output current V

= 3 V, II= –18 mA –1.2 V

= MIN to MAX, IOH= –5 mA V

= MIN to MAX, IOL= 5 mA 0.4 V

= 3 V, VO= V

= 3.3 V, VO= 1.65 V –35 mA

= 3.6 V, VO= 0.4 V –75

= 3 V, VO= 0.4 V 5

= 3.3 V, VO= 1.65 V 35 mA

= 3.6 V, VO= V

Input capacitance (Ref_IN) 2 pF

Output accuracy VIDCLK, CPUCLK, ASICCLK,

err

USBCLK, MCCLK (38.4 MHz, 19.2 MHz, 12 MHz)

Output accuracy AUDCLK (16.9344 MHz, 12.288 MHz) See Note

err

PLL start up lock time See Figure 2 0.5 ms

PLL lock time after frequency change on AUDCLK See Figure 2 0.5 ms

L(ω)

See Note

odc Duty cycle for MCCLK Threshold = VDD/2 47% 50% 53%

Duty cycle for VIDCLK, AUDCLK, CPUCLK, ASICCLK,

odc Threshold = VDD/2 45% 50% 55%

USBCLK

tr/t

Rise and fall time of the output 20%–80% of V

VIDCLK (74.175824 MHz)

CPUCLK (64 MHz) 60 150 USBCLK (48 MHz) 65 150 MCCLK (38.4 MHz) 65 150

Peak-to-peak period jitter for 10,000 cycles ps

jit(per)

ASICCLK (32 MHz) 60 150 MCCLK (19.2 MHz) 70 150 AUDCLK (16.9344 MHz) 75 150 AUDCLK (12.288 MHz) 85 150 MCCLK (12 MHz) 65 150

(1) This parameter is assured by design as a result of the chosen settings of the internal dividers in the PLL's.

= 3.6 V 1.1 mA

DD DD

– 0.4 V

– 0.4 V –5

– 0.4V 75

(1)

CDC5806

±5 µA

±55 µA

±1 ppm

±40 ppm

2 ns

75 150

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From Output

of DUT

R = 1 kΩ

CL = 10 pF

Time/ms

AUDCLK

/MHz

tL Lock-Up Time

PUC

Time/ms

REF_IN

/MHz

AUDSEL

f = 54 MHz

L(ω)

Lock Time

target

< 1%

target

< 1%

CDC5806

SCAS760A – MARCH 2004 – REVISED JULY 2004

Figure 1. LVCMOS Output Test Load

Figure 2. Timing Diagram of PLL Lock Time of Audio Clock

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

0,30 0,19

4,50 4,30

PINS **

Seating Plane

0,15 0,05

DIM

0,10

6,60 6,20

0,10

0,15 NOM

0°–8°

2016

Gage Plane

0,25

0,75 0,50

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

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TEXAS INSTRUMENTS CDC5806 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual