Texas Instruments CDC536DLR, CDC536DL, CDC536DBR Datasheet

CDC536

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

SCAS378F – APRIL 1994 – REVISED OCTOBER 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Low-Output Skew for Clock-Distribution
and Clock-Generation Applications

D

Operates at 3.3-V V

CC

D

Distributes One Clock Input to Six Outputs

D

One Select Input Configures Three Outputs
to Operate at One-Half or Double the Input
Frequency

D

No External RC Network Required

D

External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input

D

Application for Synchronous DRAM,
High-Speed Microprocessor

D

Negative-Edge-Triggered Clear for
Half-Frequency Outputs

D

TTL-Compatible Inputs and Outputs

D

Outputs Drive 50-Ω Parallel-Terminated
Transmission Lines

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Distributed VCC and Ground Pins Reduce
Switching Noise

D

Packaged in Plastic 28-Pin Shrink Small
Outline Package

description

The CDC536 is a high-performance, low-skew, low-jitter clock driver . It uses a phase-lock loop (PLL) to precisely
align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically
designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to
100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V
V

CC

and is designed to drive a 50-W transmission line.

The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock
(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between
CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL)
input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin
is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the
duty cycle at the input clock.

Output-enable (OE

) is provided for output control. When OE is high, the outputs are in the high-impedance state.

When OE

is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass

the PLL. TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for

the PLL is included on-chip, minimizing component count, board space, and cost.

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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28
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24
23
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20
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17
16
15

AV

CC

AGND
CLKIN

SEL

OE

GND

1Y1

V

CC

GND

1Y2

V

CC

GND

1Y3

V

CC

AV

CC

AGND
FBIN
TEST
CLR
V

CC

2Y1
GND
V

CC

2Y2
GND
V

CC

2Y3
GND

DB OR DL PACKAGE

(TOP VIEW)

CDC536

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

SCAS378F – APRIL 1994 – REVISED OCTOBER 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or
feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST , and upon
enable of all outputs via OE

.

The CDC536 is characterized for operation from 0°C to 70°C.

detailed description of output configurations

The voltage-controlled oscillator (VCO) in the CDC536 has a frequency range of 100 MHz to 200 MHz, twice
the operating frequency range of the CDC536 outputs. The output of the VCO is divided by two and by four to
provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency . The SEL0
and SEL1 inputs determine which of the two signals are buffered to each bank of device outputs.

One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency of this output matches that of the CLKIN signals. In the case that a VCO/2 output is wired to FBIN,
the VCO must operate at twice the CLKIN frequency, resulting in device outputs that operate at the same or
one-half the CLKIN frequency . If a VCO/4 output is wired to FBIN, the device outputs operate at the same or
twice the CLKIN frequency.

output configuration A

Output configuration A is valid when any output configured as a 1× frequency output in Table 1 is fed back to
the FBIN input. The input frequency range for the CLKIN input is 50 MHz to 100 MHz when using output
configuration A. Outputs configured as 1/2× outputs operate at half the CLKIN frequency, while outputs
configured as 1× outputs operate at the same frequency as the CLKIN input.

Table 1. Output Configuration A

INPUTS

OUTPUTS

SEL

1/2×

FREQUENCY1×FREQUENCY

L None All
H 1Yn 2Yn

NOTE: n = 1, 2, 3

output configuration B

Output configuration B is valid when any output configured as a 1× frequency output in Table 2 is fed back to
FBIN. The input frequency range for the CLKIN input is 25 MHz to 50 MHz when using output configuration B.
Outputs configured as 1× outputs operate at the CLKIN frequency, while outputs configured as 2× outputs
operate at double the frequency of the CLKIN input.

Table 2. Output Configuration B

INPUTS

OUTPUTS

SEL

1×

FREQUENCY2×FREQUENCY

L All None
H 1Yn 2Yn

NOTE: n = 1, 2, 3

CDC536

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

SCAS378F – APRIL 1994 – REVISED OCTOBER 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

2Y3

2Y2

2Y1

1Y3

1Y2

1Y1

Phase-Lock Loop

CLR

CLKIN

TEST

SEL

FBIN

OE

B

2

B

2

5

24

26

3

25

4

7

10

13

22

19

16

CDC536

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

SCAS378F – APRIL 1994 – REVISED OCTOBER 1998

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

CLKIN 3 I

Clock input. CLKIN provides the clock signal to be distributed by the CDC536 clock-driver circuit. CLKIN is used
to provide the reference signal to the integrated phase-lock loop that generates the clock output signals. CLKIN
must have a fixed frequency and fixed phase in order for the phase-lock loop to obtain phase lock. Once the
circuit is powered up and a valid CLKIN signal is applied, a stabilization time is required for the phase-lock loop
to phase lock the feedback signal to its reference signal.

CLR 24 I CLR is used for testing purposes only.

FBIN 26 I

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of the
six clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to obtain zero
phase delay between the FBIN and differential CLKIN inputs.

OE 5 I

Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE is
high, all outputs are in the high-impedance state. Since the feedback signal for the phase-lock loop is taken
directly from an output, placing the outputs in the high-impedance state interrupts the feedback loop; therefore,
when a high-to-low transition occurs at OE

, enabling the output buffers, a stabilization time is required before

the phase-lock loop obtains phase lock.

SEL 4 I

Output configuration select. SEL selects the output configuration for each output bank (e.g. 1×, 1/2×, or 2×).
(see Tables 1 and 2).

TEST 25 I

TEST is used to bypass the phase-lock loop circuitry for factory testing of the device. When TEST is low, all
outputs operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses
the PLL circuitry. TEST should be grounded for normal operation.

1Y1–1Y3 7, 10, 13 O

These outputs are configured by SEL to transmit one-half or one-fourth the frequency of the VCO. The
relationship between the CLKIN frequency and the output frequency is dependent on SEL. The duty cycle of
the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal.

2Y1–2Y3 22, 19, 16 O

These outputs transmit one-half the frequency of the VCO. The relationship between the CLKIN frequency and
the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty cycle of the
Y output signals is nominally 50% independent of the duty cycle of the CLKIN signal.