TEXAS INSTRUMENTS CDC516 Technical data

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CDC516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS575A – JULY 1996 – REVISED JANUAR Y 1998

D

Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications

D

Distributes One Clock Input to Four Banks
of Four Outputs

D

Separate Output Enable for Each Output
Bank

D

External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input

D

No External RC Network Required

D

Operates at 3.3-V V

D

Packaged in Plastic 48-Pin Thin Shrink
Small-Outline Package

CC

description

The CDC516 is a high-performance, low-skew,
low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both
frequency and phase, the feedback output
(FBOUT) to the clock (CLK) input signal. It is
specifically designed for use with synchronous
DRAMs. The CDC516 operates at 3.3-V V
is designed to drive up to five clock loads per
output.

Four banks of four outputs provide 16 low-skew,
low-jitter copies of the input clock. Output signal
duty cycles are adjusted to 50 percent,
independent of the duty cycle at the input clock.
Each bank of outputs can be enabled or disabled
separately via the 1G, 2G, 3G, and 4G control
inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the
G inputs are low, the outputs are disabled to the
logic-low state.

CC

and

V

CC

1Y0

1Y1
GND
GND

1Y2

1Y3

V

CC

1G

GND

AV

CC

CLK
AGND
AGND

GND

2G

V

CC

2Y0

2Y1
GND
GND

2Y2

2Y3

V

CC

DGG PACKAGE

(TOP VIEW)

1

48

2

47

3

46

4

45

5

44

6

43

7

42

8

41

9

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

V

CC

4Y0
4Y1
GND
GND
4Y2
4Y3
V

CC

4G
GND
AV

CC

FBIN
AGND
FBOUT
GND
3G
V

CC

3Y0
3Y1
GND
GND
3Y2
3Y3
V

CC

Unlike many products containing PLLs, the CDC516 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC516 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL may be bypassed for test purposes by strapping AV

to ground.

CC

The CDC516 is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

CDC516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS575A – JULY 1996 – REVISED JANUAR Y 1998

FUNCTION TABLE

INPUTS

1G 2G 3G 4G CLK

X X X X L L L L L L
L LLLHLLLL H
L LLHHLLLHH
L LHLHLLHL H
L LHHHLLHHH
L HLLHLHLL H
L HLHHLHLHH
L HHLHLHHL H
L HHHHLHHH H
H LLLHHLLLH
H LLHHHLLH H
H LHLHHLHL H
H LHHHHLHH H
H HLLHHHLL H
H HLHHHHLH H
H HHLHHHHL H
H H H H H H H H H H

OUTPUTS

1Y

(0:3)2Y(0:3)3Y(0:3)4Y(0:3)

FBOUT

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C CDC516DGGR

SMALL OUTLINE

(PW)

2

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functional block diagram

9

1G

16

2G

CDC516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS575A – JULY 1996 – REVISED JANUAR Y 1998

2

1Y0

3

1Y1

6

1Y2

7

1Y3

18

2Y0

19

2Y1

3G

4G

CLK

FBIN

33

40

12

37

PLL

22

23

31

30

27

26

47

46

43

2Y2

2Y3

3Y0

3Y1

3Y2

3Y3

4Y0

4Y1

4Y2

AV

CC

42

35

4Y3

FBOUT

3

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CDC516

TYPE

DESCRIPTION

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS575A – JULY 1996 – REVISED JANUAR Y 1998

Terminal Functions

TERMINAL

NAME NO.

Clock input. CLK provides the clock signal to be distributed by the CDC516 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must

CLK 12 I

FBIN 37 I

1G 9 I

2G 16 I

3G 33 I

4G 40 I

FBOUT 35 O

1Y(0:3) 2, 3, 6, 7 O

2Y(0:3) 18, 19, 22, 26 O

3Y(0:3) 31, 30, 27, 26 O

4Y(0:3) 47, 46, 43, 42 O

AV

CC

AGND 13, 14, 36 Ground Analog ground. AGND provides the ground reference for the analog circuitry.

V

CC

GND

11, 38 Power

1, 8, 17, 24,

25, 32, 41, 48

4, 5, 10, 15,

20, 21, 28, 29,

34, 39, 44, 45

Power Power supply

Ground Ground

have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.

Output bank enable. 1G is the output enable for outputs 1Y(0:3). When 1G is low, outputs 1Y(0:3) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:3) are enabled and switch at the same
frequency as CLK.

Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic-low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.

Output bank enable. 3G is the output enable for outputs 3Y(0:3). When 3G is low, outputs 3Y(0:3) are
disabled to a logic-low state. When 3G is high, all outputs 3Y(0:3) are enabled and switch at the same
frequency as CLK.

Output bank enable. 4G is the output enable for outputs 4Y(0:3). When 4G is low, outputs 4Y(0:3) are
disabled to a logic-low state. When 4G is high, all outputs 4Y(0:3) are enabled and switch at the same
frequency as CLK.

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.

Clock outputs. These outputs provide low-skew copies of CLK. Outputs 1Y(0:3) are enabled via 1G.
These outputs can be disabled to a logic-low state by deasserting the 1G control input.

Clock outputs. These outputs provide low-skew copies of CLK. Outputs 2Y(0:3) are enabled via 2G.
These outputs can be disabled to a logic-low state by deasserting the 2G control input.

Clock outputs. These outputs provide low-skew copies of CLK. Outputs 3Y(0:3) are enabled via 3G.
These outputs can be disabled to a logic-low state by deasserting the 3G control input.

Clock outputs. These outputs provide low-skew copies of CLK. Outputs 4Y(0:3) are enabled via 4G.
These outputs can be disabled to a logic-low state by deasserting the 4G control input.

Analog power supply . A VCC provides the power reference for the analog circuitry. In addition, A V
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, the PLL is
bypassed and CLK is buffered directly to the device outputs.

CC

4

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