TEXAS INSTRUMENTS CDC392 Technical data

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CDC392

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS

SCAS335A – DECEMBER 1992 – REVISED NOVEMBER 1995

GND

1Y2
1Y3

GND

2Y1
2Y2

GND

3Y1

D PACKAGE

(TOP VIEW)

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

1Y1
1T

/C

V

CC

2T/C
A
V

CC

3T/C
OE

D

Low Output Skew for Clock-Distribution
and Clock-Generation Applications

D

TTL-Compatible Inputs and
CMOS-Compatible Outputs

D

Distributes One Clock Input to Six Clock
Outputs

D

Polarity Control Selects True or
Complementary Outputs

D

Distributed VCC and GND Pins Reduce
Switching Noise

D

High-Drive Outputs (–32-mA IOH,
32-mA IOL)

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Packaged In Plastic Small-Outline Package

description

The CDC392 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew
for clock distribution. Through the use of the polarity-control (T/C) inputs, various combinations of true and
complementary outputs can be obtained. The output-enable (OE
high-impedance state.

The CDC392 is characterized for operation from –40°C to 85°C.

) input is provided to disable the outputs to a

FUNCTION TABLE

INPUTS

OE T/C A

H X X Z

L LL L
L LH H
L HL H
L H H L

OUTPUT

Y

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1995, Texas Instruments Incorporated

1

CDC392
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS

SCAS335A – DECEMBER 1992 – REVISED NOVEMBER 1995

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

9

OE

1T/C
2T/C

3T

12

A

15
13
10

/C

EN

N1
N2
N3

1
1
1
2
2
3

logic diagram (positive logic)

9

OE

1T

15

/C

16

1Y1

2

1Y2

3

1Y3

5

2Y1

6

2Y2

8

3Y1

16

1Y1

2

1Y2

2T

3T

3

1Y3

12

A

5

2Y1

13

/C

10

/C

6

2Y2

8

3Y1

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDC392

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS

SCAS335A – DECEMBER 1992 – REVISED NOVEMBER 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state or power-off state, VO –0.5 V to VCC + 0.5 V. . . . . . .

Current into any output in the low state, IO 64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Output clamp current, I

Maximum power dissipation at TA = 55°C (in still air) (see Note 2) 0.77 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils.
For more information, refer to the

Data Book

, literature number SCBD002B.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(V

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

OK

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Package Thermal Considerations

application note in the 1994

ABT Advanced BiCMOS T echnology

recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 5 ns/V
f

clock

T

A

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

Supply voltage 4.75 5 5.25 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –32 mA
Low-level output current 32 mA

Input clock frequency 90 MHz
Operating free-air temperature –40 85 °C

CC

V

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CDC392

V

I

V

CC

GND

A

Any Y

ns

T/C

Any Y

ns

OE

Any Y

ns

OE

Any Y

ns

t

A

ns

1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS

SCAS335A – DECEMBER 1992 – REVISED NOVEMBER 1995

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

V

OH

V

OL

I

I

I

OZ

I

CC

C

i

C

†

All typical values are at VCC = 5 V, TA = 25°C

o

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 and 2)

PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

sk(o)

t

r

t

f

VCC = 4.75 V, II = –18 mA –1.2 V
VCC = 4.75 V, IOH = – 32 mA 3.85 V
VCC = 4.75 V, IOL = 32 mA 0.55 V
VCC = 5.25 V, VI = VCC or GND ±1 µA
VCC = 5.25 V, VO = VCC or GND ±50 µA

VCC = 5.25 V, IO = 0,

=

or

VI = 2.5 V or 0.5 V 3 pF
VO = VCC or GND 7 pF

FROM

(INPUT)

Outputs high 10
Outputs low 40
Outputs disabled 10

TO

(OUTPUT)

Any Y (same phase) 0.6

Any Y (any phase) 2.2

MIN TYP MAX UNIT

2 6.5

1.5 5

1.5 5

1.5 5

1.5 6
3 8

1.5 5

1.5 5

1.4 ns

0.83 ns

mA

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

CL = 50 pF

(see Note A)

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS

SCAS335A – DECEMBER 1992 – REVISED NOVEMBER 1995

PARAMETER MEASUREMENT INFORMATION

2 × V

500 Ω

500 Ω

S1

CC

Open

GND

TEST

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

S1

Open

2 × V

Open

CDC392

CC

LOAD CIRCUIT FOR OUTPUTS

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. The outputs are measured one at a time with one transition per measurement.

1.5 V

70% V

CC

50% V

30% V

CC

t

r

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

CC

1.5 V

t

f

Figure 1. Load Circuit and Voltage Waveforms

t

PHL

70% V

30% V

CC

3 V

0 V

V

CC

V

OH

OL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × VCC

(see Note C)

Output

Waveform 2

S1 at Open

(see Note C)

1.5 V

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

t

PLZ

50% V

t

PHZ

50% V

1.5 V

CC

CC

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

≈ V

V

OL

V

OH

≈ 0 V

CC

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

CDC392
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS

SCAS335A – DECEMBER 1992 – REVISED NOVEMBER 1995

PARAMETER MEASUREMENT INFORMATION

A

1T/C

1Y1

t

PLH1

1Y2

t

PLH2

2T

/C

2Y1

t

PLH3

2Y2

t

PLH4

NOTES: A. Output skew , t

inputs (T

B. Output skew, t

(T

/C) are at the same logic level. It is calculated as the greater of:
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t

/C) are at the same or different logic levels. It is calculated as the greater of:

– The difference between the fastest and slowest of t

or t

PLHn

– The difference between the fastest and slowest of t

or t

PHLn

t

PHL1

t

PHL2

t

PHL3

t

PHL4

from A to any Y (same phase), can be measured only between outputs for which the respective polarity-control

sk(o),

from A↑ to any Y (e.g., t

PLH

from A↓ to any Y (e.g., t

PHL

from A↓ to any Y (e.g., t

PLH

from A↑ to any Y (e.g., t

from A to any Y (any phase), can be measured between outputs for which the respective polarity-control inputs

sk(o),

, n = 5 to 6, and t

, n = 5 to 6, and t

PHLn

PLHn

, n = 7 to 8)

, n = 7 to 8)

PHL

from A↑ to any Y or t

PLH

from A↓ to any Y or t

PHL

Figure 2. Waveforms for Calculation of t

t

PLH5

t

PLH6

t

PHL7

t

PHL8

, n = 1 to 4; or t

PLHn

, n = 1 to 4; or t

PHLn

, n = 7 to 8)

PLHn

, n = 7 to 8)

PHLn

from A↑ to any Y (e.g., t

PHL

from A↓ to any Y (e.g., t

PLH

sk(o)

t

PHL5

t

PHL6

t

PLH7

t

PLH8

PLHn
PHLn

, n = 5 to 6)
, n = 5 to 6)

PLHn

PHLn

, n = 1 to 4;

, n = 1 to 4;

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

30-Mar-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

CDC392D OBSOLETE SOIC D 16 TBD Call TI Call TI

CDC392DR OBSOLETE SOIC D 16 TBD Call TI Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

(2)

Lead/Ball Finish MSL Peak Temp

(3)

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Addendum-Page 1

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