CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
D
Operates at 3.3-V V
CC
D
LVTTL-Compatible Inputs and Outputs
D
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With 3.3-V
VCC)
D
Distributes One Clock Input to Ten Outputs
D
Distributed VCC and Ground Pins Reduce
Switching Noise
D
High-Drive Outputs (–32-mA IOH,
32-mA IOL)
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages
description
The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with
minimum skew for clock distribution. The output-enable (OE
) input disables the outputs to a high-impedance
state. The CDC351 operates at nominal 3.3-V VCC.
The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure
that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended
for customer use and should be connected to GND.
The CDC351 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
A OE
Yn
L H Z
H HZ
L LL
H L H
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC-ΙΙΒ is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
Y10
V
CC
Y9
OE
A
P0
P1
Y8
V
CC
Y7
GND
GND
Y1
V
CC
Y2
GND
Y3
Y4
GND
Y5
V
CC
Y6
GND
DB OR DW PACKAGE
(TOP VIEW)
CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
EN
5
6
A
Y1
23
Y2
21
Y3
19
Y4
18
Y5
16
Y6
14
Y7
11
Y8
9
Y9
4
Y10
2
OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
Y1
Y2
Y3
Y4
Y5
Y6
23
21
19
18
16
14
OE
Y7
Y8
Y9
Y10
11
9
4
2
A
6
5
P0 P1
87
CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state,
VO (see Note 1) –0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO 64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):DB package 0.65 W. . . . . . . . . . . . . . . . .
DW package 1.7 W. . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65 to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS T echnology
Data Book
, literature number SCBD002B.
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 3 3.6 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
I
Input voltage 0 5.5 V
I
OH
High-level output current –32 mA
I
OL
Low-level output current 32 mA
f
clock
Input clock frequency 100 MHz
T
A
Operating free-air temperature 0 70 °C
NOTE 3: Unused pins (input or I/O) must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
IK
VCC = 3 V, II = –18 mA –1.2 V
V
OH
VCC = 3 V, IOH = – 32 mA 2 V
V
OL
VCC = 3 V, IOL = 32 mA 0.5 V
I
I
VCC = 3.6 V, VI = VCC or GND ±1 µA
I
O
‡
VCC = 3.6 V, VO = 2.5 V –15 –150 mA
I
OZ
VCC = 3.6 V, VO = 3 V or 0 ±10 µA
Outputs high 0.3
I
CC
VCC = 3.6 V, IO = 0,
Outputs low 25
mA
V
I
=
V
CC
or
GND
Outputs disabled 0.3
C
i
VI = VCC or GND, VCC = 3.3 V, f = 10 MHz 4 pF
C
o
VO = VCC or GND, VCC = 3.3 V, f = 10 MHz 6 pF
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, CL = 50 pF (see Figures 1 and 2)
PARAMETER
FROM
TO
VCC = 3.3 V,
TA = 25°C
VCC = 3 V to 3.6 V,
TA = 0°C to 70°C
UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX
t
PLH
3.2 3.7 4.2
t
PHL
A
Y
3 3.5 4
ns
t
PZH
1.8 3.8 5.5 1.3 5.9
t
PZL
OE
Y
1.8 3.8 5.5 1.3 5.9
ns
t
PHZ
1.8 3.9 5.9 1.7 6.3
t
PLZ
OE
Y
1.8 4.2 5.9 1.7 6.4
ns
t
sk(o)
A Y 0.3 0.5 0.5 ns
t
sk(p)
A Y 0.2 0.8 0.8 ns
t
sk(pr)
A Y 1 1 ns
t
r
A Y 1.5 ns
t
f
A Y 1.5 ns
switching characteristics temperature and VCC coefficients over recommended operating free-air
temperature and V
CC
range (see Note 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN MAX UNIT
∝t
PLH
(T)
Average temperature coefficient of low to high
propagation delay
A Y 65†ps/10°C
∝t
PHL
(T)
Average temperature coefficient of high to low
propagation delay
A Y 45†ps/10°C
∝t
PLH(VCC
)
Average VCC coefficient of low to high propagation
delay
A
Y –140
‡
ps/
100 mV
∝t
PHL(VCC
)
Average VCC coefficient of high to low propagation
delay
A
Y –120
‡
ps/
100 mV
†
∝t
PLH
(T) and ∝t
PHL
(T) are virtually independent of VCC.
‡
∝t
PLH(VCC
) and ∝t
PHL(VCC
) are virtually independent of temperature.
NOTE 4: These data were extracted from characterization material and are not tested at the factory.
CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500 Ω
500 Ω
TEST
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
S1
Open
6 V
GND
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
3 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
3 V
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V 1.5 V
t
w
Input
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
t
PLH
t
PHL
Output
1.5 V 1.5 V
3 V
0 V
1.5 V
V
OH
V
OL
Input
0.8 V
2 V
t
r
t
f
0.8 V
2 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CDC351
1-LINE TO 10-LINE CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
A
Y1
t
PHL1
t
PLH1
Y2
t
PHL2
t
PLH2
Y8
t
PHL8
t
PLH8
t
PHL3
t
PLH3
Y3
Y4
t
PHL4
t
PLH4
Y5
t
PHL5
t
PLH5
Y6
t
PHL6
t
PLH6
Y7
t
PHL7
t
PLH7
Y9
t
PHL9
t
PLH9
Y10
t
PLH10
t
PHL10
NOTES: A. Output skew, t
sk(o)
, is calculated as the greater of:
– The difference between the fastest and slowest of t
PLHn
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
– The difference between the fastest and slowest of t
PHLn
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
B. Pulse skew, t
sk(p)
, is calculated as the greater of | t
PLHn
– t
PHLn
| (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10).
C. Process skew, t
sk(pr)
, is calculated as the greater of:
– The difference between the fastest and slowest of t
PLHn
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical
operating conditions
– The difference between the fastest and slowest of t
PHLn
(n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical
operating conditions
Figure 2. Waveforms for Calculation of t
sk(o)
, t
sk(p)
, t
sk(pr)
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