TEXAS INSTRUMENTS CDC341 Technical data
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CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998
D
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
D
TTL-Compatible Inputs and Outputs
D
Distributes One Clock Input to Eight
Outputs
D
Distributed VCC and Ground Pins Reduce
Switching Noise
D
High-Drive Outputs (–48-mA IOH,
48-mA I
D
State-of-the-Art
OL
)
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Packaging Options Include Plastic
Small-Outline (DW) Packages
DW PACKAGE
V
CC
1G
2G
A
P0
P1
V
CC
2Y4
2Y3
GND
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V
CC
1Y1
1Y2
GND
1Y3
1Y4
GND
2Y1
2Y2
GND
description
The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs
with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be
placed in a low state regardless of the A input.
The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for
customer use and should be strapped to GND.
The CDC341 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
1G 2G A 1Y1–1Y4 2Y1–2Y4
X X L L L
L LH L L
LHH L H
HLH H L
HHH H H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OUTPUTS
EPIC-ΙΙΒ is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1G
2G
2
3
4
A
G1
G2
1
1
1
1
2
2
2
2
logic diagram (positive logic)
2
1G
3
2G
19
18
16
15
13
12
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
9
2Y3
8
2Y4
19
1Y1
18
1Y2
16
1Y3
15
1Y4
4
A
13
12
2Y1
2Y2
9
2Y3
8
2Y4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
f
Input clock frequenc
MH
CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high state or power-off state,
V
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Current into any output in the low state, I
Input clamp current, I
Maximum power dissipation at T
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Book
, literature number SCBD002.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
= 55°C (in still air) (see Note 2) 1.6 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
O
application note in the
ABT Advanced BiCMOS T echnology Data
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
clock
T
A
NOTE 3: Unused pins (input or I/O) must be held high or low.
Supply voltage 4.75 5.25 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –48 mA
Low-level output current 48 mA
p
Operating free-air temperature 0 70 °C
y
One output bank loaded 80
Both output banks loaded
CC
V
40
†
z
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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