TEXAS INSTRUMENTS CDC341 Technical data

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CDC341

1-LINE TO 8-LINE CLOCK DRIVER

SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998

D

Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications

D

TTL-Compatible Inputs and Outputs

D

Distributes One Clock Input to Eight
Outputs

D

Distributed VCC and Ground Pins Reduce
Switching Noise

D

High-Drive Outputs (–48-mA IOH,
48-mA I

D

State-of-the-Art

OL

)

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Packaging Options Include Plastic
Small-Outline (DW) Packages

DW PACKAGE

V

CC

1G
2G

A
P0
P1

V

CC

2Y4
2Y3

GND

(TOP VIEW)

1

20

2

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

V

CC

1Y1
1Y2
GND
1Y3
1Y4
GND
2Y1
2Y2
GND

description

The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs
with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be
placed in a low state regardless of the A input.

The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for
customer use and should be strapped to GND.

The CDC341 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

1G 2G A 1Y1–1Y4 2Y1–2Y4

X X L L L
L LH L L
LHH L H
HLH H L
HHH H H

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OUTPUTS

EPIC-ΙΙΒ is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

CDC341
1-LINE TO 8-LINE CLOCK DRIVER

SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

1G
2G

2
3

4

A

G1
G2

1
1
1
1

2
2
2
2

logic diagram (positive logic)

2

1G

3

2G

19
18
16
15

13
12

1Y1
1Y2
1Y3
1Y4

2Y1
2Y2

9

2Y3

8

2Y4

19

1Y1

18

1Y2

16

1Y3

15

1Y4

4

A

13

12

2Y1

2Y2

9

2Y3

8

2Y4

2

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f

Input clock frequenc

MH

CDC341

1-LINE TO 8-LINE CLOCK DRIVER

SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high state or power-off state,

V

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

Current into any output in the low state, I
Input clamp current, I
Maximum power dissipation at T
Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the

Book

, literature number SCBD002.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(V

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

= 55°C (in still air) (see Note 2) 1.6 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Package Thermal Considerations

O

application note in the

ABT Advanced BiCMOS T echnology Data

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

clock

T

A

NOTE 3: Unused pins (input or I/O) must be held high or low.

Supply voltage 4.75 5.25 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –48 mA
Low-level output current 48 mA

p

Operating free-air temperature 0 70 °C

y

One output bank loaded 80
Both output banks loaded

CC

V

40

†

z

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3

CDC341

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

I

CC

,

O

,

mA

(INPUT)

(OUTPUT)

A

Y

ns

G

Y

ns

1-LINE TO 8-LINE CLOCK DRIVER

SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C

MIN TYP†MAX

V

IK

V

OH

V

OL

I

I

‡

I

O

CC

C

†

All typical values are at VCC = 5 V.

‡

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

i

switching characteristics, CL = 50 pF (see Figures 1 and 2)

PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

t

sk(o)

t

sk(p)

t

sk(pr)

t

r

t

f

VCC = 4.75 V, II = –18 mA –1.2 –1.2 V
VCC = 4.75 V, IOH = – 3 mA 2.5 2.5
VCC = 5 V, IOH = – 3 mA 3 3
VCC = 4.75 V, IOH = – 48 mA 2 2
VCC = 4.75 V, IOL = 48 mA 0.5 V
VCC = 5.25 V, VI = VCC or GND ±1 ±1 µA
VCC = 5.25 V, VO = 2.5 V –50 –100 –200 –50 –200 mA

V

= 5.25 V, I

VI = VCC or GND
VI = 2.5 V or 0.5 V 3 pF

FROM

A Y

A Y 1.5 ns
A Y 1.5 ns

= 0,

TO

Outputs high 2 3.5
Outputs low 24 33

VCC = 5 V,

TA = 25°C

MIN TYP MAX MIN MAX

3.5 4.5 3.1 4.9

3.5 4.3 3.1 4.9
2 3.8 2 4
2 3.8 2 4

0.3 0.5 0.6

0.6 0.8 0.9

VCC = 4.75 V to 5.25 V,

TA = 0°C to 70°C

1 1

V

UNIT

ns

tpd performance information relative to VCC and temperature variation (see Note 4)

Dt

PLH(TA)

Dt

PHL(TA)

Dt

PLH(VCC)

Dt

PHL(VCC)

†

Virtually independent of V

‡

Virtually independent of temperature

NOTE 4: The data extracted is from a wide range of characterization material.

4

†
†

Temperature drift of t
Temperature drift of t

‡

VCC drift of t

‡§

VCC drift of t

CC

from 0°C to 70°C –41 ps/10°C

PLH

from 0°C to 70°C –52 ps/10°C

PHL

from 4.75 V to 5.25 V 28 ps/100 mV

PLH

from 4.75 V to 5.25 V 20 ps/100 mV

PHL

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CDC341

1-LINE TO 8-LINE CLOCK DRIVER

SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

500 Ω

Input

(see Note B)

t

Output

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.

Figure 1. Load Circuit and Voltage Waveforms

A

1G

2G

1.5 V 1.5 V

PLH

1.5 V

0.8 V 0.8 V

t

r

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

2 V

t

1.5 V

PHL

t

3 V

0 V

V

OH

V

OL

f

1Yn

2Yn

NOTES: A. Output skew, t

– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t

B. Pulse skew, t

C. Process skew, t

– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t

t

PLH1

t

PLH2

, is calculated as the greater of:

sk(o)

, is calculated as the greater of | t

sk(p)

, is calculated as the greater of:

sk(pr)

t

PHL1

t

PHL2

PLHn
PHLn

– t

PLHn

(n = 1, 2) across multiple devices under identical operating conditions

PLHn

(n = 1, 2) across multiple devices under identical operating conditions

PHLn

Figure 2. Waveforms for Calculation of t

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(n = 1, 2)
(n = 1, 2)

| (n = 1, 2).

PHLn

sk(o)

, t

sk(p)

, t

sk(pr)

5

CDC341
1-LINE TO 8-LINE CLOCK DRIVER

SCAS333D – DECEMBER 1992 – REVISED OCTOBER 1998

MECHANICAL INFORMATION

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN

0.050 (1,27)

16

1

0.020 (0,51)

0.014 (0,35)
9

0.299 (7,59)

0.293 (7,45)

8

A

0.010 (0,25)

0.419 (10,65)

0.400 (10,15)

M

0.010 (0,25) NOM

0°–8°

Gage Plane

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

0.104 (2,65) MAX

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013

0.012 (0,30)

0.004 (0,10)

PINS **

DIM

A MAX

A MIN

Seating Plane

0.004 (0,10)

16

0.410

(10,41)

0.400

(10,16)

20

0.510

(12,95)

0.500

(12,70)

24

0.610

(15,49)

0.600

(15,24)

4040000/D 02/98

6

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Copyright  1998, Texas Instruments Incorporated