CDC340
1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B – DECEMBER 1992 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
D
TTL-Compatible Inputs and Outputs
D
Distributes One Clock Input to Eight
Outputs
D
Distributed VCC and Ground Pins Reduce
Switching Noise
D
High-Drive Outputs (–48-mA IOH,
48-mA I
OL
)
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Package Options Include Plastic
Small-Outline (DW) and Shrink
description
The CDC340 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs
with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be
placed in a high state regardless of the A input.
The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for
customer use and should be strapped to GND.
The CDC340 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
1G 2G A 1Y1–1Y4 2Y1–2Y4
X X L H H
L LH H H
L HH H L
H LH L H
H H H L L
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
1G
2G
A
P0
P1
V
CC
2Y4
2Y3
GND
V
CC
1Y1
1Y2
GND
1Y3
1Y4
GND
2Y1
2Y2
GND
DW PACKAGE
(TOP VIEW)
CDC340
1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B – DECEMBER 1992 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
4
A
1Y1
19
1
1Y2
18
1
1Y3
16
1
1Y4
15
1
2Y1
13
2
2Y2
12
2
2Y3
9
2
2Y4
8
2
G1
2
1G
G2
3
2G
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1Y1
19
3
2G
1Y2
18
1Y3
16
1Y4
15
2Y1
13
2Y2
12
2Y3
9
2Y4
8
2
1G
4
A
CDC340
1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B – DECEMBER 1992 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state,
VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):DW package 1.6 W. . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
Application Note in the
ABT Advanced BiCMOS Technology
Data Book
, literature number SCBD002.
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 4.75 5.25 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
I
Input voltage 0 V
CC
V
I
OH
High-level output current –48 mA
I
OL
Low-level output current 48 mA
p
One output back loaded 80
f
clock
Input clock frequenc
y
Both output banks loaded
40
MH
z
T
A
Operating free-air temperature 0 70 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
MIN TYP‡MAX
MIN
MAX
UNIT
V
IK
VCC = 4.75 V , II = –18 mA –1.2 –1.2 V
VCC = 4.75 V , IOH = – 3 mA 2.5 2.5
V
OH
VCC = 5 V, IOH = – 3 mA 3 3
V
VCC = 4.75 V , IOH = – 48 mA 2 2
V
OL
VCC = 4.75 V , IOL = 48 mA 0.5 V
I
I
VCC = 5.25 V , VI = VCC or GND ±1 ±1 µA
I
O
§
VCC = 5.25 V , VO = 2.5 V –50 –100 –200 –50 –200 mA
V
= 5.25 V , I
= 0,
Outputs high 2 3.5
I
CC
CC
,
O
,
VI = VCC or GND
Outputs low 24 33
mA
C
i
VI = 2.5 V or 0.5 V 3 pF
‡
All typical values are at VCC = 5 V.
§
No more than one output should be tested at a time, and the duration of the test should not exceed one second.
CDC340
1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B – DECEMBER 1992 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, CL = 50 pF (see Figure 1 and Figure 2)
PARAMETER
FROM
TO
VCC = 5 V,
TA = 25°C
VCC = 4.75 V to 5.25 V,
TA = 0°C to 70°C
UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX
t
PLH
Propagation delay time, low-to-high level
3.4 4.5 3 4.8
t
PHL
Propagation delay time, high-to-low level
A
Y
3.2 4.3 2.8 4.7
ns
t
PLH
Propagation delay time, low-to-high level
2 3.8 2 4
t
PHL
Propagation delay time, high-to-low level
G
Y
2 3.8 2 4
ns
t
sk(o)
Skew time, output 0.3 0.5 0.6
t
sk(p)
Skew time, pulse
A Y
0.6 0.8 0.9
ns
t
sk(pr)
Skew time, process 1.1 1.1
t
r
Rise time A Y 1.5 ns
t
f
Fall time A Y 1.5 ns
tpd performance information relative to VCC and temperature variation (see Note 4)
PARAMETER ∆ change
∆t
PLH(TA)
†
Temperature drift of t
PLH
from 0°C to 70°C –53 ps/10°C
∆t
PHL(TA)
†
Temperature drift of t
PHL
from 0°C to 70°C –58 ps/10°C
∆t
PLH(VCC)
‡
VCC drift of t
PLH
from 4.75 V to 5.25 V 43 ps/100 mV
∆t
PHL(VCC)
‡
VCC drift of t
PHL
from 4.75 V to 5.25 V –33 ps/100 mV
†
Virtually independent of V
CC
‡
Virtually independent of temperature
NOTE 4: The data extracted is from a wide range of characterization material.
CDC340
1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B – DECEMBER 1992 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
500 Ω
t
PLH
t
PHL
1.5 V 1.5 V
3 V
0 V
1.5 V
1.5 V
V
OH
V
OL
2 V
0.8 V 0.8 V
t
f
t
r
Input
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
A
1G
1Yn
t
PLH1
t
PHL1
2Yn
t
PLH2
t
PHL2
2G
NOTES: A. Output skew, t
sk(o)
, is calculated as the greater of:
– The difference between the fastest and slowest of t
PLHn
(n = 1, 2)
– The difference between the fastest and slowest of t
PHLn
(n = 1, 2)
B. Pulse skew, t
sk(p)
, is calculated as the greater of | t
PLHn
– t
PHLn
| (n = 1, 2).
C. Process skew, t
sk(pr)
, is calculated as the greater of:
– The difference between the fastest and slowest of t
PLHn
(n = 1, 2) across multiple devices under identical operating conditions
– The difference between the fastest and slowest of t
PHLn
(n = 1, 2) across multiple devices under identical operating conditions
Figure 2. Waveforms for Calculation of t
sk(o)
, t
sk(p)
, t
sk(pr)
CDC340
1-LINE TO 8-LINE CLOCK DRIVER
SCAS332B – DECEMBER 1992 – REVISED MA Y 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
4040000/B 03/95
Seating Plane
0.400 (10,15)
0.419 (10,65)
0.104 (2,65) MAX
1
0.012 (0,30)
0.004 (0,10)
A
8
16
0.020 (0,51)
0.014 (0,35)
0.293 (7,45)
0.299 (7,59)
9
0.010 (0,25)
0.050 (1,27)
0.016 (0,40)
(15,24)
(15,49)
PINS **
0.010 (0,25) NOM
A MAX
DIM
A MIN
Gage Plane
20
0.500
(12,70)
(12,95)
0.510
(10,16)
(10,41)
0.400
0.410
16
0.600
24
0.610
(17,78)
28
0.700
(18,03)
0.710
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 1998, Texas Instruments Incorporated
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