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CDC339
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS331 – DECEMBER 1992 – REVISED MARCH 1994
D
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
D
TTL-Compatible Inputs and Outputs
D
Distributes One Clock Input to Eight
Outputs
– Four Same-Frequency Outputs
– Four Half-Frequency Outputs
D
Distributed VCC and Ground Pins Reduce
Switching Noise
D
High-Drive Outputs (–48-mA IOH,
48-mA IOL)
D
State-of-the-Art E
PIC-ΙΙB
BiCMOS Design
DB OR DW PACKAGE
(TOP VIEW)
Y3
GND
Y4
V
CC
OE
CLR
V
CC
Q4
GND
Q3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Y2
GND
Y1
V
CC
CLK
GND
V
CC
Q1
GND
Q2
Significantly Reduces Power Dissipation
D
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages
description
The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring
synchronized output signals at both the primary clock frequency and one-half the primary clock frequency . The
four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch
at one-half the frequency of CLK.
When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the
Q outputs toggle on low-to-high transitions of CLK. T aking CLR low asynchronously resets the Q outputs to the
low level. When OE
is high, the outputs are in the high-impedance state.
The CDC339 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE CLR CLK Y1–Y4 Q1–Q4
H X X Z Z
L LL L L
L LH H L
L HL LQ
L H ↑ H Q
†
The level of the Q outputs before the
indicated steady-state input conditions were
established.
OUTPUTS
†
0
†
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
CDC339
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS331 – DECEMBER 1992 – REVISED MARCH 1994
logic symbol
5
OE
16
CLK
6
CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
†
EN
T
R
18
20
13
11
10
logic diagram (positive logic)
5
OE
18
Y1
Y1
Y2
1
Y3
3
Y4
Q1
Q2
Q3
8
Q4
16
CLK
T
R
CLR
6
20
13
11
Y2
1
Y3
3
Y4
Q1
Q2
10
8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . .
Current into any output in the low state, IO 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):DB package 0.6 W. . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Data Book
, literature number SCBD002B.
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
DW package 1.6 W. . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS T echnology
Q3
Q4
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
I
V
CC
GND
CDC339
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS331 – DECEMBER 1992 – REVISED MARCH 1994
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
f
clock
T
A
NOTE 3: Unused pins (input or I/O) must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
Supply voltage 4.75 5.25 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –48 mA
Low-level output current 48 mA
Input clock frequency 80 MHz
Operating free-air temperature –40 85 °C
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
V
V
I
I
I
I
I
C
C
IK
OH
OL
IH
IL
OZ
O
CC
i
o
‡
VCC = 4.75 V, II = –18 mA –1.2 V
VCC = 4.75 V, IOH = – 48 mA 2 V
VCC = 4.75 V, IOL = 48 mA 0.5 V
VCC = 5.25 V, VI = 2.7 V 50 µA
VCC = 5.25 V, VI = 0.5 V –50 µA
VCC = 5.25 V, VO = 2.7 V or 0.5 V ±50 µA
VCC = 5.25 V, VO = 2.5 V –50 –180 mA
VCC = 5.25 V, IO = 0,
=
or
VI = 2.5 V or 0.5 V 3 pF
VO = 2.5 V or 0.5 V 8 pF
Outputs high 70
Outputs low 85
Outputs disabled 70
CC
V
mA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
f
clock
t
w
t
su
Clock frequency 80 MHz
CLR low 4
Pulse duration
Setup time CLR inactive before CLK↑ 2 ns
Clock duty cycle 40% 60%
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLK low
CLK high 4
4
ns
3
CDC339
CLK
Any Y or Q
ns
OE
Any Y or Q
ns
OE
Any Y or Q
ns
↑
()
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS331 – DECEMBER 1992 – REVISED MARCH 1994
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 and 2)12
PARAMETER
f
max
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
t
r
t
†
All typical values are at VCC = 5 V, TA = 25°C.
f
FROM
(INPUT)
CLR Any Q 4 9 ns
CLK
TO
(OUTPUT)
Y↑ 0.75
Q↑ 0.9
Y↑ and Q↑ 0.9
MIN TYP†MAX UNIT
80 MHz
3 9
3 9
2 7
3 7
2 7
2 7
0.9 ns
0.7 ns
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC339
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS331 – DECEMBER 1992 – REVISED MARCH 1994
PARAMETER MEASUREMENT INFORMATION
su
500 Ω
1.5 V
t
f
500 Ω
t
h
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Timing Input 1.5 V
t
Data Input
Input
t
PLH
Output
0.8 V
t
r
1.5 V 1.5 V
VOLTAGE WAVEFORMS
1.5 V 1.5 V
2 V
2 V
S1
t
PHL
0.8 V
3 V
0 V
V
V
3 V
0 V
3 V
0 V
OH
OL
7 V
GND
Open
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 7 V
(see Note C)
Output
Waveform 2
S1 at Open
(see Note C)
TEST
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
t
PZL
t
PZH
t
PLZ
1.5 V
t
PHZ
1.5 V
S1
Open
7 V
Open
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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VOLTAGE WAVEFORMS
5
CDC339
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS331 – DECEMBER 1992 – REVISED MARCH 1994
PARAMETER MEASUREMENT INFORMATION
CLK
Y1
Y2
Y3
Y4
Q1
Q2
Q3
Q4
NOTES: A. Output skew, t
t
(n = 1, 2, 3, 4) or t
PLHn
B. Output skew, t
t
(n = 5, 6, 7, 8).
PLHn
C. Output skew, t
t
(n = 1, 2, ..., 8).
PLHn
t
PLH1
t
PLH2
t
PLH3
t
PLH4
t
PLH5
t
PLH6
t
PLH7
t
PLH8
, from CLK↑ to Y↑, is calculated as the greater of the difference between the fastest and slowest of
sk(o)
, from CLK↑ to Q↑, is calculated as the greater of the difference between the fastest and slowest of
sk(o)
, from CLK↑ to Y↑ and Q↑, is calculated as the greater of the difference between the fastest and slowest of
sk(o)
(n = 9, 10, 11, 12).
PLHn
t
PLH9
t
PLH10
t
PLH11
t
PLH12
Figure 2. Skew Waveforms and Calculations
6
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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