Texas Instruments CDC337DWR, CDC337DW, CDC337DBLE Datasheet
CDC337
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
D
TTL-Compatible Inputs and
CMOS-Compatible Outputs
D
Distributes One Clock Input to Eight
Outputs
– Four Same-Frequency Outputs
– Four Half-Frequency Outputs
D
Distributed VCC and Ground Pins Reduce
Switching Noise
D
High-Drive Outputs (–48-mA IOH,
48-mA I
OL
)
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Package Options Include Plastic
Small-Outline (DW)
description
The CDC337 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring
synchronized output signals at both the clock frequency and one-half the clock frequency. The four Y outputs
switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the
frequency of CLK.
When the output-enable (OE
) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the
Q outputs toggle on low-to-high transitions at CLK. T aking CLR
low asynchronously resets the Q outputs to the
low level. When OE
is high, the outputs are in the high-impedance state.
The CDC337 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
OE CLR CLK Y1–Y4 Q1–Q4
H X X Z Z
L LL L L
LLH H L
LHL LQ
0
†
LH↑ HQ
0
†
†
The level of the Q outputs before the
indicated steady-state input conditions were
established
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Y3
GND
Y4
V
CC
OE
CLR
V
CC
Q4
GND
Q3
Y2
GND
Y1
V
CC
CLK
GND
V
CC
Q1
GND
Q2
DW PACKAGE
(TOP VIEW)
CDC337
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
logic diagram (positive logic)
EN
5
R
6
16
CLK
Y1
18
Y2
20
Y3
1
Y4
3
Q1
13
Q2
11
Q3
10
Q4
8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
T
CLR
OE
T
Y1
18
Y2
20
Y3
1
Y4
3
Q1
13
Q2
11
Q3
10
Q4
8
R
16
CLK
CLR
OE
5
6
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state,
V
O
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55°C (in still air) (see Note 2) 1.6 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ĕ
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS T echnology
Data Book
, literature number SCBD002B.
CDC337
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 4.75 5.25 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
I
Input voltage 0 V
CC
V
I
OH
High-level output current –48 mA
I
OL
Low-level output current 48 mA
f
clock
Input clock frequency 80 MHz
T
A
Operating free-air temperature –40 85 °C
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC = 4.75 V , II = –18 mA –1.2 V
V
OH
VCC = 4.75 V , IOH = – 32 mA 3.75 V
V
OL
VCC = 4.75 V , IOL = 32 mA 0.55 V
I
IH
VCC = 5.25 V , VI = 2.7 V 50 µA
I
IL
VCC = 5.25 V , VI = 0.5 V –50 µA
I
OZ
VCC = 5.25 V , VO = VCC or GND ±50 µA
Outputs high 70
I
CC
VCC = 5.25 V , VI = VCC or GND, IO = 0
Outputs low 85
mA
Outputs disabled 70
C
i
VI = 2.5 V or 0.5 V 3 pF
C
o
VO = VCC or GND 10 pF
†
All typical values are at VCC = 5 V, TA = 25°C.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
MIN MAX UNIT
f
clock
Clock frequency 80 MHz
CLR low 4
t
w
Pulse duration
CLK low
4
ns
CLK high 4
t
su
Setup time, CLR inactive before CLK↑ 2 ns
Clock duty cycle 40% 60%
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