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CDC337
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998
D
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
DW PACKAGE
(TOP VIEW)
Applications
D
TTL-Compatible Inputs and
CMOS-Compatible Outputs
D
Distributes One Clock Input to Eight
Outputs
– Four Same-Frequency Outputs
– Four Half-Frequency Outputs
D
Distributed VCC and Ground Pins Reduce
Switching Noise
D
High-Drive Outputs (–48-mA IOH,
48-mA I
D
State-of-the-Art
OL
)
EPIC-ΙΙB
BiCMOS Design
Y3
GND
Y4
V
CC
OE
CLR
V
CC
Q4
GND
Q3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Y2
GND
Y1
V
CC
CLK
GND
V
CC
Q1
GND
Q2
Significantly Reduces Power Dissipation
D
Package Options Include Plastic
Small-Outline (DW)
description
The CDC337 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring
synchronized output signals at both the clock frequency and one-half the clock frequency. The four Y outputs
switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the
frequency of CLK.
When the output-enable (OE
Q outputs toggle on low-to-high transitions at CLK. T aking CLR
low level. When OE
is high, the outputs are in the high-impedance state.
) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the
low asynchronously resets the Q outputs to the
The CDC337 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE CLR CLK Y1–Y4 Q1–Q4
H X X Z Z
L LL L L
LLH H L
LHL LQ
LH↑ HQ
†
The level of the Q outputs before the
indicated steady-state input conditions were
established
OUTPUTS
†
0
†
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
CDC337
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998
logic symbol
5
OE
16
CLK
6
CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
†
EN
T
R
18
20
13
11
10
logic diagram (positive logic)
5
OE
18
Y1
Y1
Y2
1
Y3
3
Y4
Q1
Q2
Q3
8
Q4
CLK
CLR
16
6
T
R
20
13
11
Y2
1
Y3
3
Y4
Q1
Q2
10
Q3
8
Q4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high state or power-off state,
V
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Current into any output in the low state, I
Input clamp current, I
Maximum power dissipation at T
Storage temperature range, T
ĕ
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Data Book
, literature number SCBD002B.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
= 55°C (in still air) (see Note 2) 1.6 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
O
application note in the 1994
ABT Advanced BiCMOS T echnology
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC337
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
f
clock
T
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
All typical values are at VCC = 5 V, TA = 25°C.
Supply voltage 4.75 5.25 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –48 mA
Low-level output current 48 mA
Input clock frequency 80 MHz
Operating free-air temperature –40 85 °C
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
V
V
I
I
I
I
C
C
IK
OH
OL
IH
IL
OZ
CC
i
o
VCC = 4.75 V, II = –18 mA –1.2 V
VCC = 4.75 V, IOH = – 32 mA 3.75 V
VCC = 4.75 V, IOL = 32 mA 0.55 V
VCC = 5.25 V, VI = 2.7 V 50 µA
VCC = 5.25 V, VI = 0.5 V –50 µA
VCC = 5.25 V, VO = VCC or GND ±50 µA
Outputs high 70
VCC = 5.25 V, VI = VCC or GND, IO = 0
VI = 2.5 V or 0.5 V 3 pF
VO = VCC or GND 10 pF
Outputs low 85
Outputs disabled 70
CC
V
mA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
MIN MAX UNIT
f
clock
t
w
t
su
Clock frequency 80 MHz
CLR low 4
Pulse duration
Setup time, CLR inactive before CLK↑ 2 ns
Clock duty cycle 40% 60%
CLK low
CLK high 4
4
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CDC337
CLK
Any Y or Q
ns
OE
Any Y or Q
ns
OE
Any Y or Q
ns
↑
()
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
t
r
t
†
All typical values are at VCC = 5 V, TA = 25°C.
NOTE 4: All specifications are valid only for all outputs switching.
f
= 50 pF (unless otherwise noted) (see Note 4 and Figures 1 and 2)
L
FROM
(INPUT)
CLR Any Q 4 10 ns
CLK
TO
(OUTPUT)
Y↑ 0.75
Q↑ 0.9
Y↑ and Q↑ 0.9
MIN TYP†MAX UNIT
80 MHz
4 9
4 9
3 7
3 7
2 7
2 7
ns
0.9 ns
0.7 ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
Timing Input
CL = 50 pF
(see Note A)
SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
500 Ω
500 Ω
LOAD CIRCUIT
1.5 V
S1
3 V
0 V
Open
GND
Input
1.5 V 1.5 V
CLOCK DRIVER
WITH 3-STATE OUTPUTS
TEST
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
w
VOLTAGE WAVEFORMS
S1
Open
2 × V
Open
CC
CDC337
3 V
0 V
50% V
t
t
h
2 V
CC
f
t
su
Data Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
0.8 V
t
r
1.5 V 1.5 V
VOLTAGE WAVEFORMS
1.5 V 1.5 V
2 V
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
0.8 V
3 V
0 V
V
V
3 V
0 V
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note C)
Output
Waveform 2
S1 at Open
(see Note C)
CC
t
PZL
t
PZH
VOLTAGE WAVEFORMS
t
PLZ
50% V
t
PHZ
50% V
CC
CC
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
CDC337
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
CLK
Y1
Y2
Y3
Y4
Q1
Q2
Q3
Q4
NOTES: A. Output skew, t
t
(n = 1, 2, 3, 4) or t
PLHn
B. Output skew, t
t
(n = 5, 6, 7, 8).
PLHn
C. Output skew, t
t
(n = 1, 2, ..., 8).
PLHn
t
PLH1
t
PLH2
t
PLH3
t
PLH4
t
PLH5
t
PLH6
t
PLH7
t
PLH8
, from CLK↑ to Y↑, is calculated as the greater of the difference between the fastest and slowest of
sk(o)
, from CLK↑ to Q↑, is calculated as the greater of the difference between the fastest and slowest of
sk(o)
, from CLK↑ to Y↑ and Q↑, is calculated as the greater of the difference between the fastest and slowest of
sk(o)
(n = 9, 10, 11, 12).
PLHn
Figure 2. Waveforms for Calculation of t
t
PLH9
t
PLH10
t
PLH11
t
PLH12
sk(o)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC337
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998
MECHANICAL INFORMATION
DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
0.050 (1,27)
16
1
0.020 (0,51)
0.014 (0,35)
9
0.299 (7,59)
0.293 (7,45)
8
A
0.010 (0,25)
0.419 (10,65)
0.400 (10,15)
M
0.010 (0,25) NOM
0°–8°
Gage Plane
0.010 (0,25)
0.050 (1,27)
0.016 (0,40)
0.104 (2,65) MAX
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
0.012 (0,30)
0.004 (0,10)
PINS **
DIM
A MAX
A MIN
Seating Plane
0.004 (0,10)
16
0.410
(10,41)
0.400
(10,16)
20
0.510
(12,95)
0.500
(12,70)
24
0.610
(15,49)
0.600
(15,24)
4040000/D 02/98
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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