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CDC330
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS329A – OCTOBER 1993 – REVISED MARCH 1994
• Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
DW PACKAGE
(TOP VIEW)
Applications
• TTL-Compatible Inputs and Outputs
• Two Banks Distribute One Clock Input to
Three Same-Frequency Clock Outputs
• One Bank Distributes One Clock Input to
Four Half-Frequency Clock Outputs
• Internal Power-Up Circuit
• Distributed V
Switching Noise
• Symmetrical Output Drive (–32-mA I
32-mA IOL)
• State-of-the-Art
and Ground Pins Reduce
CC
EPIC-ΙΙB
BiCMOS Design
OH
,
GND
1Y1
1Y2
GND
2Q1
2OE
2A
2Q2
GND
3Y1
3Y2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1OE
1Y3
1A
V
CC
PRE
2Q3
GND
2Q4
V
CC
3OE
3Y3
3A
Significantly Reduces Power Dissipation
• Packaged in Plastic Small-Outline Package
description
The CDC330 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring
output signals at both the primary clock frequency and one-half the primary clock frequency.
This device contains two banks that fan out one input to three same-frequency outputs and one bank that fans
out one input to four half-frequency outputs with minimum skew for clock distribution. Each bank of Y outputs
switch in phase and at the same frequency as its clock (A) input. The four Q outputs switch at one-half the
frequency of their clock (2A) input.
When the output-enable (2OE) input is low and the preset (PRE) input is high, the Q outputs toggle on
high-to-low transitions of 2A. Taking PRE low asynchronously presets the Q outputs to the high level. When a
bank’s OE input is high, the outputs are in the high-impedance state.
The CDC330 is characterized for operation from 0°C to 70°C.
FUNCTION TABLES
INPUTS
nOE nA
H X Z
L LL
L H H
n = 1, 3
INPUTS
2OE PRE 2A
H X X Z
L LL H
L H ↓ Toggle
OUTPUTS
nY1–nY3
OUTPUTS
2Q1–2Q3
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
2–1
CDC330
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS329A – OCTOBER 1993 – REVISED MARCH 1994
logic symbol
22
1A
24
1OE
7
2A
20
PRE
6
2OE
13
3A
15
3OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
†
EN
T
PR
EN
EN
23
17
19
10
11
14
logic diagram (positive logic)
24
2
1Y1
3
1Y2
1Y3
5
2Q1
8
2Q2
2Q3
2Q4
3Y1
3Y2
3Y3
1OE
1A
2OE
2A
PRE
22
6
7
20
2
1Y1
3
1Y2
23
1Y3
5
17
2Q1
8
2Q2
2Q3
T
R
3OE
3A
15
13
19
10
11
14
2Q4
3Y1
3Y2
3Y3
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC330
V
I
V
CC
GND
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS329A – OCTOBER 1993 – REVISED MARCH 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . .
Current into any output in the low state, IO 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) 1.6 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Data Book
, literature number SCBD002B.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS T echnology
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
T
A
NOTE 3: Unused pins (input or I/O) must be held high or low.
Supply voltage 4.75 5.25 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –32 mA
Low-level output current 32 mA
Operating free-air temperature 0 70 °C
CC
V
†
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
V
IK
V
OH
V
OL
I
IH
I
IL
I
OZ
§
I
O
I
CC
C
i
C
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
o
VCC = 4.75 V, II = –18 mA –1.2 V
VCC = 4.75 V, IOH = – 32 mA 2 V
VCC = 4.75 V, IOL = 32 mA 0.5 V
VCC = 5.25 V, VI = 2.7 V 50 µA
VCC = 5.25 V, VI = 0.5 V –50 µA
VCC = 5.25 V, VO = VCC or GND ±50 µA
VCC = 5.25 V, VO = 2.5 V –30 –180 mA
VCC = 5.25 V, IO = 0,
=
or
VI = 2.5 V or 0.5 V 3 pF
VO = 2.5 V or 0.5 V 9 pF
Outputs high 11 40
Outputs low 15 30
Outputs disabled 10 30
mA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–3
CDC330
f
Clock frequenc
f
†
MH
A
A
Any Y or Q
ns
A
OE
Any Y or Q
ns
A
OE
Any Y or Q
ns
t
ns
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS329A – OCTOBER 1993 – REVISED MARCH 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
MIN MAX UNIT
clock
t
w
t
su
Pulse duration
Setup time PRE inactive before 2A↓ 2 ns
y
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figures 1 and 2)
PARAMETER
max
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
sk(o)
t
sk(pr)
†
Duty cycle 40 – 60%
NOTE 4: All specifications are valid only for all outputs switching.
FROM
(INPUT)
1A or 3A Any 1Y or 3Y 67
2A Any Q 100
ny A or
PRE Any Q 12.5 ns
ny
ny
1A
3A
1A or 3A
2A
Any A or A
1A/3A (duty cycle 40 – 60%) 67 MHz
(duty cycle 40 – 60%) 100 MHz
2A
1A/3A low 5.9
1A/3A high 5.9
low 2.8
2A
2A high 4.5
PRE low 3
TO
(OUTPUT)
Any 1Y 0.4
Any 3Y 0.4
Any 1Y or 3Y 0.5
Any Q 0.4
Any Y or Q 1 ns
MIN MAX UNIT
10.5
ns
11
9
8.5
8.5
9
z
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SCAS329A – OCTOBER 1993 – REVISED MARCH 1994
PARAMETER MEASUREMENT INFORMATION
CDC330
CLOCK DRIVER
WITH 3-STATE OUTPUTS
su
500 Ω
1.5 V
t
f
500 Ω
t
h
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Timing Input 1.5 V
t
Data Input
Input
t
PLH
Output
0.8 V
t
r
1.5 V 1.5 V
VOLTAGE WAVEFORMS
1.5 V 1.5 V
2 V
2 V
S1
t
PHL
0.8 V
3 V
0 V
V
V
3 V
0 V
3 V
0 V
OH
OL
7 V
GND
Open
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 7 V
(see Note C)
Output
Waveform 2
S1 at Open
(see Note C)
TEST
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
t
PZL
t
PZH
t
PLZ
1.5 V
t
PHZ
1.5 V
S1
Open
7 V
Open
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VOLTAGE WAVEFORMS
2–5
CDC330
CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS329A – OCTOBER 1993 – REVISED MARCH 1994
PARAMETER MEASUREMENT INFORMATION
nA
nY1
nY2
nY3
2A
2Q1
2Q2
2Q3
2Q4
t
PLH1
t
PLH2
t
PLH3
t
PLH4
t
PLH5
t
PLH6
t
PHL1
t
PHL2
t
PHL3
t
PLH8
t
PLH9
t
PLH10
t
PHL4
t
PHL5
t
PHL6
t
PHL8
t
PHL9
t
PHL10
NOTES: A. Output skew, t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
B. Process skew, t
conditions.
t
PLH7
, is calculated as the greater of:
sk(o)
, is calculated the same as output skew, t
sk(pr)
PLHn
PLHn
PLHn
PHLn
PHLn
PHLn
Figure 2. Waveforms for Calculation of t
t
PHL7
(n = 1, 2, 3)
(n = 4, 5, 6, 7)
(n = 8, 9, 10)
(n = 1, 2, 3)
(n = 4, 5, 6, 7)
(n = 8, 9, 10)
, across multiple CDC330 devices under identical operating
sk(o)
, t
sk(o)
sk(pr)
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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