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CDC329
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCBS117A–D4501, JANUAR Y 1991–REVISED NOVEMBER 1992
GND
1Y2
2Y1
GND
2Y2
3Y
GND
4Y
D PACKAGE
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1Y1
1T
/C
V
CC
2T/C
A
V
CC
3T/C
4T
/C
• Low Output Skew for Clock-Distribution
and Clock-Generation Applications
• State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
• TTL-Compatible Inputs and
CMOS-Compatible Outputs
• Distributes One Clock Input to Six Clock
Outputs
• Polarity Control Selects True or
Complementary Outputs
• Distributed V
and GND Pins Reduce
CC
Switching Noise
• High-Drive Outputs (–15-mA I
OH
,
64-mA IOL)
• Packaged in Plastic Small-Outline Package
description
The CDC329 contains a clock driver circuit that distributes one input signal to six outputs with minimum skew
for clock distribution. Through the use of the polarity control inputs (T/C), various combinations of true and
complementary outputs can be obtained.
The CDC329 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
T/C A
L L L
L HH
H LH
H H L
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
12
A
1T/C
2T
3T/C
4T
15
13
/C
10
9
/C
N1
N2
N3
N4
OUTPUT
Y
1
1
2
2
3
4
16
1Y1
2
1Y2
3
2Y1
5
2Y2
6
3Y
8
4Y
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1992, Texas Instruments Incorporated
1
CDC329
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCBS117A–D4501, JANUAR Y 1991–REVISED NOVEMBER 1992
logic diagram (positive logic)
15
1T/C
13
/C
2T
12
A
10
3T
/C
9
/C
4T
16
1Y1
2
1Y2
3
2Y1
5
2Y2
6
3Y
8
4Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state
or power-off state, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
Input clamp current, I
Output clamp current, I
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Continuous total power dissipation at (or below) 25°C free-air temperature (see Note 2) 1000 mW. . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. For operation above 25°C free-air temperature, derate to 478 mW at 85°C at the rate of 8.7 mW/°C.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 5 ns/V
T
A
NOTE 3: Unused inputs must be held high or low.
Supply voltage 4.75 5 5.25 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –15 mA
Low-level output current 64 mA
Operating free-air temperature –40 85 °C
CC
V
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC329
I
CC
,
O
,
A
Any Y
ns
T/C
Any Y
ns
t
A
ns
A
Any Y
ns
t
A
ns
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCBS117A–D4501, JANUARY 1991–REVISED NOVEMBER 1992
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
V
OH
V
OL
I
I
CC
C
†
All typical values are at VCC = 5 V, TA = 25°C
i
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 and 2)
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
sk(o)
t
r
t
f
VCC = 4.75 V, II = –18 mA –1.2 V
VCC = 4.75 V, IOH = –15 mA 3.85 V
VCC = 4.75 V, IOL = 64 mA 0.55 V
VCC = 5.25 V, VI = VCC or GND ±1 µA
V
= 5.25 V, I
VI = VCC or GND
VI = 2.5 V or 0.5 V 3 pF
FROM
(INPUT)
= 0,
Any Y (same phase) 0.5
Any Y (any phase) 2.5
Outputs high 50 µA
Outputs low 20 30 mA
TO
(OUTPUT)
MIN TYP MAX UNIT
2 6.6
1.7 5.4
1.6 7.4
1.7 6.3
2 ns
1.3 ns
switching characteristics, VCC = 5 V ± 0.25 V, T
PARAMETER
t
PLH
t
PHL
sk(o)
FROM
(INPUT)
= 25°C to 70°C (see Figures 1 and 2)
A
TO
(OUTPUT)
Any Y (same phase) 0.5
Any Y (any phase) 2
MIN MAX UNIT
2.3 5.9
1.7 4.8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CDC329
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCBS117A–D4501, JANUAR Y 1991–REVISED NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
CL = 50 pF
500 Ω
Input
(see Note B)
t
Output
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
1.5 V 1.5 V
PLH
50% V
CC
20% V
CC
t
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
80% V
CC
t
PHL
50% V
20% V
3 V
0 V
V
OH
CC
CC
V
OL
t
f
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC329
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCBS117A–D4501, JANUARY 1991–REVISED NOVEMBER 1992
1T
2T
/C
1Y1
1Y2
/C
2Y1
2Y2
WAVEFORMS FOR CALCULATION OF t
A
t
PLH1
t
PLH2
t
PLH3
t
PLH4
t
PHL1
t
PHL2
t
PHL3
t
PHL4
t
PLH5
t
PLH6
t
PHL7
t
PHL8
sk(o)
t
PHL5
t
PHL6
t
PLH7
t
PLH8
Output skew, t
are at the same logic level. It is calculated as the greater of:
a) the difference between the fastest and slowest of t
(e.g., t
b) the difference between the fastest and slowest of t
(e.g., t
c) the difference between the fastest and slowest of t
(e.g., t
d) the difference between the fastest and slowest of t
(e.g., t
Output skew, t
the same or different logic levels. It is calculated as the greater of:
a) the difference between the fastest and slowest of t
(e.g., t
b) the difference between the fastest and slowest of t
(e.g., t
from A to any Y (same phase), can be measured only between outputs for which the respective polarity control inputs (T/C)
sk(o),
, n = 1 to 4; or t
PLHn
, n = 1 to 4; or t
PHLn
, n = 7 to 8), and
PLHn
, n = 7 to 8).
PHLn
from A to any Y (any phase), can be measured between outputs for which the respective polarity control inputs (T
sk(o),
, n = 1 to 4; or t
PLHn
, n = 1 to 4; or t
PHLn
, n = 5 to 6),
PLHn
, n = 5 to 6),
PHLn
, n = 5 to 6, and t
PLHn
, n = 5 to 6, and t
PHLn
PLH
PHL
PLH
PHL
PLH
PHLn
PHL
PLHn
Figure 2. Skew Waveforms and Calculations
from A↑ to any Y
from A↓ to any Y
from A↓ to any Y
from A↑ to any Y
from A↑ to any Y or t
, n = 7 to 8), and
from A↓ to any Y or t
, n = 7 to 8).
from A↑ to any Y
PHL
from A↓ to any Y
PLH
/C) are at
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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