TEXAS INSTRUMENTS CDC328A Technical data

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CDC328A

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY

SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995

D

Low Output Skew for Clock-Distribution
and Clock-Generation Applications

D

TTL-Compatible Inputs and Outputs

D

Distributes One Clock Input to Six Clock
Outputs

D

Polarity Control Selects True or
Complementary Outputs

D

Distributed VCC and GND Pins Reduce
Switching Noise

D

High-Drive Outputs (–48-mA IOH,

D OR DB PACKAGE

(TOP VIEW)

1Y2
2Y1

2Y2

3Y

4Y

1
2
3
4
5
6
7
8

GND

GND

GND

16
15
14
13
12
11
10

1Y1
1T

/C

V

CC

2T/C
A
V

CC

3T/C

9

4T

/C

48-mA IOL)

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Package Options Include Plastic
Small-Outline (D) and Shrink Small-Outline
(DB) Packages

description

The CDC328A contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew
for clock distribution. Through the use of the polarity-control inputs (T/C), various combinations of true and
complementary outputs can be obtained.

The CDC328A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

T/C A

L L L

L HH
H LH
H H L

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

12

A

15

1T/C
2T
3T
4T/C

13

/C

10

/C

9

N1
N2

N3
N4

OUTPUT

Y

1
1
2
2
3
4

16

1Y1

2

1Y2

3

2Y1

5

2Y2

6

3Y

8

4Y

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1995, Texas Instruments Incorporated

1

CDC328A
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY

SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995

logic diagram (positive logic)

1T

/C

/C

2T

A

3T

/C

/C

4T

15

13

12

10

9

16

1Y1

2

1Y2

3

2Y1

5

2Y2

6

3Y

8

4Y

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state

or power-off state, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the low state, I
Input clamp current, I
Output clamp current, I

(V

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package 0.77 W. . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils.
For more information, refer to the

Data Book

, literature number SCBD002B.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Package Thermal Considerations

96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

DB package 0.6 W. . . . . . . . . . . . . . . . . .

application note in the 1994

ABT Advanced BiCMOS T echnology

†

2

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CDC328A

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY

SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995

recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 5 ns/V
f

clock

T

A

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

Supply voltage 4.75 5 5.25 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –48 mA
Low-level output current 48 mA

Input clock frequency 100 MHz
Operating free-air temperature –40 85 °C

CC

V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CDC328A

I

CC

,

O

,

mA

A

Any Y

ns

T/C

Any Y

ns

t

A

ns

1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY

SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

V

OH

V

OL

I

I

‡

I

O

CC

C

†

All typical values are at VCC = 5 V, TA = 25°C

‡

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

i

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 and 2)

PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

sk(o)

t

sk(p)

t

r

t

f

VCC = 4.75 V, II = –18 mA –1.2 V
VCC = 4.75 V, IOH = –48 mA 2 V
VCC = 4.75 V, IOL = 48 mA 0.5 V
VCC = 5.25 V, VI = VCC or GND ±1 µA
VCC = 5.25 V, VO = 2.5 V –15 –100 mA

V

= 5.25 V, I

VI = VCC or GND
VI = 2.5 V or 0.5 V 3 pF

FROM

(INPUT)

A Any Y 1 ns

= 0,

Outputs high 10
Outputs low 40

TO

(OUTPUT)

Any Y (same phase) 0.5

Any Y (any phase) 1

Any Y 1.5 ns
Any Y 1.5 ns

MIN MAX UNIT

1.7 5

1.5 5

1.5 5

1.4 5

4

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CDC328A

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY

SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

500 Ω

Input

(see Note B)

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.

Figure 1. Load Circuit and Voltage Waveforms

1.5 V 1.5 V

1.5 V

0.8 V 0.8 V

t

r

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

2 V

t

1.5 V

PHL

t

3 V

0 V

V

OH

V

OL

f

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5

CDC328A
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY

SCAS327B – DECEMBER 1992 – REVISED NOVEMBER 1995

PARAMETER MEASUREMENT INFORMATION

A

/C

1T

1Y1

t

PHL1

t

PHL2

t

PHL3

1Y2

2T

2Y1

t

PLH1

t

PLH2

/C

t

PLH3

t

PLH5

t

PLH6

t

PHL7

t

PHL5

t

PHL6

t

PLH7

2Y2

t

PLH4

NOTES: A. Output skew, t

inputs (T

B. Output skew, t

(T

C. Pulse skew, t

/C) are at the same logic level. It is calculated as the greater of:
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t

/C) are at the same or different logic levels. It is calculated as the greater of:
– The difference between the fastest and slowest of t

or t

PLHn

– The difference between the fastest and slowest of t

or t

PHLn

t

PHL4

from A to any Y (same phase), can be measured only between outputs for which the respective polarity-control

sk(o),

from A↑ to any Y (e.g., t

PLH

from A↓ to any Y (e.g., t

PHL

from A↓ to any Y (e.g., t

PLH

from A↑ to any Y (e.g., t

PLHn

PHL

from A↑ to any Y or t

PLH

from A↓ to any Y or t

PHL

- t

(n = 1, 2, 3, 4, 5, 6 ,7, 8).

PHLn

from A to any Y (any phase), can be measured between outputs for which the respective polarity-control inputs

sk(o),

, n = 5 to 6, and t

, n = 5 to 6, and t

, is calculated as the greater of t

sk(p)

PHLn

PLHn

, n = 7 to 8)

, n = 7 to 8)

Figure 2. Waveforms for Calculation of t

t

PHL8

sk(o)

, n = 1 to 4; or t

PLHn

, n = 1 to 4; or t

PHLn

, n = 7 to 8)

PLHn

, n = 7 to 8)

PHLn

from A↑ to any Y (e.g., t

PHL

from A↓ to any Y (e.g., t

PLH

, t

sk(p)

t

PLH8

PLHn
PHLn

, n = 5 to 6)
, n = 5 to 6)

PLHn

PHLn

, n = 1 to 4;

, n = 1 to 4;

6

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