TEXAS INSTRUMENTS CDC328 Technical data

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CDC328

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY

SCBS116B – JANUARY 1991 – REVISED MARCH 1994

• Replaces SN74ABT328

• Low Output Skew for Clock-Distribution

and Clock-Generation Applications

• TTL-Compatible Inputs and Outputs

• Distributes One Clock Input to Six Clock

Outputs

• Polarity Control Selects True or

Complementary Outputs

• Distributed V

Switching Noise

• High-Drive Outputs (–15-mA I

and GND Pins Reduce

CC

OH

,

D OR DB PACKAGE

(TOP VIEW)

GND

GND

GND

1Y2
2Y1

2Y2

3Y

4Y

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

1Y1
1T

/C

V

CC

2T/C
A
V

CC

3T/C
4T

/C

9

64-mA IOL)

• State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

• Package Options Include Plastic

Small-Outline (D) and Shrink Small-Outline
(DB) Packages

description

The CDC328 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew
for clock distribution. Through the use of the polarity-control inputs (T/C), various combinations of true and
complementary outputs can be obtained.

The CDC328 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

T/C A

L L L

L HH
H LH
H H L

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

12

A

15

1T/C
2T

3T/C
4T

13

/C

10
9

/C

N1
N2

N3
N4

OUTPUT

Y

1
1
2
2
3
4

16

1Y1

2

1Y2

3

2Y1

5

2Y2

6

3Y

8

4Y

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1994, Texas Instruments Incorporated

2–1

CDC328
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY

SCBS116B – JANUAR Y 1991 – REVISED MARCH 1994

logic diagram (positive logic)

1T

/C

/C

2T

A

3T

/C

/C

4T

15

13

12

10

9

16

1Y1

2

1Y2

3

2Y1

5

2Y2

6

3Y

8

4Y

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state

or power-off state, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the low state, I
Input clamp current, I
Output clamp current, I

(V

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

Continuous total power dissipation at (or below) 25°C free-air temperature (see Note 2) 1000 mW. . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. For operation above 25°C free-air temperature, derate to 478 mW at 85°C at the rate of 8.7 mW/°C.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 5 ns/V
f

clock

T

A

NOTE 3: Unused inputs must be held high or low.

Supply voltage 4.75 5 5.25 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –15 mA
Low-level output current 64 mA

Input clock frequency 80 MHz
Operating free-air temperature –40 85 °C

CC

V

†

2–2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDC328

I

CC

,

O

,

A

Any Y

ns

T/C

Any Y

ns

t

A

ns

A

Any Y

ns

t

A

ns

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY

SCBS116B – JANUARY 1991 – REVISED MARCH 1994

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

V

OH

V

OL

I

I

‡

I

O

CC

C

†

All typical values are at VCC = 5 V, TA = 25°C

‡

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

i

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 and 2)

PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

sk(o)

t

r

t

f

VCC = 4.75 V, II = –18 mA –1.2 V
VCC = 4.75 V, IOH = –15 mA 2.5 V
VCC = 4.75 V, IOL = 64 mA 0.55 V
VCC = 5.25 V, VI = VCC or GND ±1 µA
VCC = 5.25 V, VO = 2.5 V –15 –100 mA

V

= 5.25 V, I

VI = VCC or GND
VI = 2.5 V or 0.5 V 3 pF

FROM

(INPUT)

= 0,

Any Y (same phase) 0.7

Any Y (any phase) 2.6

Outputs high 50 µA
Outputs low 20 30 mA

TO

(OUTPUT)

MIN TYP MAX UNIT

1.7 7

1.5 5.4

1.5 8

1.4 6.6

1.2 ns

0.5 ns

switching characteristics, VCC = 5 V ± 0.25 V, T

PARAMETER

t

PLH

t

PHL

sk(o)

FROM

(INPUT)

= 25°C to 70°C (see Figures 1 and 2)

A

TO

(OUTPUT)

Any Y (same phase) 0.7

Any Y (any phase) 2.1

MIN MAX UNIT

2.1 6.1

1.7 4.8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2–3

CDC328
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY

SCBS116B – JANUAR Y 1991 – REVISED MARCH 1994

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

500 Ω

Input

(see Note B)

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.

Figure 1. Load Circuit and Voltage Waveforms

1.5 V 1.5 V

1.5 V

0.8 V 0.8 V

t

r

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

2 V

t

1.5 V

PHL

t

3 V

0 V

V

OH

V

OL

f

2–4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1T

2T

/C

1Y1

1Y2

/C

2Y1

CDC328

1-LINE TO 6-LINE CLOCK DRIVER

WITH SELECTABLE POLARITY

SCBS116B – JANUARY 1991 – REVISED MARCH 1994

PARAMETER MEASUREMENT INFORMATION

A

t

PLH1

t

PLH2

t

PLH3

t

PHL1

t

PHL2

t

PHL3

t

PLH5

t

PLH6

t

PHL7

t

PHL5

t

PHL6

t

PLH7

2Y2

t

PLH4

NOTES: A. Output skew, t

inputs (T

B. Output skew, t

(T

/C) are at the same logic level. It is calculated as the greater of:

– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t

/C) are at the same or different logic levels. It is calculated as the greater of:

– The difference between the fastest and slowest of t

or t

PLHn

– The difference between the fastest and slowest of t

or t

PHLn

t

PHL4

from A to any Y (same phase), can be measured only between outputs for which the respective polarity-control

sk(o),

from A↑ to any Y (e.g., t

PLH

from A↓ to any Y (e.g., t

PHL

from A↓ to any Y (e.g., t

PLH

from A↑ to any Y (e.g., t

from A to any Y (any phase), can be measured between outputs for which the respective polarity-control inputs

sk(o),

, n = 5 to 6, and t

, n = 5 to 6, and t

PHLn

PLHn

, n = 7 to 8)

, n = 7 to 8)

PHL

from A↑ to any Y or t

PLH

from A↓ to any Y or t

PHL

Figure 2. Waveforms for Calculation of t

t

PHL8

, n = 1 to 4; or t

PLHn

, n = 1 to 4; or t

PHLn

, n = 7 to 8)

PLHn

, n = 7 to 8)

PHLn

from A↑ to any Y (e.g., t

PHL

from A↓ to any Y (e.g., t

PLH

sk(o)

t

PLH8

PLHn
PHLn

, n = 5 to 6)
, n = 5 to 6)

PLHn

PHLn

, n = 1 to 4;

, n = 1 to 4;

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2–5

CDC328
1-LINE TO 6-LINE CLOCK DRIVER
WITH SELECTABLE POLARITY

SCBS116B – JANUAR Y 1991 – REVISED MARCH 1994

2–6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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Copyright  1998, Texas Instruments Incorporated