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CDC319DBR

Datasheet CDC319DBR Datasheet (Texas Instruments)

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CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
1
D
High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM (Synchronous DRAM) Clock Buffering Applications
D
Output Skew, t
sk(o)
, Less Than 250 ps
D
Pulse Skew, t
sk(p)
, Less Than 500 ps
D
Supports up to Two Unbuffered SDRAM DIMMs (Dual Inline Memory Modules)
D
I2C Serial Interface Provides Individual Enable Control for Each Output
D
Operates at 3.3 V
D
Distributed VCC and Ground Pins Reduce Switching Noise
D
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
D
Packaged in 28-Pin Shrink Small Outline (DB) Package
description
The CDC319 is a high-performance clock buffer that distributes one input (A) to 10 outputs (Y) with minimum skew for clock distribution. The CDC319 operates from a 3.3-V power supply , and is characterized for operation from 0°C to 70°C.
The device provides a standard mode (100K-bits/s) I2C serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs (SDATA and SCLOCK) provide integrated pullup resistors (typically 140 kΩ) and are 5-V tolerant.
Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit is written to the control register. The registers are write only and must be accessed in sequential order (i.e., random access of the registers is not supported).
The CDC319 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state. When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
V
CC
1Y0 1Y1
GND
V
CC
1Y2 1Y3
GND
A
V
CC
3Y0
GND
V
CC
SDATA
V
CC
2Y3 2Y2 GND V
CC
2Y1 2Y0 GND OE V
CC
3Y1 GND GND SCLOCK
DB PACKAGE
(TOP VIEW)
Intel is a trademark of Intel Corporation
CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
2
FUNCTION TABLE
INPUTS
OUTPUTS
OE A 1Y0–1Y3 2Y0–2Y3 3Y0–3Y1
L X Hi-Z Hi-Z Hi-Z H L L L L H H H
†
H
†
H
†
†
The function table assumes that all outputs are enabled via the appropriate I2C configuration register bit. If the output is disabled via the appropriate configuration bit, then the output is driven to a low state, regardless of the state of the A input.
logic diagram (positive logic)
1Y0–1Y3
2Y0–2Y3
3Y0 – 3Y1
OE
SDATA
SCLOCK
A
I2C
Register
Space
I2C
20
14
15
9
2, 3, 6, 7
22, 23, 26, 27
11, 18
10
/
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
1Y0–1Y3 2, 3, 6, 7 O 3.3-V SDRAM byte 0 clock outputs 2Y0–2Y3
22, 23, 26, 27 O 3.3-V SDRAM byte 1 clock outputs
3Y0–3Y1
11, 18 O 3.3-V clock outputs provided for feedback control of external PLLs (phase-locked loops)
A
9 I Clock input
OE
20 I
Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal 140-kΩ pullup resistor is internally integrated.
SCLOCK
15 I I2C serial clock input. A nominal 140-kΩ pullup resistor is internally integrated.
SDATA
14 I/O
Bidirectional I2C serial data input/output. A nominal 140-kΩ pullup resistor is internally integrated.
GND
4, 8, 12, 16,
17, 21, 25
Ground
V
CC
1, 5, 10, 13,
19, 24, 28
3.3-V power supply
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
3
I2C DEVICE ADDRESS
A7
A6 A5 A4 A3 A2 A1 A0 (R/W)
H H L H L L H —
I2C BYTE 0-BIT DEFINITION
†
BIT
DEFINITION DEFAULT VALUE
7 Reserved H 6 Reserved H 5 Reserved H 4 Reserved H 3 1Y3 enable (pin 7) H 2 1Y2 enable (pin 6) H 1 1Y1 enable (pin 3) H 0 1Y0 enable (pin 2) H
†
When the value of the bit is high, the output is enabled. When the value of the bit is low, the output is forced to a low state. The default value of all bits is high.
I2C BYTE 1-BIT DEFINITION
†
BIT
DEFINITION DEFAULT VALUE
7 2Y3 enable (pin 27) H 6 2Y2 enable (pin 26) H 5 2Y1 enable (pin 23) H 4 2Y0 enable (pin 22) H 3 Reserved H 2 Reserved H 1 Reserved H 0 Reserved H
†
When the value of the bit is high, the output is enabled. When the value of the bit is low, the output is forced to a low state. The default value of all bits is high.
I2C BYTE 2-BIT DEFINITION
†
BIT
DEFINITION DEFAULT VALUE
7 3Y1 enable (pin 18) H 6 3Y0 enable (pin 11) H 5 Reserved H 4 Reserved H 3 Reserved H 2 Reserved H 1 Reserved H 0 Reserved H
†
When the value of the bit is high, the output is enabled. When the value of the bit is low, the output is forced to a low state. The default value of all bits is high.
CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(SCLOCK, SDATA) (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(SDATA) (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO –0.5 V to VCC +0.5 V. . . Current into any output in the low state (except SDATA), I
O
48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into SDATA in the low state, IO 12 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) (SCLOCK) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) (SDATA) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2) 120 °C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.
recommended operating conditions (see Note 3)
MIN TYP MAX UNIT
V
CC
3.3-V core supply voltage 3.135 3.465 V A, OE 2 VCC+0.3 V
V
IH
High-level input voltage
SDATA, SCLOCK (see Note 3)
2.2 5.5 V
A, OE –0.3 0.8 V
V
IL
Low-level input voltage
SDATA, SCLOCK (see Note 3)
0 1.04 V
I
OH
High-level output current Y outputs –24 mA
I
OL
Low-level output current Y outputs 24 mA
R
I
Input resistance to V
CC
SDATA, SCLOCK (see Note 3)
140 kΩ
f
(SCL)
SCLOCK frequency 100 kHz
t
(BUS)
Bus free time 4.7 µs
t
su(START)
STAR T setup time 4.7 µs
t
h(START)
STAR T hold time 4 µs
t
w(SCLL)
SCLOCK low pulse duration 4.7 µs
t
w(SCLH)
SCLOCK high pulse duration 4 µs
t
r(SDATA)
SDATA input rise time 1000 ns
t
f(SDATA)
SDATA input fall time 300 ns
t
su(SDATA)
SDATA setup time 250 ns
t
h(SDATA)
SDATA hold time 0 ns
t
su(STOP)
STOP setup time 4 µs
T
A
Operating free-air temperature 0 70 °C
NOTE 3: The CMOS-level inputs fall within these limits: VIH min = 0.7 × VCC and VIL max = 0.3 × VCC.
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
5
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IK
Input clamp voltage VCC = 3.135 V , II = –18 mA –1.2 V
V
OH
High-level output voltage Y outputs VCC = 3.135 V , IOH = –1 mA 2.4 V
Y outputs VCC = 3.135 V , IOL = 1 mA 0.4
V
OL
Low-level output voltage
IOL = 3 mA 0.1 0.4
V
SDATA
V
CC
= 3.
135 V
IOL = 6 mA 0.2 0.6
SDATA VCC = 3.135 V , VO = VCC MAX 20 µA
p
VCC = 3.135 V , VO = 2 V –54 –126
IOHHigh-level output current
Y outputs
VCC = 3.3 V, VO = 2.6 V –60
mA VCC = 3.465 V , VO = 3.135 V –21 –46 VCC = 3.135 V , VO = 1 V 49 118
I
OL
Low-level output current Y outputs
VCC = 3.3 V, VO = 0.7 V 58
mA VCC = 3.465 V , VO = 0.4 V 23 53
A 5
I
IH
High-level input current
OE
VCC = 3.465 V , VI = V
CC
20
µA
SCLOCK, SDATA 20 A –5
I
IL
Low-level input current
OE
VCC = 3.465 V , VI = GND
–10
–50
µA
SCLOCK, SDATA –10 –50
I
OZ
High-impedance-state output current VCC = 3.465 V , VO = 3.465 V or 0 ±10 µA
I
off
Off-state current SCLOCK, SDATA VCC = 0, VI = 0 V to 5.5 V 50 µA
I
CC
Supply current VCC = 3.465 V , IO = 0 0.2 0.5 mA
∆I
CC
Change in supply current
VCC = 3.135 V to 3.465 V , One input at VCC – 0.6 V, All other inputs at VCC or GND
500 µA
C
i
Input capacitiance VI = VCC or GND, VCC = 3.3 V 4 pF
C
o
Output capacitance VO = VCC or GND, VCC = 3.3 V 6 pF
C
I/O
SDATA I/O capacitance V
I/O
= VCC or GND, VCC = 3.3 V 7 pF
CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
6
switching characteristics over recommended operating conditions
PARAMETER FROM TO TEST CONDITIONS MIN MAX UNIT
A Y 1.2 3.6 ns
t
PLH
Low-to-high level propagation delay time
SCLOCK↓
SDATA
valid
VCC = 3.3 V ±0.185 V , See Figure 3
2 µs
t
PLH
Low-to-high level propagation delay time SDATA↑ Y
VCC = 3.3 V ±0.185 V , See Figure 3
150 ns
A Y 1.2 3.6 ns
t
PHL
High-to-low level propagation delay time
SCLOCK↓
SDATA
valid
VCC = 3.3 V ±0.185 V , See Figure 3
2 µs
t
PHL
High-to-low level propagation delay time SDATA↑ Y
VCC = 3.3 V ±0.185 V , See Figure 3
150 ns
t
PZH
Enable time to the high level
1 4.7
t
PZL
Enable time to the low level
OE
Y
1 4.7
ns
t
PHZ
Disable time from the high level
1 4.7
t
PLZ
Disable time from the low level
OE
Y
1 4.7
ns
t
sk(o)
Skew time A Y 250 ps
t
sk(p)
Skew time A Y 500 ps
t
sk(pr)
Skew time A Y 1 ns
t
r
Rise time Y 0.5 1.3 ns Rise time (see Note 4 and
CL = 10 pF 6
t
r
(
Figure 3)
SDATA
CL = 400 pF 250
ns
t
f
Fall time Y 0.5 1.3 ns Fall time (see Note 4 and
CL = 10 pF 20
t
f
(
Figure 3)
SDATA
CL = 400 pF 250
ns
NOTE 4: This parameter has a lower limit than BUS specification. This allows use of series resistors for current spike protection.
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
7
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR tpd AND t
sk
S1
6 V
Open
GND
500 Ω
500 Ω
TEST
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
S1
Open
6 V
GND
Output Enable
(high-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
≈ 3 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
V
CC
3 V
0 V
1.5 V 1.5 V
t
w
Input
VOLTAGE WA VEFORMS
VOLTAGE WA VEFORMS
VOLTAGE WA VEFORMS
t
PLH
t
PHL
Output
1.5 V 1.5 V
3 V
0 V
1.5 V
V
OH
V
OL
Input
0.4 V
2.4 V
t
r
t
f
0.4 V
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR tr AND t
f
2.4 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
8
PARAMETER MEASUREMENT INFORMATION
A
1Y0
t
PHL1
t
PLH1
1Y1
t
PHL2
t
PLH2
2Y3
t
PHL8
t
PLH8
t
PHL3
t
PLH3
1Y2
1Y3
t
PHL4
t
PLH4
2Y0
t
PHL5
t
PLH5
2Y1
t
PHL6
t
PLH6
2Y2
t
PHL7
t
PLH7
3Y0
t
PHL9
t
PLH9
3Y1
t
PLH10
t
PHL10
NOTES: A. Output skew, t
sk(o)
, is calculated as the greater of:
– The difference between the fastest and slowest of t
PLHn
(n = 1:10)
– The difference between the fastest and slowest of t
PHLn
(n = 1:10)
B. Pulse skew, t
sk(p)
, is calculated as the greater of |t
PLHn
– t
PHLn
| (n = 1:10).
C. Process skew, t
sk(pr)
, is calculated as the greater of:
– The difference between the fastest and slowest of t
PLHn
(n = 1:10) across multiple devices under identical operating conditions
– The difference between the fastest and slowest of t
PHLn
(n = 1:10) across multiple devices under identical operating conditions
Figure 2. Waveforms for Calculation of t
sk(o)
, t
sk(p)
, t
sk(pr)
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
9
PARAMETER MEASUREMENT INFORMATION
DUT
RL = 1 kΩ
VO = 3.3 V
CL = 10 pF or
CL = 400 pF
GND
t
su(START)
t
(BUS)
t
r(SDATA)
t
h(START)
t
su(SDATA)
t
h(SDATA)
t
f
t
r
t
w(SCLL)
t
w(SCLH)
t
su(START)
t
PHL
t
PLH
0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
Stop Condition
t
su(STOP)
Repeat Start
Condition
(see Note A)
Start or Repeat Start Condition
SCLOCK
SDATA
Start
Condition
(S)
Bit 7 MSB
Bit 6
Bit 0
LSB
(R/W)
Acknowledge
(A)
Stop
Condition
(P)
4 to 6 Bytes for Complete Device
Programming
TEST CIRCUIT
VOLTAGE WA VEFORMS
t
f(SDATA)
BYTE DESCRIPTION
1 I2C address 2 Command (dummy value, ignored) 3 Byte count (dummy value, ignored) 4 I2C data byte 0 5 I2C data byte 1 6 I2C data byte 2
NOTES: A. The repeat start condition is not supported.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 kHz, ZO = 50 Ω, tr ≥ 10 ns, tf≥ 10 ns.
Figure 3. Propagation Delay Times, t
r
and t
f
CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
10
MECHANICAL INFORMATION
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040065 /C 10/95
28 PIN SHOWN
Gage Plane
8,20 7,40
0,15 NOM
0,63
1,03
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60 5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65
M
0,15
0°–8°
0,10
3,30
8
2,70
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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