Texas Instruments CDC319DBR Datasheet
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
High-Speed, Low-Skew 1-to-10 Clock Buffer
for SDRAM (Synchronous DRAM) Clock
Buffering Applications
D
Output Skew, t
sk(o)
, Less Than 250 ps
D
Pulse Skew, t
sk(p)
, Less Than 500 ps
D
Supports up to Two Unbuffered SDRAM
DIMMs (Dual Inline Memory Modules)
D
I2C Serial Interface Provides Individual
Enable Control for Each Output
D
Operates at 3.3 V
D
Distributed VCC and Ground Pins Reduce
Switching Noise
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D
Packaged in 28-Pin Shrink Small Outline
(DB) Package
description
The CDC319 is a high-performance clock buffer that distributes one input (A) to 10 outputs (Y) with minimum
skew for clock distribution. The CDC319 operates from a 3.3-V power supply , and is characterized for operation
from 0°C to 70°C.
The device provides a standard mode (100K-bits/s) I2C serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs
(SDATA and SCLOCK) provide integrated pullup resistors (typically 140 kΩ) and are 5-V tolerant.
Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,
random access of the registers is not supported).
The CDC319 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
1Y0
1Y1
GND
V
CC
1Y2
1Y3
GND
A
V
CC
3Y0
GND
V
CC
SDATA
V
CC
2Y3
2Y2
GND
V
CC
2Y1
2Y0
GND
OE
V
CC
3Y1
GND
GND
SCLOCK
DB PACKAGE
(TOP VIEW)
Intel is a trademark of Intel Corporation
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
OE A 1Y0–1Y3 2Y0–2Y3 3Y0–3Y1
L X Hi-Z Hi-Z Hi-Z
H L L L L
H H H
†
H
†
H
†
†
The function table assumes that all outputs are enabled via the appropriate I2C
configuration register bit. If the output is disabled via the appropriate configuration bit,
then the output is driven to a low state, regardless of the state of the A input.
logic diagram (positive logic)
1Y0–1Y3
2Y0–2Y3
3Y0 – 3Y1
OE
SDATA
SCLOCK
A
I2C
Register
Space
I2C
20
14
15
9
2, 3, 6, 7
22, 23, 26, 27
11, 18
10
/
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
1Y0–1Y3 2, 3, 6, 7 O 3.3-V SDRAM byte 0 clock outputs
2Y0–2Y3
22, 23, 26, 27 O 3.3-V SDRAM byte 1 clock outputs
3Y0–3Y1
11, 18 O 3.3-V clock outputs provided for feedback control of external PLLs (phase-locked loops)
A
9 I Clock input
OE
20 I
Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal
140-kΩ pullup resistor is internally integrated.
SCLOCK
15 I I2C serial clock input. A nominal 140-kΩ pullup resistor is internally integrated.
SDATA
14 I/O
Bidirectional I2C serial data input/output. A nominal 140-kΩ pullup resistor is internally
integrated.
GND
4, 8, 12, 16,
17, 21, 25
Ground
V
CC
1, 5, 10, 13,
19, 24, 28
3.3-V power supply
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I2C DEVICE ADDRESS
A7
A6 A5 A4 A3 A2 A1 A0 (R/W)
H H L H L L H —
I2C BYTE 0-BIT DEFINITION
†
BIT
DEFINITION DEFAULT VALUE
7 Reserved H
6 Reserved H
5 Reserved H
4 Reserved H
3 1Y3 enable (pin 7) H
2 1Y2 enable (pin 6) H
1 1Y1 enable (pin 3) H
0 1Y0 enable (pin 2) H
†
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
I2C BYTE 1-BIT DEFINITION
†
BIT
DEFINITION DEFAULT VALUE
7 2Y3 enable (pin 27) H
6 2Y2 enable (pin 26) H
5 2Y1 enable (pin 23) H
4 2Y0 enable (pin 22) H
3 Reserved H
2 Reserved H
1 Reserved H
0 Reserved H
†
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
I2C BYTE 2-BIT DEFINITION
†
BIT
DEFINITION DEFAULT VALUE
7 3Y1 enable (pin 18) H
6 3Y0 enable (pin 11) H
5 Reserved H
4 Reserved H
3 Reserved H
2 Reserved H
1 Reserved H
0 Reserved H
†
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(SCLOCK, SDATA) (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(SDATA) (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO –0.5 V to VCC +0.5 V. . .
Current into any output in the low state (except SDATA), I
O
48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into SDATA in the low state, IO 12 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) (SCLOCK) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) (SDATA) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2) 120 °C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
MIN TYP MAX UNIT
V
CC
3.3-V core supply voltage 3.135 3.465 V
A, OE 2 VCC+0.3 V
V
IH
High-level input voltage
SDATA, SCLOCK
(see Note 3)
2.2 5.5 V
A, OE –0.3 0.8 V
V
IL
Low-level input voltage
SDATA, SCLOCK
(see Note 3)
0 1.04 V
I
OH
High-level output current Y outputs –24 mA
I
OL
Low-level output current Y outputs 24 mA
R
I
Input resistance to V
CC
SDATA, SCLOCK
(see Note 3)
140 kΩ
f
(SCL)
SCLOCK frequency 100 kHz
t
(BUS)
Bus free time 4.7 µs
t
su(START)
STAR T setup time 4.7 µs
t
h(START)
STAR T hold time 4 µs
t
w(SCLL)
SCLOCK low pulse duration 4.7 µs
t
w(SCLH)
SCLOCK high pulse duration 4 µs
t
r(SDATA)
SDATA input rise time 1000 ns
t
f(SDATA)
SDATA input fall time 300 ns
t
su(SDATA)
SDATA setup time 250 ns
t
h(SDATA)
SDATA hold time 0 ns
t
su(STOP)
STOP setup time 4 µs
T
A
Operating free-air temperature 0 70 °C
NOTE 3: The CMOS-level inputs fall within these limits: VIH min = 0.7 × VCC and VIL max = 0.3 × VCC.
Loading...