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CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
D
High-Speed, Low-Skew 1-to-10 Clock Buffer
for SDRAM (Synchronous DRAM) Clock
Buffering Applications
D
Output Skew, t
D
Pulse Skew, t
D
Supports up to Two Unbuffered SDRAM
, Less Than 250 ps
sk(o)
, Less Than 500 ps
sk(p)
DIMMs (Dual Inline Memory Modules)
D
I2C Serial Interface Provides Individual
Enable Control for Each Output
D
Operates at 3.3 V
D
Distributed VCC and Ground Pins Reduce
Switching Noise
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D
Packaged in 28-Pin Shrink Small Outline
V
CC
1Y0
1Y1
GND
V
CC
1Y2
1Y3
GND
V
CC
3Y0
GND
V
CC
SDATA
A
DB PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
2Y3
2Y2
GND
V
2Y1
2Y0
GND
OE
V
3Y1
GND
GND
SCLOCK
(DB) Package
description
The CDC319 is a high-performance clock buffer that distributes one input (A) to 10 outputs (Y) with minimum
skew for clock distribution. The CDC319 operates from a 3.3-V power supply , and is characterized for operation
from 0°C to 70°C.
The device provides a standard mode (100K-bits/s) I2C serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs
(SDATA and SCLOCK) provide integrated pullup resistors (typically 140 kΩ) and are 5-V tolerant.
CC
CC
CC
Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,
random access of the registers is not supported).
The CDC319 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a trademark of Intel Corporation
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
CDC319
I/O
DESCRIPTION
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
SCAS590 – DECEMBER 1997
logic diagram (positive logic)
2
C CONTROL INTERFACE
INPUTS
OE A 1Y0–1Y3 2Y0–2Y3 3Y0–3Y1
L X Hi-Z Hi-Z Hi-Z
H L L L L
H H H
†
The function table assumes that all outputs are enabled via the appropriate I2C
configuration register bit. If the output is disabled via the appropriate configuration bit,
then the output is driven to a low state, regardless of the state of the A input.
20
OE
FUNCTION TABLE
†
OUTPUTS
†
H
†
H
SDATA
SCLOCK
14
I2C
I2C
15
9
A
Register
Space
10
/
Terminal Functions
TERMINAL
NAME NO.
1Y0–1Y3 2, 3, 6, 7 O 3.3-V SDRAM byte 0 clock outputs
2Y0–2Y3
3Y0–3Y1
A
OE
SCLOCK
SDATA
GND
V
CC
22, 23, 26, 27 O 3.3-V SDRAM byte 1 clock outputs
11, 18 O 3.3-V clock outputs provided for feedback control of external PLLs (phase-locked loops)
9 I Clock input
20 I
15 I I2C serial clock input. A nominal 140-kΩ pullup resistor is internally integrated.
14 I/O
4, 8, 12, 16,
17, 21, 25
1, 5, 10, 13,
19, 24, 28
Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal
140-kΩ pullup resistor is internally integrated.
Bidirectional I2C serial data input/output. A nominal 140-kΩ pullup resistor is internally
integrated.
Ground
3.3-V power supply
2, 3, 6, 7
22, 23, 26, 27
11, 18
1Y0–1Y3
2Y0–2Y3
3Y0 – 3Y1
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
I2C DEVICE ADDRESS
A6 A5 A4 A3 A2 A1 A0 (R/W)
A7
H H L H L L H —
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
I2C BYTE 0-BIT DEFINITION
BIT
7 Reserved H
6 Reserved H
5 Reserved H
4 Reserved H
3 1Y3 enable (pin 7) H
2 1Y2 enable (pin 6) H
1 1Y1 enable (pin 3) H
0 1Y0 enable (pin 2) H
†
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
BIT
7 2Y3 enable (pin 27) H
6 2Y2 enable (pin 26) H
5 2Y1 enable (pin 23) H
4 2Y0 enable (pin 22) H
3 Reserved H
2 Reserved H
1 Reserved H
0 Reserved H
†
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
DEFINITION DEFAULT VALUE
I2C BYTE 1-BIT DEFINITION
DEFINITION DEFAULT VALUE
†
†
I2C BYTE 2-BIT DEFINITION
BIT
7 3Y1 enable (pin 18) H
6 3Y0 enable (pin 11) H
5 Reserved H
4 Reserved H
3 Reserved H
2 Reserved H
1 Reserved H
0 Reserved H
†
When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DEFINITION DEFAULT VALUE
†
3
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
SCAS590 – DECEMBER 1997
2
C CONTROL INTERFACE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Input voltage range, V
Output voltage range, V
Voltage range applied to any output in the high-impedance or power-off state, VO –0.5 V to VCC +0.5 V. . .
Current into any output in the low state (except SDATA), I
Current into SDATA in the low state, IO 12 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) (SCLOCK) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) (SDATA) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(SCLOCK, SDATA) (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(SDATA) (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 2) 120 °C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
MIN TYP MAX UNIT
V
CC
V
IH
V
IL
I
OH
I
OL
R
I
f
(SCL)
t
(BUS)
t
su(START)
t
h(START)
t
w(SCLL)
t
w(SCLH)
t
r(SDATA)
t
f(SDATA)
t
su(SDATA)
t
h(SDATA)
t
su(STOP)
T
A
NOTE 3: The CMOS-level inputs fall within these limits: VIH min = 0.7 × VCC and VIL max = 0.3 × VCC.
3.3-V core supply voltage 3.135 3.465 V
A, OE 2 VCC+0.3 V
High-level input voltage
Low-level input voltage
High-level output current Y outputs –24 mA
Low-level output current Y outputs 24 mA
Input resistance to V
SCLOCK frequency 100 kHz
Bus free time 4.7 µs
STAR T setup time 4.7 µs
STAR T hold time 4 µs
SCLOCK low pulse duration 4.7 µs
SCLOCK high pulse duration 4 µs
SDATA input rise time 1000 ns
SDATA input fall time 300 ns
SDATA setup time 250 ns
SDATA hold time 0 ns
STOP setup time 4 µs
Operating free-air temperature 0 70 °C
CC
SDATA, SCLOCK
(see Note 3)
A, OE –0.3 0.8 V
SDATA, SCLOCK
(see Note 3)
SDATA, SCLOCK
(see Note 3)
2.2 5.5 V
0 1.04 V
140 kΩ
†
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SDATA
V
135 V
IOHHigh-level output current
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Input clamp voltage VCC = 3.135 V, II = –18 mA –1.2 V
IK
V
High-level output voltage Y outputs VCC = 3.135 V, IOH = –1 mA 2.4 V
OH
Y outputs VCC = 3.135 V, IOL = 1 mA 0.4
V
Low-level output voltage
OL
SDATA VCC = 3.135 V, VO = VCC MAX 20 µA
p
I
Low-level output current Y outputs
OL
I
High-level input current
IH
I
Low-level input current
IL
I
High-impedance-state output current VCC = 3.465 V, VO = 3.465 V or 0 ±10 µA
OZ
I
Off-state current SCLOCK, SDATA VCC = 0, VI = 0 V to 5.5 V 50 µA
off
I
Supply current VCC = 3.465 V, IO = 0 0.2 0.5 mA
CC
∆I
Change in supply current
CC
C
Input capacitiance VI = VCC or GND, VCC = 3.3 V 4 pF
i
C
Output capacitance VO = VCC or GND, VCC = 3.3 V 6 pF
o
C
SDATA I/O capacitance V
I/O
Y outputs
A 5
OE
SCLOCK, SDATA 20
A –5
OE
SCLOCK, SDATA –10 –50
= 3.
CC
VCC = 3.135 V, VO = 2 V –54 –126
VCC = 3.3 V, VO = 2.6 V –60
VCC = 3.465 V, VO = 3.135 V –21 –46
VCC = 3.135 V, VO = 1 V 49 118
VCC = 3.3 V, VO = 0.7 V 58
VCC = 3.465 V, VO = 0.4 V 23 53
VCC = 3.465 V, VI = V
VCC = 3.465 V, VI = GND
VCC = 3.135 V to 3.465 V,
One input at VCC – 0.6 V,
All other inputs at VCC or GND
= VCC or GND, VCC = 3.3 V 7 pF
I/O
IOL = 3 mA 0.1 0.4
IOL = 6 mA 0.2 0.6
CC
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
20
–10
–50
500 µA
V
mA
mA
µA
µA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
CDC319
OE
Y
ns
OE
Y
ns
t
(
SDATA
ns
t
(
SDATA
ns
1-LINE TO 10-LINE CLOCK DRIVER
PLH
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
sk(o)
sk(p)
sk(pr)
r
r
f
f
2
C CONTROL INTERFACE
PARAMETER FROM TO TEST CONDITIONS MIN MAX UNIT
A Y 1.2 3.6 ns
Low-to-high level propagation delay time
Low-to-high level propagation delay time SDATA↑ Y
High-to-low level propagation delay time
High-to-low level propagation delay time SDATA↑ Y
Enable time to the high level
Enable time to the low level
Disable time from the high level
Disable time from the low level
Skew time A Y 250 ps
Skew time A Y 500 ps
Skew time A Y 1 ns
Rise time Y 0.5 1.3 ns
Rise time (see Note 4 and
Figure 3)
Fall time Y 0.5 1.3 ns
Fall time (see Note 4 and
Figure 3)
SCLOCK↓
A Y 1.2 3.6 ns
SCLOCK↓
SDATA
valid
SDATA
valid
VCC = 3.3 V ±0.185 V ,
See Figure 3
VCC = 3.3 V ±0.185 V ,
See Figure 3
VCC = 3.3 V ±0.185 V ,
See Figure 3
VCC = 3.3 V ±0.185 V ,
See Figure 3
1 4.7
1 4.7
1 4.7
1 4.7
CL = 10 pF 6
CL = 400 pF 250
CL = 10 pF 20
CL = 400 pF 250
WITH I
SCAS590 – DECEMBER 1997
switching characteristics over recommended operating conditions
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTE 4: This parameter has a lower limit than BUS specification. This allows use of series resistors for current spike protectio n.
2 µs
150 ns
2 µs
150 ns
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
PARAMETER MEASUREMENT INFORMATION
500 Ω
500 Ω
LOAD CIRCUIT FOR tpd AND t
From Output
Under Test
CL = 30 pF
(see Note A)
sk
S1
6 V
GND
Open
Input
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
1.5 V 1.5 V
2
C CONTROL INTERFACE
TEST
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
w
VOLTAGE WAVEFORMS
SCAS590 – DECEMBER 1997
S1
Open
6 V
GND
3 V
0 V
LOAD CIRCUIT FOR tr AND t
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
2.4 V
0.4 V
t
r
VOLTAGE WAVEFORMS
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
1.5 V
2.4 V
t
f
Figure 1. Load Circuit and Voltage Waveforms
f
t
PHL
0.4 V
3 V
0 V
V
V
OH
OL
Output
Enable
(high-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
VOLTAGE WAVEFORMS
t
PLZ
1.5 V
t
PHZ
1.5 V
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
V
CC
0 V
≈ 3 V
V
OL
V
OH
≈ 0 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
SCAS590 – DECEMBER 1997
2
C CONTROL INTERFACE
PARAMETER MEASUREMENT INFORMATION
A
1Y0
t
PHL1
1Y1
t
PHL2
1Y2
t
PHL3
1Y3
t
PHL4
2Y0
t
PHL5
2Y1
t
PHL6
2Y2
t
PHL7
2Y3
t
PHL8
3Y0
t
PHL9
3Y1
t
PHL10
t
PLH1
t
PLH2
t
PLH3
t
PLH4
t
PLH5
t
PLH6
t
PLH7
t
PLH8
t
PLH9
t
PLH10
NOTES: A. Output skew, t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
B. Pulse skew, t
C. Process skew, t
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
, is calculated as the greater of:
sk(o)
, is calculated as the greater of |t
sk(p)
, is calculated as the greater of:
sk(pr)
PLHn
(n = 1:10)
PLHn
(n = 1:10)
PHLn
– t
PHLn
(n = 1:10) across multiple devices under identical operating conditions
PLHn
(n = 1:10) across multiple devices under identical operating conditions
PHLn
Figure 2. Waveforms for Calculation of t
| (n = 1:10).
sk(o)
, t
sk(p)
, t
sk(pr)
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
PARAMETER MEASUREMENT INFORMATION
VO = 3.3 V
RL = 1 kΩ
DUT
CL = 10 pF or
CL = 400 pF
GND
TEST CIRCUIT
2
C CONTROL INTERFACE
SCAS590 – DECEMBER 1997
SCLOCK
t
SDATA
t
su(START)
(BUS)
t
f(SDATA)
t
h(START)
Start or
Repeat Start
Condition
Start
Condition
(S)
t
w(SCLL)
t
r
Bit 7
MSB
t
f
t
r(SDATA)
t
su(SDATA)
BYTE DESCRIPTION
1 I2C address
2 Command (dummy value, ignored)
3 Byte count (dummy value, ignored)
4 I2C data byte 0
5 I2C data byte 1
6 I2C data byte 2
NOTES: A. The repeat start condition is not supported.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 kHz, ZO = 50 Ω, tr ≥ 10 ns, tf≥ 10 ns.
4 to 6 Bytes for Complete Device
t
w(SCLH)
Bit 6
Programming
t
h(SDATA)
VOLTAGE WAVEFORMS
Bit 0
LSB
(R/W)
t
PHL
Repeat Start
(see Note A)
Acknowledge
Condition
(A)
t
PLH
Condition
t
su(START)
t
su(STOP)
Stop Condition
Stop
(P)
0.7 V
0.3 V
0.7 V
0.3 V
CC
CC
CC
CC
Figure 3. Propagation Delay Times, t
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
and t
r
f
9
CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I
SCAS590 – DECEMBER 1997
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
2
C CONTROL INTERFACE
MECHANICAL INFORMATION
0,65
28
1
2,00 MAX
0,38
0,22
15
14
A
0,05 MIN
0,15
5,60
5,00
M
8,20
7,40
Seating Plane
0,10
0,15 NOM
Gage Plane
0°–8°
0,25
1,03
0,63
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
8
3,30
2,70
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /C 10/95
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1998, Texas Instruments Incorporated
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